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2011-09-16ENGR00156850 gpu-viv: add gpu-viv driver sourcerel_imx_2.6.38_11.09.01Richard Zhao
It's vivante driver 4.5.0 (Sep 5, 2011) with freescale changes. Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Acked-by: Lily Zhang
2011-09-16ARM: twd: register clockevents device before enabling PPIWill Deacon
The smp_twd clockevents driver currently enables the local timer PPI before the clockevents device is registered. This can lead to a kernel panic if a spurious timer interrupt is generated before registration has completed since the kernel will treat it as an IPI timer. This patch moves the clockevents device registration before the IRQ unmasking so that we can always handle timer interrupts once they can occur. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-09-16ENGR00156849 MX6Q: add relative clock for BCHHuang Shijie
The BCH needs the pl301_mx6qperl_bch clock. The BCH will not work if the clock is not enabled. So add it. Signed-off-by: Huang Shijie <b32955@freescale.com>
2011-09-15ENGR00156374 ipuv3: check channel busy while wait disable irqJason Chen
there is chance channel already quit busy before wait disable irq in ipu_disable_channel, so add check during irq wait. this patch also comments f_calc and m_calc fix build warning. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-09-08ENGR00156234 ipuv3: fix cpmem issueJason Chen
sometimes update to cpmem may not correct. make ipu_get_soc more robust. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-09-08ENGR00155147 mx5x mx6x: adjust dma zone max size to 184MJason Chen
adjust dma zone max size to 184M. keep default size as 96M. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-09-08ENGR00155146 ipuv3: use mutex instead of spin lockJason Chen
keep spin lock for irq function, but use mutex replace other splin lock to provide better sync method. Add _ipu_get/put function to check clock enable. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-09-08ENGR00155140 ipuv3: add support of power suspend/resumeJason Chen
add support of power suspend/resume. because IPU has issue of restore current buffer register, this code only work for single buffer mode. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-09-08ENGR00155135-3 ipuv3 dev: add processing driver supportJason Chen
IPU's IC/IRT/VDI modules provide resizing/CSC/combination/de-interlacing support, this patch make all these features into one processing driver. A struct ipu_task is the interface between user and this driver, user just need fill his task struct and queue it through ioctl, then wait ipu hardware finish its job (now only support BLOCKING operation, not support NO_BLOCK operation). Pls refer to inlcude/linux/ipu.h for structure information and unit test for usage. This patch is for ipu driver changes. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-09-08ENGR00155135-2 ipuv3 dev: add processing driver supportJason Chen
IPU's IC/IRT/VDI modules provide resizing/CSC/combination/de-interlacing support, this patch make all these features into one processing driver. A struct ipu_task is the interface between user and this driver, user just need fill his task struct and queue it through ioctl, then wait ipu hardware finish its job (now only support BLOCKING operation, not support NO_BLOCK operation). Pls refer to inlcude/linux/ipu.h for structure information and unit test for usage. This patch is for MSL file change. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-09-08ENGR00155135-1 ipuv3 dev: add processing driver supportJason Chen
IPU's IC/IRT/VDI modules provide resizing/CSC/combination/de-interlacing support, this patch make all these features into one processing driver. A struct ipu_task is the interface between user and this driver, user just need fill his task struct and queue it through ioctl, then wait ipu hardware finish its job (now only support BLOCKING operation, not support NO_BLOCK operation). Pls refer to inlcude/linux/ipu.h for structure information and unit test for usage. This patch is for header file change. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-09-08ENGR00156232 [mx6q]change cpuinfo keywordTony Lin
MX[0-9] is the keyword for multimedia applications, so change the cpuinfo from i.MX 6Quad to MX6 Quad Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-09-07ENGR00155880 USB device: Fix RNDIS Full Speed hang during initializationAnish Trivedi
When setup irq is received, the status phase of the transfer is primed on ep0 before the data phase. The usb requests are added to the list of transfer descriptors (maintained by driver) in reverse of their expected completion order. Completion order is data followed by status, however the list of tds contains status followed by data. Upon completion of the data request, the irq handler proceeds to check the 1st td in the list -- the status request. In full speed mode, the status phase has not yet completed at this time, so the td's ACTIVE bit is still set. This leads irq handler to ignore the completion interrupt without checking the actual td for the data request that caused the interrupt. In high speed mode, this issue does not bear itself out because the status request also completes by the time the irq handler goes to process the data completion interrupt. The simple fix for this issue is to prime the status request AFTER the data request, so that the list of tds maintained by the driver contains the tds in the order of expected completion. Signed-off-by: Anish Trivedi <anish@freescale.com>
2011-09-06ENGR00156153: MX6- Fix bugs in clock code.Ranjani Vaidyanathan
Refer to the ipcg table in the spec to ensure that the parent clocks are set correctly. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-09-05ENGR00155995 [MX6]Adjust default thermal pointAnson Huang
Current thermal reading formula is not accurate, and different board has different value, previous setting of trip point setting is too low, and some boards can reach hot and critical point easily, so change the trip point as below: critical : 50 -> 100 C hot : 40 -> 90 C active : 30 -> 80 C these trip points value can also be changed via echo an value into /sys/class/thermal/thermal_zone0/trip.. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-09-02ENGR00155981: MX6: Fix crash caused by cpufreq during suspend/resumeRanjani Vaidyanathan
Random crashes occur in CPUFREQ code when resuming from suspend. The root cause is due to freeing and allocating of common data structure (frequency table) shared among all the CPUs. Fix the code by ensuring that the common data structure is only created and deleted once. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-09-02ENGR00154436-2 - MXC HDMI: Support complete feature setDanny Nold
- Cleaned up video mode configuration in HDMI driver - Add support for configurable ipu-to-hdmi mappings - Add hotplug support. - Adapt interrupt handling to account for sharing interrupt with HDMI audio - Remove audio configuration - Change code to only use CEA HDMI modes - Add support for AVI InfoFrame - Add aspect ratio to EDID mode data - Add rounding support to IPU pix clk setup - Add powerdown/powerup flow - Support FB notifications - Remove build warnings Signed-off-by: Danny Nold <dannynold@freescale.com>
2011-09-02ENGR00154436-1 - MACH-MX6: MXC HDMI updates to support full feature setDanny Nold
- Corrected logic bug in how GPR registers are set - Add support for configurable ipu-to-hdmi mappings - Add aspect ratio to EDID mode data - Expanded HDMI register field defines - Removed HDMI platform data now handled by HDMI core in MFD Signed-off-by: Danny Nold <dannynold@freescale.com>
2011-09-02ENGR00155958: MX6: Fix bug in setting parent of periph_clkRanjani Vaidyanathan
periph_clk mux should be set only after the periph_clk2 mux is set. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-09-02ENGR00155912 [mx6q]clock: correct pll disable functionTony Lin
pll3 and pll7 have opposite power down bit definition comparing with other plls. so reverse the bit when setting these two plls Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-09-02ENGR00155893 [mx6q]clock: correct set parent functionTony Lin
set periph_clk_sel to derive clock from periph_clk2_clk Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-09-02ENGR00155890 [mx6q] code clean upTony Lin
remove unnecessary '\' Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-09-01ENGR00155845-2 mfd for hdmiAlan Tull
This is a mfd for the internal HDMI Transmitter on i.Mx. It handles resources that are shared by the seperate video and audio drivers. Signed-off-by: Alan Tull <alan.tull@freescale.com>
2011-09-01ENGR00155845-1 mfd for hdmiAlan Tull
This is a mfd for the internal HDMI Transmitter on i.Mx. It handles resources that are shared by the seperate video and audio drivers. Signed-off-by: Alan Tull <alan.tull@freescale.com>
2011-09-01ENGR00155715: MX6: Fix warnings is clock and cpufreq code.Ranjani Vaidyanathan
Fixed warnings in clocks and cpufreq code. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-09-01ENGR00155761 usb-host: fix the buiild warning with upstream reviewing patchPeter Chen
Warning message: /home/b29397/work/projects/linux-2.6-imx/drivers/usb/host/ehci.h: 748: warning: function declaration isn't a prototype Signed-off-by: Peter Chen <peter.chen@freescale.com>
2011-09-01ENGR00155764 usb-host: fix the system hang when access register with clocks OFFPeter Chen
Fix the system hang when access usb registers with usb's clocks are OFF, open the usb clock before visiting the usb registers resolves this problem Signed-off-by: Peter Chen <peter.chen@freescale.com>
2011-09-01ENGR00155759 [MX6]MMDC clock should be always onAnson Huang
1. We should enable mmdc_ch0 clock in init to make its usecount > 0, or ipu's parent is mmdc_ch0, when ipu enable/disable clock, mmdc_ch0 will be also enable/disable, cause system hang when disable. 2. Remove build warning of unuse variable. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-09-01ENGR00155731 [MX6]clock disable should functionAnson Huang
un-comment __clk_disable function and __clk_disable_inwait function. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-09-01ENGR00155612-4 [mx6q]change the delay after clock frequence change to 1msTony Lin
100ms is too long delay, thus it impact other tasks scheduling. for example, nfs reports timeout if two sd card is inserted because the 100ms delay occupies cpu too long. 1ms value is evaluated by IC engineer. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-09-01ENGR00155612-3 [mx6q]add delay after cmd6 for eMMC compatibilityTony Lin
sandisk eMMC4.4 cards need a 1ms delay after cmd6 (switch cmd) which is confirm by sandisk errata. add 1ms delay after cmd6 to provide more robustness and compatiblity of our driver supporting eMMC4.4 cards. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-09-01ENGR00155612-2 [mx6q]dynamically sd pad setting changeTony Lin
call platform callback funtion, if exists, when clock frequency is changed. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-09-01ENGR00155612-1 [mx6q]dynamically sd pad setting changeTony Lin
on mx6q, it supports sd3.0 card with DDR 50MHz, SDR 100Mhz and SDR 200MHz. sd pads have to be changed dynamically for these large scale of clock frequencies. add different pad setting definitions for these clock frequencies under board file, since these settings are really board dependent. add callback funtion in sdhc platform data to give driver approach to change pad setting according to current clock frequency. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-09-01usb: ehci: make HC see up-to-date qh/qtd descriptor ASAPMing Lei
This patch introduces the helper of ehci_sync_mem to flush qtd/qh into memory immediately on some ARM, so that HC can see the up-to-date qtd/qh descriptor asap. This patch fixs one performance bug on ARM Cortex A9 dual core platform, which has been reported on quite a few ARM machines (OMAP4, Tegra 2, snowball...), see details from link of https://bugs.launchpad.net/bugs/709245. The patch has been tested ok on OMAP4 panda A1 board, and the performance of 'dd' over usb mass storage can be increased from 4~5MB/sec to 14~16MB/sec after applying this patch. Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Ming Lei <ming.lei@canonical.com>
2011-09-01ENGR00155627 [MX6]Add thermal cooling deviceAnson Huang
Add anatop thermal cooling device,currently only support secondary CPUs hotplug when temperature is too hot,binding the processor cooling device with anatop thermal zone. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-09-01ENGR00155627-1 [MX6]Add thermal cooling devieAnson Huang
1.Common code of thermal_sys has some bug,could not set the mode via sysfs using echo enable/disabled command; 2.Since the anatop thermal formula still not accurate, in order to help test and adjust the trip point of anatop thermal zone, we add the set trip point temp value into the sysfs interface. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-09-01ENGR00155718 [MX6]CPUs hotplug sometimes failAnson Huang
Sometimes when system very busy,hotplug may fail because CPU0 has no chance to kill secondary CPUs from hardware,secondary CPUs keep enter/exit wfi ,and we have a printk after wfi,that makes CPU0 has no chance to kill secondary CPUs,we should remove this printk. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-09-01ENGR00155611 [mx6q]correct eMMC DDR mode clock settingTony Lin
in uSDHC controller, SDCLKFS field in SYS_CTRL register is defined differently from eSDHC In Single Data Rate mode(DDR_EN bit of MIXERCTRL is '0') Only the following settings are allowed: 80h) Base clock divided by 256 40h) Base clock divided by 128 20h) Base clock divided by 64 10h) Base clock divided by 32 08h) Base clock divided by 16 04h) Base clock divided by 8 02h) Base clock divided by 4 01h) Base clock divided by 2 00h) Base clock divided by 1 While in Dual Data Rate mode(DDR_EN bit of MIXERCTRL is '1') Only the following settings are allowed: 80h) Base clock divided by 512 40h) Base clock divided by 256 20h) Base clock divided by 128 10h) Base clock divided by 64 08h) Base clock divided by 32 04h) Base clock divided by 16 02h) Base clock divided by 8 01h) Base clock divided by 4 00h) Base clock divided by 2 so the clock setting function should be changed to fit the definition Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-08-30ENGR00139280: MX6: Add CPUFREQ supportRanjani Vaidyanathan
Add support for CPUFREQ for SMP system. Added support for 1GHz, 800MHz, 400MHz and 160MHz. Added support for scaling the voltage along with frequency. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-08-30ENGR00153925 MX6Q: Fix EGA touch failure on lvds2 portFrank Li
lvds2 port use i2c3 port. Add EGA i2c register data to i2c port3. but two touch can't work at the same time because irq conflict. Signed-off-by: Frank Li <Frank.Li@freescale.com>
2011-08-30ENGR00139255 MX6Q_BSP ESAI: Add esai recording supportLionel Xu
Add ESAI recording to mx6q platform. To differentiate mx6q and mx53 in codec machine layer code. Signed-off-by: Lionel Xu <R63889@freescale.com>
2011-08-30USB: Mark EHCI LPM functions as __maybe_unusedMaksim Rayskiy
ehci_lpm_set_da and ehci_lpm_check are EHCI 1.1 specific functions which are not used on many platforms but do generate annoying gcc warnings Signed-off-by: Maksim Rayskiy <mrayskiy@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-30ENGR00155396 usb-host: fix below build warningPeter Chen
drivers/usb/host/ehci-hub.c:109: warning: 'ehci_adjust_port_wakeup_flags' defined but not used Signed-off-by: Peter Chen <peter.chen@freescale.com>
2011-08-29ENGR00139255-2 MX6Q_BSP ESAI: Add esai recording supportLionel Xu
Add ESAI recording to mx6q platform. Note: since there is pad conflict between esai record and fec, add a boot argument esai_record to deal with it. This argument is required to enable the record functionality. Signed-off-by: Lionel Xu <R63889@freescale.com>
2011-08-29ENGR00139255-1 MX6Q_BSP ESAI: Add esai recording supportLionel Xu
Add ESAI recording to mx6q platform. Note: since there is pad conflict between esai record and fec, add a boot argument esai_record to deal with it. This argument is required to enable the record functionality. Signed-off-by: Lionel Xu <R63889@freescale.com>
2011-08-29ENGR00155151 imx6q clock: fix ldb and ipu-di clock enable registerJason Chen
ipu2-di should use CCGR3 4&5, ldb_di should use 6&7. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-08-29ENGR00154080 ipuv3: fix clear buffer functionJason Chen
fix clear buffer function. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-08-29ENGR00155145 ipuv3 disp pos: restore pos setting after channel disable.Jason Chen
FG pos need be reset to 0 when channel disable, but it will lost old setting. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-08-29ENGR00153474 ipuv3 split mode: vf and enc task display with errorJason Chen
For split mode, if using vf/enc task, the display is not correct. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-08-29ENGR00155141 ipuv3 split mode: adjust split calculate functionJason Chen
One issue was found in split mode: For input 1024x600, output 1360x768, after stripe calculation, input width and input column are not right. This patch fix this issue. Signed-off-by: Jason Chen <b02280@freescale.com>
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