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[DO NOT INTEGRATE TO MAIN]
Add and enable rear camera sensor.
Support only one sensor for now.
Change-Id: Iee284bca42ffaf1d4b3b6de15caf72324e9c427e
Reviewed-on: http://git-master/r/37135
Tested-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Shail Dave <sdave@nvidia.com>
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[DO NOT INTEGRATE TO MAIN]
Enable rear camera sensor for enterprise board
Change-Id: I9f75f59314c20e67f39b8e131f65cc446e8f9a70
Reviewed-on: http://git-master/r/37134
Tested-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Shail Dave <sdave@nvidia.com>
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Gpio controlling w_disable has changed since Fab3.
Modify it accordingly.
Bug 819563
Cherry picked from main. [DO NOT INTEGRATE TO MAIN]
Change-Id: Ic403d981a742eaa55fbdbb7f0986dee0ff957c31
Reviewed-on: http://git-master/r/37122
Reviewed-by: Rajkumar Jayaraman <rjayaraman@nvidia.com>
Tested-by: Rajkumar Jayaraman <rjayaraman@nvidia.com>
Reviewed-by: Shail Dave <sdave@nvidia.com>
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Change-Id: I07aa6bfdbbb12f7e921f1f1be7136dae8bd8a834
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Following files will show information of DC and hdmi
/sys/kernel/debug/tegradc.[01]/{regs,mode,stats}
/sys/kernel/debug/tegra_hdmi/regs
/sys/devices/nvhost/tegradc.[01]/stats_enable
Bug 827295
Change-Id: I60bcf4454b9ea7d0ed73a6199595b06dbfa32cd7
Reviewed-on: http://git-master/r/32454
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Revert MMC_BLOCK_DEFERRED_RESUME feature from SD driver. The feature
was not implemented thread-safe. Fixing it would require a lot
of locking logic at limited value.
Deferred resume has no effect on eMMC, because eMMC will be used right
after resume. For SD card it only saves power between resume and first
SD card access, which is a limited usecase. It does not save power
on normal SD card idle.
Bug 833034
Change-Id: Ic6c9d751f463ef8135d0cf4c845462598fab774c
Reviewed-on: http://git-master/r/36451
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Alex Courbot <acourbot@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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MMC_BLOCK_DEFERRED_RESUME causes race conditions in the SD/MMC driver,
i.e. mmc_sd_detect() will be called from different threads causing
inconsistent state. Disabling feature for Tegra.
Bug 833034
see http://git-master/r/36254
(cherry picked from commit a8b6bb5de9b9645ecdabc3e954f04898e45e9038)
Change-Id: Iee0e2bb525fcdd5e417d0679697c598ff90cb20f
Reviewed-on: http://git-master/r/36448
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Bug 814896, 820602
Reviewed-on: http://git-master/r/35948
(cherry picked from commit 4b9158b73bd5b5ae9b1059d31e062362d4732064)
Change-Id: I56c9f51bc1d6cbf455795a65d702e62ea5be1522
Reviewed-on: http://git-master/r/36676
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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only tegra2 needs dc underflow reset worker, disable worker if tegra2
support is disabled.
bug 836677
Change-Id: I98ba440f1d93c900fa1ce7d1bfd239e3060c437a
Reviewed-on: http://git-master/r/36597
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Disable HDA related clocks when device is not connected
to HDMI. HDA clocks will be enabled from HDMI driver when
HDMI device is hot plugged.
Bug 820213
Change-Id: I4e6839aab0dc5277b11c415cbb495766f72442b8
Reviewed-on: http://git-master/r/36517
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Niranjan Wartikar <nwartikar@nvidia.com>
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
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Implementation for dsi panel power management
Bug 833709
Bug 793857
Change-Id: Ia13c9b0a4a8a4ec1d802ad56cdbcdc27e5f183d4
Reviewed-on: http://git-master/r/36139
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Tested-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
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Implementation for:
- syncpt for ulpm
- power saving in different components of the controller
- correcting syncpt sequence for BTA
Bug 833709
Bug 793857
Change-Id: I60ff03c64dc46a3dd8e09e1c6d43ab8355b8b649
Reviewed-on: http://git-master/r/36142
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Tested-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
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With the recent switch to having the hid layer handle standard axis
initialization, the Magic Trackpad now reports relative axes. This would
be fine in the normal mode, but the driver puts the device in multitouch
mode where no relative events are generated. Also, userspace software
depends on accurate axis information for device type detection. Thus,
ignoring the relative axes from the Magic Trackpad is best.
Signed-off-by: Chase Douglas <chase.douglas@canonical.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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Let the HID core handle input device setup and HID-compliant reports.
This driver then only has to worry about the non-standard reports.
Signed-off-by: Michael Poole <mdpoole@troilus.org>
Acked-by: Chase Douglas <chase.douglas@canonical.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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Function was returning int where as the return type was void.
Bug 836761
Change-Id: I126c65892acefdbcf7cad7d217662e4957ebaa71
Reviewed-on: http://git-master/r/36279
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Depends on MPU device tree changes as well.
Change-Id: I65e63cec318d17d10589ce1f8c7c50f8470dc704
Reviewed-on: http://git-master/r/36168
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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FPGA platforms require the standard PLL-P frequency. Configure
the clock tables approprately based upon platform type.
Change-Id: I0c39c819cc935715d19ba684d365dcf9a1f2b518
Reviewed-on: http://git-master/r/36150
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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CONFIG_HOTPLUG was inadvertantly used where CONFIG_HOTPLUG_CPU
should have been used.
Change-Id: Ibbc925b01ea64f1b2cfb86c215557357bf9c185a
Reviewed-on: http://git-master/r/35942
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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use FB_BLANK_POWERDOWN on hdmi device in earlysuspend to cause
tegra_dc_disable.
This change applies to enterprise,whistler and ventana.
Fixes bug 835171
Change-Id: I792ab60344667acbdfcbd65a2ba697c2e7b59a78
Reviewed-on: http://git-master/r/35854
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Checks from a fuse whether we have one or two register sets.
- fuse.h/fuse.c: Implement tegra_register_sets()
- nvhost_3dctx.c: Use tegra_register_sets() to determine number of
sets to save.
- dev.c: Create entry /sys/module/nvhost/parameters/register_sets to
return to user space the number of sets.
Change-Id: Ibd9a50cfe77a642335bd85b5814e8fdd8d2c35e6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/29786
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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If defered SD card resume (CONFIG_MMC_BLOCK_DEFERRED_RESUME) is enabled,
PM_POST_SUSPEND handler will never set host->rescan_disable back to 0,
and card detect logic will be disabled forever.
fix missing break
fix incorrect cleanup sequences
Bug 833034
See http://git-master/r/36251
(cherry picked from commit 31d509d8e2e2b7c35da69029f932d35c3995fe36)
Change-Id: Ia0c7b82ac6590fa2ea05de13c32d699604718176
Reviewed-on: http://git-master/r/36447
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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instead of checking for NULL, IS_ERR() should
be used to check the validity of a clock handle
Reviewed-on: http://git-master/r/#change,35619
(cherry picked from commit cfb16f57d0a846dba4cd5d6a87c05dcb8efd188d)
Change-Id: If844a166deabc7e67c9af69e4d05f59757773895
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/36218
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Some windows host drivers require this small delay in order to properly
detect the tegra device. This patch ensures correct detection in all
cases.
Workaround for bug 814907
(cherry picked from commit 53c4f00605677c8de4311586c4f75903978cbd94)
Reviewed-on: http://git-master/r/35613
(cherry picked from commit 126a2fca500004a4b03ea377da000e8972efaed6)
Change-Id: Iaff87cbc2fe3332f9cb27a08e1156015fc66a3c5
Reviewed-on: http://git-master/r/36211
Reviewed-by: Alex Courbot <acourbot@nvidia.com>
Tested-by: Alex Courbot <acourbot@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Change-Id: I54da4d7547a0c2482805c4a3bf903a9559b36ca3
Reviewed-on: http://git-master/r/36201
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
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Updated Tegra3 EMC DFS table to match new PLLP base frequency
(408MHz) and enable power saving features.
Bug 836260
Change-Id: Ie85cda67804ea29a0df475464020b1e76176ea3b
Reviewed-on: http://git-master/r/36049
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
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Change-Id: I32e2e58d61305366853d73dc30be3934d3e45355
Reviewed-on: http://git-master/r/35941
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
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Change-Id: I6dbc601cde3297e7c6fd63600c588cb3774271b8
Reviewed-on: http://git-master/r/35940
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
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Change-Id: I6657cfa42019a833824cad669d10d407bd598c0e
Reviewed-on: http://git-master/r/35935
Reviewed-by: Ping Lai <plai@nvidia.com>
Reviewed-by: Vivek Aseeja <vaseeja@nvidia.com>
Tested-by: Krishna Monian <kmonian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
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Setting TEGRA_WAKE_KBC_EVENT as a wakeupsource in
enterprise_suspend_data structure.
Change-Id: Idb02699c6bdaec9abfc5525688351c2f3ad8da31
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/35876
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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this will allow to control the sclk from the respective
driver owners of these clocks
Change-Id: I69b2dfbbd68cff4cd87c65e2aed6cd9600e72668
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/35873
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
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This reverts commit 141f664e2b5052d7fcd57c5287ae1e27db0f658b.
The original commit
(a) renamed con_id for shared user clock from "sclk" to "hclk"
(b) increased requested clock rate
Since there is no "hclk" shared bus in tegra clock tree, this
effectively disabled busy hint from USB driver, and actually
reduced the bus clock (instead of increasing it).
Bug 821986 sated that clock effect has not been tested.
Reverting it would at least restore 80MHz bus clock limit required
for USB operations.
Change-Id: I280340699df96c1cd21e3d8c0a65b5f89a7607b4
Reviewed-on: http://git-master/r/36200
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
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Change-Id: I5e037ecd2c1be4fc7b5f5c514abd1fc84a491cc4
Reviewed-on: http://git-master/r/35751
Reviewed-by: Yun Long <ylong@nvidia.com>
Tested-by: Yun Long <ylong@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
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The E1291-A04 power rails are different then the A02/A03 version of E1291.
Supporting the A04 power rails properly.
Change-Id: I4c7dc0afa5b6bb1a7350418ef07f4ee7192cff30
Reviewed-on: http://git-master/r/35722
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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We need TCA6416 for E1187/E1188. It is not on E1198/E1291 boards.
So for E1198/E1291, we can return without doing anything in
cardhu_ov5650_late_init.
Bug: 822234
Change-Id: I25e0af2ed0da70ac33470b282f4446b6a9471be8
Reviewed-on: http://git-master/r/35707
Tested-by: Abhiruchi Birajdar <abirajdar@nvidia.com>
Reviewed-by: Gary Zhang <garyz@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Frank Chen <frankc@nvidia.com>
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If set voltage vddio rail fails, vddio pointer remains as non-null.
This causes error for vddio rail regulator_disable call during suspend.
In error path vddio rail is reset to NULL to prevent above problem.
Bug 836172
Change-Id: I48b3cb3b9792f54f2661b13b95299d8caac4e144
Reviewed-on: http://git-master/r/35621
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
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This reverts commit ba038f38e6c0edd77dc65c28324ddd18185389fb.
It caused regression in camcoder usecase.
fixes bug 835818
Change-Id: I008a27d70b4e7066ec12f7d66d9d60e66ace0447
Reviewed-on: http://git-master/r/35434
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Tested-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: Zhijun He <zhhe@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
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Do not check PLLX lock bit on PLLX sanity check, since it might not be in the
lock state yet.
Change-Id: I607210330dc355a1359dc856a192bd4163df4cb3
Reviewed-on: http://git-master/r/35261
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Enable MPE power gating, but keep it powered on when userspace has a
channel open.
Bug 809847
Change-Id: I30a297c079c0911fdaf9de528e3d5bf4a7cc1d72
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/32179
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Fixes "warning: function declaration isn't a prototype".
Change-Id: Ifbf00f2294413193ff5a7d652252841072466779
Reviewed-on: http://git-master/r/35441
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Enterprise defconfig has been updated to include
new changes added by MPU v3.3.4.
config changed: CONFIG_MPU_SENSORS_TIMERIRQ=y
BUG 836539
Change-Id: I2d6f1e790de806733fb89aa3414307c58a0d2a65
Reviewed-on: http://git-master/r/35426
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Change-Id: I524435fefffeb0b62dd21d34d0523103ab01815f
Reviewed-on: http://git-master/r/35292
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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- "avp_lib: Successfully unloaded '%s'" was duplicated.
Change-Id: I32c6d0cdd2bd5d1529e3596b4bc6e3220bc498de
Reviewed-on: http://git-master/r/34609
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Change-Id: I38b9752adc9e927935fe7ffe5590c41577a45809
Reviewed-on: http://git-master/r/34381
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Made changes in the code to include PM269's Keypad Functionality
Bug 833265
Change-Id: Iec996d9c0f8fe03a8f28278b0dfc80c699d14d26
Reviewed-on: http://git-master/r/34364
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Adds userspace control for 3d barrier on 3d panel found on enterprise.
Provides 2 sysfs files:
/sys/devices/nvhost/tergradc/stereo_mode
/sys/devices/nvhost/tergradc/stereo_orientation
These are used to enable/disable 3d barrier and control it's
orientation, respectively.
Change-Id: I580f0992c19cbee9a695bac9bef503c9888abc83
Reviewed-on: http://git-master/r/32575
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Enables performance events and OProfile support in Android configs.
In minimal "savedefconfig" format.
Bug 796624.
Change-Id: I2d88d3eeaa3bfe56ab8f77d55bf40066b1e08d52
Reviewed-on: http://git-master/r/31163
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
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Change-Id: I4d7f1673f12fe048b48224359fbf0d27ad0d7433
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/35414
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Updated Tegra3 EMC clock change procedure with periodic qrst support,
and EMC DFS tables.
Bug 836260
Change-Id: Ia3d7f58bf61ee6e695ab62f934388d4c1b4d2079
Reviewed-on: http://git-master/r/35321
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
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smp_processor_id() only makes sense if the code can not move to a
different CPU. The tegra clock code runs with IRQs enabled and
preemption on, so it can move to a different CPU.
Bug 827687
Change-Id: I8b3077c71966e535cc6ca2a2ec63eca0d7119777
Reviewed-on: http://git-master/r/35239
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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