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Change-Id: Idf489cf40c4e657d938c8249053ff443f615acc7
Reviewed-on: http://git-master/r/54813
Reviewed-by: Ryan Wong <ryanw@nvidia.com>
Tested-by: Ryan Wong <ryanw@nvidia.com>
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In hdmi_pcm_open(), the evaluated PCM hw parameters are stored in
hinfo, but these aren't properly set back to the current runtime
record since these have been set beforehand in azx_pcm_open().
This patch fixes the behavior.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
(cherry picked from commit 639cef0eb6df05d5516520aa89b0c9fe62ee2d3b)
Bug 879658
Change-Id: Id8eea5a9516a92192671e081f5284de184a12b3a
Reviewed-on: http://git-master/r/54281
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
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The WARs checked into 12r7: disable LP0/LP1 and slave LP2, and force
maxcpus to 1 aren't needed when used with the newer tf_include.h from
this TL drop.
bug 868906
bug 870224
bug 877339
Change-Id: Ic3002b1d5fa09e8171c0d43bf6978ae96e51daf8
Reviewed-on: http://git-master/r/53324
Reviewed-by: Rahul Prabhakar <rahulp@nvidia.com>
Tested-by: Rahul Prabhakar <rahulp@nvidia.com>
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Reviewed-by: Jonathan White <jwhite@nvidia.com>
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The clock control apis can be sleepable in tegra platform as
spi require frequency/voltage boosting.
Moving the clock controls api out of spin lock context.
bug 874841
Change-Id: Id93ee03673f1d3c97175b965d561ec32397db662
Reviewed-on: http://git-master/r/52617
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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The I2C driver incorrectly manipulated the 10-bit address of corresponding
slave devices when initiating protocol based transactions. This caused NACK
errors from the slave devices that only support 10-bit addressing. Fixed by
skipping address shifting when the slave devices support 10-bit addresses.
Bug 874193
Change-Id: Idf69e434fd7e68c22047474169f7c6a8145721e2
Reviewed-on: http://git-master/r/51866
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Error handling in the driver was not correctly done earlier. Changes
done are as follows:
- error returned stored in int data type instead of u8 or s8
- few places error was not checked, added the checks needed.
Change-Id: Ife6f70787b1aae51b9bafab1afafb65257013ca5
Reviewed-on: http://git-master/r/51855
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Delay gain change by 1 frame. This will prevent sensor
applying new gain setting in the middle of the frame.
Bug 870349
Change-Id: Ib4e0e2fef99dcbf05a0656640af529e8f02c2a7d
Reviewed-on: http://git-master/r/52773
Reviewed-by: Krupal Divvela <kdivvela@nvidia.com>
Tested-by: Krupal Divvela <kdivvela@nvidia.com>
Tested-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 871094
Change-Id: I1b3bf7d4d50e08939c0ea9fc2e1c56fdc34d7323
Reviewed-on: http://git-master/r/52771
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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This reverts commit 03e9285cdc365ce1fa21fff224372dd8e5d883bd.
bug 872490
Change-Id: I4f72a8cbecffeca3b83f9740432f0d408d745e46
Reviewed-on: http://git-master/r/52698
Reviewed-by: Luke Huang <lhuang@nvidia.com>
Tested-by: Luke Huang <lhuang@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Making i2c clock control like clock enable/disable to
atomic call by removing can-sleep parents.
bug 876130
Change-Id: Id6dfd45014028e443ab9b29d6d5429b46a23a069
Reviewed-on: http://git-master/r/52619
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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On exit from deep sleep (LP0) restore from SDRAM Tegra3 MC registers
that are not saved in PMC scratch file for boot-rom restoration. Since
SDRAM after LP0 is running at boot rate, MC registers are saved only
once during initialization.
Bug 874351
Change-Id: Ib9ace46ede1efd5ee4097b17c3591a5b9f937a60
Reviewed-on: http://git-master/r/52526
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Ankit Pashiney <apashiney@nvidia.com>
Reviewed-by: Daniel Solomon <daniels@nvidia.com>
Tested-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Refactor nvhost_acm.c so that module specific code can be separated from
generic code:
* Module clock and power op descriptions added to channelmap table
* New module busy/idle interface added
* 3D clock scaling for Tegra3 moved behind the module busy/idle API
* 3D power off code moved to 3dctx where it belongs
* Module power on API removed as there were no users
* Get/Set rate moved to Tegra3 specific file
Bug 870791
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: Ia27db32c606b7dd3f9acf0c7e43e4de80a9ef0b4
Reviewed-on: http://git-master/r/51275
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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nvhost_module_rate() must turn clock on before querying its value.
Bug 873710
Change-Id: Idae811c6f7a27cbd0b9d701921fad36eaca1121e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/52357
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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This reverts commit 1a5733cc93dc9ec0eabe6115038567d3cf48a61a.
Change-Id: I1764f15694c6bc662f2f561c0442bbd60cff9703
Reviewed-on: http://git-master/r/52736
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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SMMU simply needs to know its assigned IOVA range, but does not need
address space resources.
Bug 874438
Change-Id: I96a8718e692bbb96b5fce6ec7ebc90f6930f358c
Reviewed-on: http://git-master/r/52670
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
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Adding remote wakeup support.
Bug 805906
Change-Id: I4e8637161abd1c5de90b0f856ad5c877e9433e42
Reviewed-on: http://git-master/r/52620
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Tested-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Rama Kandhala <rkandhala@nvidia.com>
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I_MDM_RST (gpio33) is connected to PMIC VMON_OUT.
It shouldn't be driven high, only low when reset is performed.
Modem reset relies on power cycle (PON low->high) today.
Bug 866051
Change-Id: I96631d7055979e9bb3365ffca27c2fb46afe7c3f
Reviewed-on: http://git-master/r/52593
Tested-by: Frederic Bossy <fbossy@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Settings in DIDIM driver are now phased in over a defined
number of steps in order to minimize the perception of changes
to the settings during runtime
Bug 840155
Change-Id: Icbafebd7f70445f9aad1c5819a1eb7e426410784
Reviewed-on: http://git-master/r/52495
Tested-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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Updated following into i2c driver:
(1) Because of race condition between isr and tx fifo fill,
duplicate data is being written. So added locking to make
Tx fifo fill as atomic.
(2) Removed unnessary synchronization between isr and init.
clock driver is making sure that any write operations will
be completed before disabling the driver clock.
Change-Id: Id68b238ec1b60b5b5c15a15930f36b39b33eeded
Reviewed-on: http://git-master/r/52549
Reviewed-by: Alok Chauhan <alokc@nvidia.com>
Tested-by: Alok Chauhan <alokc@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Add support for Sony PS3 game controller for
Bluetooth and USB interface.
Bug 847075
Change-Id: If1abd56a8ed6e4157630c42c8efba89d090f6be5
Reviewed-on: http://git-master/r/52363
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Vandana Salve <vsalve@nvidia.com>
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Add powergating for vi, csi and isp in tegra_camera
Bug 855758
Change-Id: Ibb026f71ea0623e0e8e21cb8c250f92728d0d60b
Reviewed-on: http://git-master/r/52099
Reviewed-by: Bhushan Rayrikar <brayrikar@nvidia.com>
Tested-by: Bhushan Rayrikar <brayrikar@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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Adding support for E1257 platform.
bug 864294
Reviewed-on: http://git-master/r/50662
(cherry picked from commit 8217615021a6ffeb992327f6b010ea9deebc34e7)
Change-Id: If1420f39ba5a6f724dd09b46881ba145cc784a0a
Reviewed-on: http://git-master/r/52258
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Restore FCR while resuming debug uart, to enable RX and TX FIFOs with
trigger levels configured during initialisation of debug uart port.
Bug 867063
Change-Id: I37bc521d7263ee7a3aa0fa77295b768be7b44361
Reviewed-on: http://git-master/r/52343
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Using the register caching for optimizing the update of pmu register
through i2c. In this way, the frequent read of pmu register is
avoided.
bug 870689
Change-Id: Ic6666d4c04d7a46236dae5cc42d3b0815606efef
Reviewed-on: http://git-master/r/52335
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Adding USB remote wakeup events for bringing system out of Low Power mode.
Bug 805906
Change-Id: If8a0a3e4b2aa344138a908f466fb2a7e9a71f058
Reviewed-on: http://git-master/r/52310
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Tested-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Adding USB remote wakeup events for bringing system out of Low Power mode.
Bug 805906
Change-Id: I66814ea09f2903fbaba513dce7d1f7c1a1744ec5
Reviewed-on: http://git-master/r/52309
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Tested-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Removed the polling/PMC based method for the usb hotplug detection.
Bug 865094
Change-Id: Idad6eb4a25fc0c589b46f11d5d8a47a41b60f251
Reviewed-on: http://git-master/r/52284
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Set EPP default clock low.
Note that 2D default clock is already low.
bug: 790961
Change-Id: Ie104c961d45253f26beed7ad3885bfaf1427ecbc
Reviewed-on: http://git-master/r/52240
Tested-by: Mandar Potdar <mpotdar@nvidia.com>
Reviewed-by: Mohan Nimaje <mnimaje@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Avoiding the suspend of the system if the spi transfer is
in progress for current transfer queue.
bug 864987
Change-Id: Ifc16ce92b36d3b5700990ca686dd6a9858cd74ae
Reviewed-on: http://git-master/r/52037
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Enabling the XCVR setup for USB using USB calibration
fuses.
Bug 867817
Change-Id: I273437339a42961f6b1a335d57869435e5ded8fa
Reviewed-on: http://git-master/r/51575
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Adding software programmability to add appropriate
offset for usb calibration.
Bug 867817
Change-Id: I06ba74036a54b9283c58bfab35410d95b8fccf12
Reviewed-on: http://git-master/r/51573
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Bug 873860
Change-Id: I035ddc3106d1c9a71acbbf47072f888dee8ded36
Reviewed-on: http://git-master/r/52178
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Robert Morell <rmorell@nvidia.com>
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Bug 873860
Change-Id: Ia29a74689c150fec782e91884bd4116bd89f253c
Reviewed-on: http://git-master/r/52135
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Robert Morell <rmorell@nvidia.com>
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Temporarily disable support since it appears the
modeset to 1080p takes longer than anticipated.
Re-enable once issue has been fixed.
Bug 869099
Change-Id: I4d596e33016a3723bca9bdb707cedd993a18f71b
Reviewed-on: http://git-master/r/51833
Tested-by: Dhiren Bhatia <dbhatia@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
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ISP needs the vertical output size to be a little more
than the actual resolution. Change vertical size to
1088 for 1920x1080 mode.
Bug 870687
Change-Id: I0c90a9da48f9b5915f1af0f9dab2b6d090da050d
Reviewed-on: http://git-master/r/51682
Reviewed-by: Bhushan Rayrikar <brayrikar@nvidia.com>
Tested-by: Bhushan Rayrikar <brayrikar@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Shiva Dubey <sdubey@nvidia.com>
Reviewed-by: Charlie Huang <chahuang@nvidia.com>
Tested-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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Change the pll source of vi_sensor from PLL_M to PLL_P since PLL_M is
more variable. Also we can get exactly 24MHz mclk rather than 24.24MHz.
Bug 870687
Change-Id: Idd754aea5486e26b7391dbdb397cb4f2116cc4e7
Reviewed-on: http://git-master/r/51677
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Balanced CPU and core domains thermal throttling on Tegra3. When
throttling is enabled the new algorithm caps core bus frequencies
(EMC, cbus and sbus) along with CPU rate. The throttling steps, and
time spent on each step are pre-defined based on characterization
results.
Change-Id: Id18109f6319032aad4332b13955996116a7f6485
Reviewed-on: http://git-master/r/51497
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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This change supports PM313(reworked) with 19X12 on E1198.
Bug ID : 875415
Change-Id: Ia774278c8f652dfb4204bb7c82976f101f0b559e
Reviewed-on: http://git-master/r/51929
Reviewed-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Tested-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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set i2s sample rate to 8 KHz which is connected to baseband.
Change-Id: Ice19e102826d7e2ce2ffb759adf44417ebb00f1a
Reviewed-on: http://git-master/r/51819
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Update card_present variable during resume by reading
card detect gpio value inorder to detect cards inserted
or removed during suspend
Bug 871234
Change-Id: I4e068d5ad595d58fa245d7ec1fb24973ffdd4aca
Reviewed-on: http://git-master/r/51778
Reviewed-by: Venkata Jagadish <vjagadish@nvidia.com>
Tested-by: Venkata Jagadish <vjagadish@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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To reduce i2c transaction, added struct max77663_register into
struct max77663_regulator. It includes cache value for each register,
so there is no need for i2c read after updating cache value
in preinit function.
Bug 849360
Change-Id: Ifeea34606dc22f9c04d44a6a783021fd9632477e
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/51526
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Fixed issues in entering suspend mode when
no pcie devices are connected
bug 873836
Change-Id: I420fc1bae17e1c63c037b24465ab07029bb68aa4
Reviewed-on: http://git-master/r/51506
Tested-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Added Tegra3 kernel dvfs throttling interface for VDD_CORE domains.
Requests from this interface are combined with sysfs capping requests
and the most aggressive (minimal) cap level is set.
Change-Id: I3a612d1ea85dce0d90b586ca6e2d23deae7bcc9e
Reviewed-on: http://git-master/r/51496
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
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Selecting debug console from linux command line.
bug 795847
Change-Id: I00a6447db29251ef4c2a52b742528ff99ea33845
Reviewed-on: http://git-master/r/51847
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Optimizing the time require to change the voltage by using the
register caching.
bug 870689
Change-Id: I3a26bb53a0b717eb900545070de2ad846ab31598
Reviewed-on: http://git-master/r/51836
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
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Bug 874120
Change-Id: If058527adc3b0c5c903ed75ab1ffaeb08be37df2
Reviewed-on: http://git-master/r/51828
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Anshul Jain (SW) <anshulj@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Change-Id: Ib85c6ac6ab971be84a1ac0dc07d7efbc078e59af
Reviewed-on: http://git-master/r/51724
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Tegra cpu complex frequency is set by cpufreq driver to the maximum
of per-cpu target frequencies specified by the respective governors
running on each cpu core. It guarantees that final frequency is above
all per-cpu policy low limits, but policy high limit set on one core,
may be exceeded if the other core has higher target.
This commit implements complementary mode in cpufreq driver that set
final cpu frequency below all per-cpu maximum policy limits. The new
mode is disabled by default, and can be activated via
/sys/module/cpu_tegra/parameters/force_policy_max
Change-Id: I079b7c55b079cdf62afae469b59f4b2cf0fc97d0
Reviewed-on: http://git-master/r/51722
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Satya Popuri <spopuri@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
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Turning on PCIE is breaking LP0. Needs to be fixed before getting
enabled.
This reverts commit 03fdda36cc03a4fa5d731df8b3ec1785621e746d.
Change-Id: I3389f9c2a0b6864ac4c183abdaeef09fe57b22a0
Reviewed-on: http://git-master/r/51844
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Tested-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Karthik Ramakrishnan <karthikr@nvidia.com>
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RNDIS should always be registered as first function in
list of usb functions available. Moving accessory function
down the order
Bug 874046
Change-Id: I70260b3e3036d627abcacf63df49728f2dd78841
Reviewed-on: http://git-master/r/51580
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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