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2013-02-14video: tegra: dsi: Dont program initialized panelsRakesh Iyer
Do not program some panels that the bootloader has already initialized. This avoids periods of blanking during boot. Bug 1219004 Change-Id: Ie08b20a0892d62dc1b960d37f709eda933e886cc Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Reviewed-on: http://git-master/r/197685 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2013-02-14cpuquiet: Remove synchronization from runnables_work_func()Peter Boonstoppel
runnables_stop() can deadlock when cancel_work_sync() waits for the work function to end and the work function blocks on the same lock held by runnables_stop(). Removing the locks from runnables_work_func() fixes this. This should be safe because runnables_lock protects runnables_state and runnables_work_func() only reads runnables_state. Also, the functions that change state to DISABLED do a cancel_work_sync() to guarantee the work function stopped running. Bug 1215668 Change-Id: I70617b3b0fc81db8555869e67e3b11652af8d94c Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/195797 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-13mmc: tegra: Option to disable all UHS modesPavan Kunapuli
Adding option to disable all the UHS modes - SDR12, SDR25, SDR50, DDR50, SDR104, HS200. Bug 1189241 Change-Id: I673cf5c819cb4c2ec0525f6e47b493ad1a4b7112 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/199931 Reviewed-by: Rama Kandhala <rkandhala@nvidia.com>
2013-02-13ARM: Tegra: Dalmore: Adding return statement.pdabade
Adding return statement to avoid registration of platform device twice for board E1613. Change-Id: Ie0d630195f884ee0fc11d21d6aa6a32f2b0d4463 Signed-off-by: Pankaj Dabade <pdabade@nvidia.com> Reviewed-on: http://git-master/r/199900 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-02-13ARM: tegra: enable dma based transferKunal Agrawal
enable dma based transfer for T114 A02 SOC based board Bug 1233632 Change-Id: I1bfe6ea6e82c535efce9a4bbceb7d7146c290dfc Signed-off-by: Kunal Agrawal <kunala@nvidia.com> Reviewed-on: http://git-master/r/199340 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-02-13power: max17048: fix charging statusSyed Rafiuddin
state of charge suddenly jumps to 0% resolving the same issue. Bug 1214186 Change-Id: I234a369b86678c8ea177c368ff828930f5ccf73b Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com> Reviewed-on: http://git-master/r/199267 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-02-13ARM: tegra: roth: update with correct vreset valueSyed Rafiuddin
use correct vreset value for max17048 fuel-gauge driver. Bug 1214186 Change-Id: I2bc69bfbd457152e8888907b17fba5369eb3907a Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com> Reviewed-on: http://git-master/r/199266 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2013-02-13ARM: tegra: Get cluster ID by reading MPIDRBo Yan
This is to avoid MMIO access, thus save a few processor cycles. Change-Id: Ib4a2aaf8e991885baab51cd74a37387e91cfb5a8 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/171656 (cherry picked from commit 10b7f4ccbf961cbde6b2dec5eb789c1d3beb0f75) Reviewed-on: http://git-master/r/198890 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-02-13ARM: tegra11x: Remove redundant cpu_number callsBo Yan
The "cpu_number" maps cpu number for slow cluster to "4", this can be reused later, no need to call "cpu_number" every time. Change-Id: Ib0636b80b587868e23a6b07a5cc9960e13d38353 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/198580 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-02-13ARM: tegra: power-edp tableDiwakar Tundlam
Added code for populating cpu power edp table during init. This is needed for the AP+DRAM super system EDP client. Bug 1159974 Change-Id: Ib632cd010627903374fc999f39759f7f54eee136 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> (cherry picked from commit 4ec0d4357df774cd32e18595b4fa5707679bfbd6) Reviewed-on: http://git-master/r/198397 GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2013-02-13ARM: tegra11: add frequency cap clocksSivaram Nair
Frequency cap clocks for EMC and CBUS are added for AP+DRAM EDP super-client support. Bug 1159974 Change-Id: I416cc363025e1ce94e4499300775576eb1cd8178 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> (cherry picked from commit 87d33aa536b156d6c69d1131c95f91ee86725c11) Reviewed-on: http://git-master/r/198396 GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2013-02-13EDP: fixing bug with priority definitionsSivaram Nair
The min and max priority constants are defined incorrectly (in the wrong order). This patch corrects it and updates the affected drivers and platform data. Change-Id: I94a628c4f4076d1c36dff1692f0427ad1f218fb5 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> (cherry picked from commit 3d2fe9f41fdd54d4c79b7202680e93de8debc8a1) Reviewed-on: http://git-master/r/198395 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2013-02-13input: misc: mpu: Add I2C shutdown supportErik Lilliebjerg
Bug 1202588 Change-Id: I60f3b4e7f3bd4fdf76ad78e29596155edcf65b2f Reviewed-on: http://git-master/r/191640 (cherry picked from commit 96b108f17e611f8d9c9aab1fb8e660ea6d559534) Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com> Reviewed-on: http://git-master/r/197635 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-12input: touch: raydium: power sequenceDavid Jung
Update Raydium touch driver for new power sequence. Bug 1228213 Change-Id: I20fd8fd94af36192120180b0ee91a3021c46a159 Signed-off-by: Xiaohui Tao <xtao@nvidia.com> Signed-off-by: David Jung <djung@nvidia.com> Reviewed-on: http://git-master/r/198124 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-02-12arm:tegra: remove clock enable in board fileXiaohui Tao
Clock is controlled in raydium driver now. Remove the clock enable in board file. Bug 1228213 Change-Id: I6fa83adf3689fa9911544caba54340101af19ed7 Signed-off-by: Xiaohui Tao <xtao@nvidia.com> Reviewed-on: http://git-master/r/197647 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: David Jung <djung@nvidia.com> Tested-by: David Jung <djung@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-12input: touch: raydium: update power sequenceDavid Jung
Update power sequence for Raydium touch. Bug 122813 Change-Id: I12b13e043c5853b1f886f51285525f2165da2ff4 Signed-off-by: David Jung <djung@nvidia.com> Reviewed-on: http://git-master/r/196763 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-12arm: tegra: roth: raydium power sequenceXiaohui Tao
Update power sequence for roth. Bug 1228213 Change-Id: I7a3872205d421aae7456868cd1dd1b29d5d5d92b Signed-off-by: Xiaohui Tao <xtao@nvidia.com> Signed-off-by: David Jung <djung@nvidia.com> Reviewed-on: http://git-master/r/196654 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-12input: touch: raydium remove spurious interruptsDavid Jung
Raydium code drop to remove spurious interrupts. Bug 1219704 Change-Id: I03d0c178b1d788753026b55dceebf2175484f983 Signed-off-by: David Jung <djung@nvidia.com> Reviewed-on: http://git-master/r/196560 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-12input: touch: raydium slow scan updatesDavid Jung
Raydium code drop. Update code for slow scan. Bug 1054801 Change-Id: Ie123e14ab9892b8055ab7af4bae9dd14189acfa6 Signed-off-by: David Jung <djung@nvidia.com> Reviewed-on: http://git-master/r/194480 Reviewed-by: Robert Collins <rcollins@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-12arm: tegra: Add raydium touch clock namesAly Hirani
Add the clock names for the raydium touch driver. Also remove clk_enable()s as the raydium driver now properly enables the touch clock. Bug 1188790 Change-Id: Ia9dce83b7943dab35e3902dbefdb8d806df365ae Signed-off-by: Aly Hirani <ahirani@nvidia.com> Reviewed-on: http://git-master/r/172909 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-02-12Revert "ARM: Tegra: Roth: Disable Touch"David Jung
This reverts commit b7a9217f6fec4f70d0f6a5ea4e03d3b89d5f4b18. Re-enable touch for roth. Bug 1228213 Change-Id: Ic45c9834e544412cdf7f22ba4be49b8f627e5d39 Signed-off-by: David Jung <djung@nvidia.com> Reviewed-on: http://git-master/r/196559 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-12power: max17048: Adding shutdown functionalitySyed Rafiuddin
This change is intended to add shutdown fucntionality to the max17048 fuel gauge driver Bug 1202296 Change-Id: Id3fe159d99dbdf9c5623e5c6609860aa1274df73 Signed-off-by: Darbha Sriharsha <dsriharsha@nvidia.com> Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com> Reviewed-on: http://git-master/r/195546 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-02-12video: tegra: dc: report correct HDMI mode to TVJon Mayo
Reports correct aspect ratio and VIC to TV. bug 1230953 bug 1227041 Change-Id: Ia973f526a50b679627b8fa74dde99bc405c86061 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/199716 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-02-12ARM: tegra: clock: Add warning on boot over-clockingAlex Frid
Change-Id: If0ae2c46d9a8a927b1fddc809b7daf05c2b49c21 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/199201 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-02-12ARM: tegra11x: Support min residency per platformBo Yan
Though there is no compelling reason to have different residency requirement of Fmin@Vmin and non-CPU power gating for each platform, still makes it possible to define these thresholds per platform. If they are not defined, the default value are taken. Change-Id: I663afb869338bd2e4078b15253c8f8e29c3d6b3c Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/198846 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2013-02-12security: tf_driver: fix incorrect cpu affinity in tf_driverHyung Taek Ryoo
This change fixes incorrect cpu affinity after excuting tf_driver. The process using tf_driver sometimes can't be schecduled to available onlined cpu. It is because cpu affinity has changed after using tf_driver. tf_driver saves current cpu affinity by calling sched_getaffinity which returns cpu affinity AND-masked by onlined cpus. tf_driver should save just current cpu affinity, not cpu affinity AND-masked by onlined cpus. bug 1218943 cherry picked from commit bba209aa7fe8b4f52f5d42acc1b21d8f54c18fe0) Reviewed-on: http://git-master/r/#change,195830 Change-Id: I5fbc1e6a3c67fbd01e4f2f5321aea168f7ba07c9 Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com> Reviewed-on: http://git-master/r/198842 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-02-12arm: tegra: soctherm: Hi-precision get_temp by converting raw countsDiwakar Tundlam
Bug 1200077 Change-Id: I1c1432fe460e03f1354eac1a25a6639e50234a2a Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/197349 Reviewed-by: Automatic_Commit_Validation_User
2013-02-12arm: tegra: soctherm: Wrap precision calculation with macrosDiwakar Tundlam
Bug 1200077 Change-Id: Idfc0b5897498db7ff4b014bef8ca4ed2fa49ce59 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/197347 Reviewed-by: Automatic_Commit_Validation_User
2013-02-11asoc: tegra: fixing EDP client prioritiesSivaram Nair
The client priorities are fixed to reflect the change in EDP driver. Change-Id: I445c4d484fa14d584389fe43e0aa1137ec6bae81 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/199294 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2013-02-11arm: tegra: roth: Remove left and right NCT72Anshul Jain
The current POR of roth doesn't need left and right NCT sensors. These sensors have been removed from new revisions of roth boards. Bug 1233567 Change-Id: I7760f926d0ba7ec097fe0595c6b94c6c5b835b39 Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/198919 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-11ARM: tegra: restrict battery EDP manager to plutoSivaram Nair
Battery EDP manager is needed only in pluto at the moment. Removing it from elsewhere. Change-Id: Ic98b2a36d3b3d16d425d786a19b70c682b865173 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/198764 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2013-02-11ARM: tegra11: macallan: remove as364x LED driverHayden Du
Macallan does not have LED as364x on board, hence removing entries from board file bug 1232868 Change-Id: I554f9caa8aa2e98455d6380e8b7e735e42a9cb05 Signed-off-by: Hayden Du <haydend@nvidia.com> Reviewed-on: http://git-master/r/198634 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-11input-cfboost: add trace pointsYogish Kulkarni
Add trace points to log time stamp when the input event is received and time at which boost work is scheduled. This is for detailed profiling of touch latency. Bug 1229219 Change-Id: I5f2f4f3d821d93b550fa9f86dc8fd562fa5d460a Signed-off-by: Yogish Kulkarni <yogishk@nvidia.com> Reviewed-on: http://git-master/r/197954 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-02-11misc: ti-st: clean up st_host_wake driverNagarjuna Kristam
remove checkpatch errors on st_host_wake driver Bug 1179655 Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Change-Id: If90ff7fdb27b982023959d9b3752cb02c0696787 Reviewed-on: http://git-master/r/197498 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-11include: wl_wilink: include sk_buff.h fileNagarjuna Kristam
sk_buff.h header file is needed to compile st_host_wake driver Bug 1179655 Change-Id: I71d7290a7e3d7fea4f06caad4907c533bab31243 Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Reviewed-on: http://git-master/r/197415 Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-11ARM: tegra: config: enable ST_HCI and ST_HOST_WAKE configsNagarjuna Kristam
Bug 1179655 Change-Id: Idf4bfa33f19654e1acff5d0ef42398352daff281 Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Reviewed-on: http://git-master/r/197404 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-02-11TI Bluetooth: Adding TI Host Wakeup Driver changesRaghavendra Shenoy Mathav
Signed-off-by: Raghavendra Shenoy Mathav <raghavendra.shenoy@ti.com> Bug 1179655 Change-Id: I904ed2d392b6ff8fbfb00e949f470542387aace4 Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Reviewed-on: http://git-master/r/197395 Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com> Tested-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-11ARM: tegra11: dalmore: Fix build error with CONFIG_MACH_DALMORERoger Hsieh
sd_brightness is not exported only on dalmore board file. Add it in to get build error fixed. Bug 1214485 Change-Id: Ib79cbbafaba976103c4e866d3962e247dd50d3ef Signed-off-by: Roger Hsieh <rhsieh@nvidia.com> Reviewed-on: http://git-master/r/189454 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-02-11regulator: palmas: implement errata for ES1.0,ES2.0 and ES2.1Laxman Dewangan
The device has the errata and sw need to implement the WAR for proper functioning of the device. The errata are: 1. SMPS- slew rate (TSTEP) is slower than expected ----------------------------------------------- when output voltage target is close to previous one IMPACT: The settling time is greater than specified slew rate in register map and datasheet for voltage scaling of the SMPS. DESCRIPTION: Measurement done on WCSP ES2.0, SMPS8, SMPS6, SMPS12 for TSTEP=0x02(5mV/us) - step from VOUT= 0.5v to 1.65V ==>slew rate is around 5mV/us - step from VOUT= 0.96v to 1.04V ==>slew rate is around 2.5mV/us for TSTEP=0x03(2.5mV/us) - step from VOUT= 0.5v to 1.65V ==>slew rate is around 2.5mV/us - step from VOUT= 0.96v to 1.04V ==>slew rate is around 1.6mV/us WORKAROUND: Adapt wait time using above value. REVISION IMPACTED: ES1.0/ES2.0/ES2.1 2. LDO8_TRACKING: PD in tracking mode ------------------------------------- IMPACT: Higher consumption and performance impact when LDO8 is set in tracking mode and LDO is set to have its pull down enabled in OFF mode. DESCRIPTION: When LDO8 is set in tracking mode and the LDO is set to have its pull down enabled in OFF, the pull down is also enabled in ACTIVE mode. WORKAROUND: In tracking mode, bit7 of LDO_PD_CTRL1 register must be set to 0. When LDO8 is disabled, to have the pull down, bit7 of LDO_PD_CTRL1 register must then be set to 1. In LDO8 regulation mode, behavior is the same as the other LDOs. REVISION IMPACTED: ES 2.1 ES2.0 ES1.0 bug 1228386 bug 1195226 Change-Id: Ib19a21cb722b1bc07d93a0cf866c134672ef8735 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/199132 Reviewed-by: Automatic_Commit_Validation_User
2013-02-11mfd: palmas: read internal design rev and sw otp revsion of deviceLaxman Dewangan
Read internal design revision and sw otp version of the device and print this message. This will help on implementing the errata of different ES version of device. bug 1228386 bug 1195226 Change-Id: I616aafd20cc0fce0f75a2f730107905f739f77cb Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/199131 Reviewed-by: Automatic_Commit_Validation_User
2013-02-11mfd: palmas: Add APIs to access the Palmas' registersLaxman Dewangan
Palmas register set is divided into different blocks (base and offset) and hence different i2c addresses. The i2c address offsets are derived from base address of block of registers. Add inline APIs to access the Palma's registers which takes the base of register block and register offset. The i2c address offset is derived from the base address of register blocks. Change-Id: Ia4155e4ecba76bd6024583058ad943b9c7410976 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/199130 Reviewed-by: Automatic_Commit_Validation_User
2013-02-11video: fbmon: correct the hsync/vsync polaritiesRakesh Iyer
Fix the vsync/hsync polarities in the Extended resolution modedb table. Bug 1227070. Change-Id: Ie370391b2e97e94cca365abb937c6d1a128c96ef Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Reviewed-on: http://git-master/r/198964 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2013-02-11video: tegra: dc: fix HDMI VSI lengthRakesh Iyer
Write the correct number of bytes for the vendor specific infoframe. Also initialize all the bits in the infoframe. Bug 1227070. Change-Id: I6992acfe70b1d1a456db351218c11b9b8426b7dc Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Reviewed-on: http://git-master/r/198942 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2013-02-11ARM: tegra: roth: properly configure PK3 aka GMI_CS2Laxman Dewangan
In roth, pin GMI_CS2 is used for touch 1v8 voltage switch control. Making change to reflect the same i.e. do not configure GPIO_PK3 for the internal MIC. bug 1230317 Change-Id: I36f4e3d1a6c74bc37fa9c6833ed8da27bb0bf624 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/198738 Reviewed-by: Automatic_Commit_Validation_User
2013-02-11ARM: tegra11: clock: Update I2C5 maximum rate limitAlex Frid
Bug 1161126 Change-Id: Ib0a492d41ec13e0d061545ccab3ac6bab914c5da Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/198690 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2013-02-11ARM: tegra11: dvfs: Remove CSI/DSI dvfs tablesAlex Frid
Removed CSI/DSI dvfs tables since all clocks in this subsystem are characterized at maximum frequency in the entire operating voltage range. Bug 1161126 Change-Id: I32d08d94a5cab1636c53e02ddbb3042bc51d67cd Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/198689 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2013-02-11ARM: tegra11: dvfs: Update tables for GPU and system clocksAlex Frid
Bug 1161126 Change-Id: I90193fb22044a0ff3c0b6fd3ef0f3f37d92aad39 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/198688 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2013-02-11ARM: tegra11: dvfs: Upgrade CL-DVFS disable output opsAlex Frid
New CL-DVFS h/w (rev A02 of Tegra11 SoC) allows to disable CL-DVFS output while I2C transaction is in progress without compromising bus integrity. This commit added to platform data configuration option <out_quiet_then_disable> that is set only for older versions of the chip. In case when <out_quiet_then_disable> option is not set, a procedure for exiting closed loop mode to open loop mode is modified as follows: - I2C output is disabled before the switch (while still operating in closed loop mode) to avoid unnecessary voltage jump to "safe value" - Possible transaction in progress is flushed after interface is disabled - Flush timeout is reported to the caller that initiated closed loop exit (bus integrity is guaranteed even if timeout happens) In addition output is now disabled while look-up table is reloaded in cosed loop mode to avoid race between table write (s/w) and read (h/w). Bug 1159200 Change-Id: I9d0f0dfa55664c5792ca81018c127628d461da0b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/198633 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2013-02-11tlv320aic3xxx: add i2c shutdown implementationRahul Mittal
Adds i2c shutdown related checks Bug 1226744 Change-Id: Ic9833dd620f108d6c4a339579b71e80c790503f9 Signed-off-by: Rahul Mittal <rmittal@nvidia.com> Reviewed-on: http://git-master/r/197860 Reviewed-by: Vijay Mali <vmali@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com>
2013-02-11driver: max17042: Set correct temperature rangeGraziano Misuraca
Max17042 returns the temperature in deci-celsius. The temperature range was set to +/-70 which is actually only +/- 7 degrees. Change the range to -20 to +70 C so that the driver does not incorrectly believe the battery is overheating. Bug 1220507 Change-Id: I6046933cc7597bd4051673238261219ce8cfa106 Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com> Reviewed-on: http://git-master/r/195782 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Gaurav Batra <gbatra@nvidia.com> Tested-by: Gaurav Batra <gbatra@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-07 21:14:13 +0000