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MIPI CSI2 depends on this clock to work.
This patch also updates the binding document.
Signed-off-by: Robby Cai <R63905@freescale.com>
(cherry picked from commit 67e7963f6f7ddb6c001bb34c6af71f2330fd0e3f)
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After change the resolution, the blank state will be changed, the audio will
be triggered to start. which didn't care about the audio is running or not
before changing the resolution.
Add hdmi_abort_state for this special case.
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
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The offset reflects the current position of DMA access in the ALSA ring buffer.
So we should clear it before re-start DMA engine becasue the DMA access should
re-start its job from the 0 position. If we don't do this, the driver might get
a wrong idea about current position of DMA access. Thus fix it.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 8f265543ffda0a19e3f469967a7d61d8b344f080)
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We found HDMI Audio has a performance issue when playback 8 channels 192KHz
files, CPU might lag its interrupt responsing while SDMA continues updating
HDMI internal AHB DMA's address and restarting AHB DMA, which resulted the
noise when AHB DMA access overlaps with the data copy procedures in this
driver.
Thus we here double the buffer size and period size of HDMI Audio to chop
the CPU interrupt to its half in the same span of time so that we can keep
the data copy procedures safe and provent it from overlapping access with
AHB DMA.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 04af1a351e016f52276ae002fd9f64b6b2962168)
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LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.
This patch ensures that the low power idle code checks the status of the
dummy ldo2p5 regulator before disabling LDO2p5.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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wakeup
LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.
This patch adds the dummy regulator to the dts files.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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When dma zone memory used up, gckOS_AllocateNonPagedMemory() will try to
free non paged memory cache and allocate again. Such operation will cause
twice memory mutex request and cause gpu driver hang.
The solution is free the memory mutex at first before trying to free non
paged memory cache.
Date: Feb 27, 2014
Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Shawn Guo
(cherry picked from commit 79ed8edd23f990f6c1429154c2ee773c83bfd72e)
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Add hwrng support for i.MX6SL.
1. Add RNG driver. This driver originated as fsl-rngc.c. It
has been modified to support device tree. The name has been
changed since it supports both b and c variants of RNG.
2. Added clock and compatible info to the device tree data.
3. Added the entry in the options in the Kconfig for hwrng.
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
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When split mode deinterlacing is the ipu_calc_stripes_sizes() was failing due
to an unnecessary test. Added logic to use the maximal_stripe_width only if
the flag parameter has the bit 0 clear for not equal stripe sizes.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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For i.MX6 ARD board, the board not support read EDID from TV,
so HDMI driver will create a default support mode list when system
bootup.
Because yocto xserver can not get video mode information from
framebuffer now, and xserver will set default video mode XGA
to framebuffer, but XGA mode is not support by hdmi.
Remove XGA and SXGA from default support list.
HDMI driver will find a nearest match video mode in support list.
It is VGA mode. HDMI support VGA mode well.
Issue is fixed.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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This patch extracts the register init code for ESAI along with the default slot
number which is more common to I2S and LEFT_J mode.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit ad9c7ab4ff75488c0cc44bcc5d87af2d5d1139cf)
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This patch sets ESAI as LEFT_J format master so as to let ESAI provide bit
clock and frame clock for stability.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 38df16f71c95e2aa8e0b4c1ddd2ed7ec2c4fef4b)
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This patch mainly adds the clock route from external 24.576MHz OSC to internal
ESAI clock via analog clock2 PADs on the SoC and pll4 so that ESAI can get an
entirely synchronous clock source against CS42888.
[ 1, We found if using pll4 to generate a 24.576MHz from inernal 24.0MHz OSC,
we would get noise during the audio playback via ESAI->CS42888 even though
this generated clock's rate is equal to the external one statistically. It
might be resulted from the tiny difference between two clock source, which
might be crucial to the sensitive CODEC we use -- CS42888. So we here apply
the old 3.0.35 way to feed ESAI the same clock source as CS42888.
2, Ideally, we should use bypass mode for pll4 since we only need to get
the raw rate (24.576MHz) while currently bypass mode in clk-pllv3.c isn't
entirely supported: The clock rate would be fixed to 24.0MHz if setting to
bypass, which would cause child clock get an incorrect rate and the driver
who uses the child clock fail to derive a needed clock rate, and it might
be dangerous to involve the clk-pllv3.c driver to this fix. Thus we here
apply 3.0.35 way provisionally. ]
Expected result:
anaclk2 0 1 24576000
lvds2_in 0 1 24576000
pll4_sel 0 1 24576000
pll4_audio 0 1 786432000
pll4_post_div 0 1 786432000
pll4_audio_div 0 1 786432000
esai_sel 0 1 786432000
esai_pred 0 1 98304000
esai_podf 0 1 24576000
esai 0 1 24576000
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 49584be724d4d9c7a753d2b981b3932d8d871eb4)
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We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC.
And this lvds2, along with lvds1, can be used to provide external clock source
to the internal pll, such as pll4_audio and pll5_video.
So This patch mainly adds the lvds2 to the clock tree and fix its relationship
with pll4 accordingly.
[ To reduce the risk from code changing. This patch only takes care of pll4
related part. We might later need to add the relationship with pll5 too. ]
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 5b74b6b26e4b44d265090fc6ad15b15ccb7b5cff)
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All of these functions might be called before we enable the core clock in the
startup() by set_bias_level() or late_probe() in machine driver for example.
To make it safe, we here add pair of clock en/disabling to each function.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit e6df36df2bc8062f3d1c0a19d18acc843a77619d)
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This patch removes the function imx6q_lvds_cabc_init() from the
machine layer since we have a dedicated Hannstar CABC driver to
control the CABC feature.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit b0d2154a9c63b2beba774e46b90ec3d55609c672)
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This patch removes the device tree node lvds_cabc_ctrl, since
it is replaced by hannstar_cabc_lvds0 and hannstar_cabc_lvds1.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 6a3d2c5e858afeef695bcd9fe2ecc0933d3d29da)
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This patch adds a device tree node for the Hannstar CABC function.
We currently disable the CABC feature since it makes a panel's
backlight unstable when display content varies considerably from
time to time.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 0c98df5d1b04ea043e5279628aebf406c250f5e3)
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This patch adds a device tree node for the Hannstar CABC function.
The LVDS0 and LVDS1 interfaces of the i.MX6dql Sabreauto platform
shares a control pin for the CABC function, but LVDS1's control
wire is invalid for the unpopulated resistor R265 on the main board.
We currently disable the CABC feature since it makes a panel's
backlight unstable when display content varies considerably from
time to time.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 6af4f4ac7c361a60fe05400497f644db3adcfc94)
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This patch enables the Hannstar CABC driver in imx_v7_defconfig.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 9eeaeb6a259af6864a6db563100a300ba67ed83e)
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This patch documents the Hannstar CABC driver's device tree bindings.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 0a6b9cf8548ffe03b8df494d08bece54ef3e528e)
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This patch adds Hannstar CABC driver support. The CABC
function turns the backlight density of a display panel
automatically according to the content shown on the panel.
It is controlled(enabled/disabled) by a GPIO.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 2dddbc55bd8ae9461067e1a9d047b2994510e6d8)
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The bottom 16KB of the IRAM is reserved for the IRAM page table.
Reduce the available IRAM size for the other drivers by 16KB.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Whenever DDR is explicitly put into self-refresh, we need to ensure
that no access are made to the DDR. All the bus masters excpet ARM
are shutdown gracefully.
The ARM core can continue to access the DDR due to:
1. Speculative accesses
This can be prevented by flushing the Branch Target Address Cache
2. Aggressive Prefetching
This can be minimized by adding nops.
Apart from this the TLB architecture in ARM does not guarantee that
an entry remains in the TLB unless its explicitly locked. Even if
free slots are available an entry maybe evicted. So flushing the TLB
does not guarantee a page table walk will not happen.
The solution is to put a minimized page table in IRAM that can be used when
DDR is in self-refresh. The IRAM page tables should have entries for IRAM,
AIPS1 and AIPS2 as these entries will be needed by the code that puts DDR
into self-refresh. It should not contain any entries that point to the DDR.
This patch set accomplishes the following:
1. Set the IRAM to be mapped as 1M sections in the high mem region.
This makes it possible to create entries for the IRAM code in the IRAM page table.
We need to ensure that both the DDR and IRAM page table have mapping for the IRAM code.
2. Ensure the IRAM, AIPS1, AIPS2 have entries in the IRAM page table.
3. Save TTBR1
4. Set TTBR1 to point to the page tables stored in IRAM. Switch to using
TTBR1 before DDR is put into self-refresh. Ensure the following settings:
a. TTBCR.N = 1
This means the 0-2G virtual address space is translated using TTBR0
and 2G-4G is translated using TTBR1.
b. Set TTBCR.PD0 = 1
With this setting page table walks using TTBR0 are disabled.
4. After the DDR has exited self-refresh, reset TTBCR to 0 (TTBR0 will
be used for translations now).
5. Restore TTBR1
Even though TTBR1 is only used to decode the top 2G of virtual address
space, ARM requires that we allocate the entire 16KB for the page table.
To minimize IRAM/OCRAM required, we put the code in the bottom 8K and
page table entries in the top 8K.
This requires the low power code be optimized to occupy as little space
as possible.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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- add one imx pcie ep simple skeleton driver to demo
the msi trigger capability in imx6 pcie rc/ep validation
system
- in order to avoid the modification of common codes,
force the msi address to be 0x01ff8000
Test howto:
- Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images
- EP side(console command and kernel message):
root@sabresd_6dq:/ # memtool 0x1ff8000=0
Writing 32-bit value 0x0 to address 0x01FF8000
root@sabresd_6dq:/ #
- RC side(console command and kernel message):
root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI
384: 1 0 0 0 PCI-MSI
- EP side(console command and kernel message):
root@sabresd_6dq:/ # memtool 0x1ff8000=0
Writing 32-bit value 0x0 to address 0x01FF8000
- RC side(console command and kernel message):
root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI
384: 2 0 0 0 PCI-MSI
Signed-off-by: Richard Zhu <r65037@freescale.com>
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- setup one new outbound memory region at rc side, used
to let imx6 pcie rc can access the memory of imx6 pcie ep
in imx6 pcie rc ep validation system.
- set the default address of the ddr memory to be 0x4000_0000
NOTE:
- default address 0x4000_0000 of ep side would be
accessed in this demo.
Test howto:
step1:
EP side:
1.1:
echo 0x40000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/ep_bar0_addr
1.2:
memtool -32 0x40000000 4
E
Reading 0x4 count starting at address 0x40000000
0x40000000: 6FE9E9F6 7583FBB9 39EAEFEA FBDCFD78
step2:
RC side:
memtool -32 0x01000000=58D454DA
memtool -32 0x01000004=7332095B
step3:
EP side:
memtool -32 0x40000000 4
E
Reading 0x4 count starting at address 0x40000000
0x40000000: 58D454DA 7332095B 39EAEFEA FBDCFD78
Signed-off-by: Richard Zhu <r65037@freescale.com>
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The ECSPI1 needs the GPIO3_19 to select/de-select the SPI NOR chip.
This patch adds a new pinctrl for this GPIO, and select this pinctrl
when we enable the ECSPI1.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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the EIM_D18
The ECSPI needs the pin EIM_D18 which is controlled by the steering.
So we have to configurate the EIM_A24 to GPIO, and select the GPIO to LOW
status.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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full-speed idle
If the high-speed device does not enter full-speed idle after
wakeup on disconnect logic has effected, there will be an
unexpected disconnect wakeup interrupt due to the bus is still SE0.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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The CPU_DYING notifier is called by cpu stopper task which
does not own the context held in the VFP hardware. Calling
vfp_force_reload() has no effect.
Replace it with clearing vfp_current_hw_state.
Signed-off-by: Yuanyuan Zhong <zyy@motorola.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 384b38b66947b06999b3e39a596d4f2fb94f77e4)
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The WEIN NOR needs the pin EIM_D18 which is controlled by the steering.
So we have to configurate the EIM_A24 to GPIO, and select the GPIO to LOW
status.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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- add sata phy cr(offset:0x7f3f) reset in sata resume to
workaround imx6q sata kinds of suspend resume link
issues.
- add sata phy cr reset during imx6q sata initialization,
to initialize the sata phy to be an initialized state.
- add about 100us delay between mpll_clk enable and cr-rst,
make sure that the mpll_clk is stable.
- add about 100us delay between cr-rst and waiting for rx_pll
stable too, make sure that the cr-rst is finished.
- change the tx level setting from 1.025v to be the default
value 1.104v
- make sure the sata phy internal pll ref clk enable is
cleared before it is set, otherwise, the sata phy link
maybe failed when some devices are used.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Select HIGHMEM config to avoid the vmalloc region overlap on
boards that have big RAM.
Previous imx_v7_defconfig change(CONFIG_CRYPTO_TEST) did NOT follow
the savedefconfig rule, fix it as well.
Signed-off-by: Anson Huang <b20788@freescale.com>
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When device boot into console, frame buffer failed to work after
suspend/resume.
That is caused by LCDIF IP lost all registers configuration
in suspend mode, and console didn't reconfiguration fb after resume.
Same issue didn't found with Yocto UI.
Reinitialize frame buffer driver after resume to fix the issue.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Kernel will dump when run deinterlace stress test.
It is caused by vditmpbuf being reallocated by another thread
when one thread accesses it.
Issue is fixed by putting these code in mutex.
Kernel dump log:
[Playing ][Vol=01][00:00:10/00:00:30][fps:32]Unable to handle kernel
paging request at virtual address 607d6085
pgd = 80004000
[607d6085] *pgd=00000000
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 50 Comm: ipu2_task Not tainted 3.10.17-02308-g3700819 #28
task: ac1dc700 ti: ac1ba000 task.ti: ac1ba000
PC is at __kmalloc+0x40/0x114
LR is at __kmalloc+0x14/0x114
pc : [<800bbd40>] lr : [<800bbd14>] psr: 200f0013
sp : ac1bbbc8 ip : 008cc000 fp : 00001e40
r10: ac772e00 r9 : 0057b255 r8 : 000000d0
r7 : 00000790 r6 : ac773800 r5 : 607d6085 r4 : ac001b00
r3 : 00000000 r2 : 814f92a0 r1 : 000000d0 r0 : 000398c9
Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 3c4c004a DAC: 00000015
Process ipu2_task (pid: 50, stack limit = 0xac1ba238)
Stack: (0xac1bbbc8 to 0xac1bc000)
Signed-off-by: Sandor Yu <R01008@freescale.com>
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__va function only can handle frame buffer from low memory.
Use page_address function to replace it, that can handle
frame buffer from both lower and high memory.
Use ioremap_nocache function to handle Frame buffer
from GPU reserve memory pool.
Correct vdi data save buffer size, save both luma and chroma part for
interleaved YUV format.
For non-interleaved and partial-interleaved YUV format,
save luma part data, chroma part is not covered in the patch.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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property in dts
Add property "retain-state-suspended" in dts.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 7fa74454e8fb857b050901097bf78167ac3c04cd)
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gpio-leds driver common framework didn't take care of this case if use CONFIG_OF
, add property "retain-state-suspended" in dts and check it while gpio-leds
device created.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 118c650de0bb518d377b0e6427b38fc101fe31aa)
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From schematic, below GPIO keys' active state is low, so we need
to set correct active state in dts.
i.MX6Q/DL-SABRESD board: power, vol+ and vol-.
i.MX6Q/DL-SABREAUTO board: home, back, prog, vol+ and vol-.
Signed-off-by: Anson Huang <b20788@freescale.com>
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We should set watchdog timer to be disabled in low power mode,
as there is no service running in background, otherwise, system
will reset unexpected.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The tcrypt module is used to test the crypto API by being passed a
mode=<value> during module load. The test runs to completion before
insmod/modprobe returns. That makes the RCU stall detection in newer
kernels unhappy.
The simple fix is to add CONFIG_PREEMPT to the kernel config. That's
what this patch does. If that introduces other problems,
crypto/tcrypt.c can be modified to call schedule() in the correct
places. Here's a patch that should work if this one has to be
reverted:
diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c
index 66d254c..b771f7d 100644
--- a/crypto/tcrypt.c
+++ b/crypto/tcrypt.c
@@ -33,6 +33,7 @@
#include <linux/jiffies.h>
#include <linux/timex.h>
#include <linux/interrupt.h>
+#include <linux/sched.h>
#include "tcrypt.h"
#include "internal.h"
@@ -182,6 +183,7 @@ static void test_cipher_speed(const char *algo, int enc, unsigned int sec,
goto out;
}
+ schedule();
printk("test %u (%d bit key, %d byte blocks): ", i,
*keysize * 8, *b_size);
@@ -448,6 +450,7 @@ static void test_hash_speed(const char *algo, unsigned int sec,
if (speed[i].klen)
crypto_hash_setkey(tfm, tvmem[0], speed[i].klen);
+ schedule();
printk(KERN_INFO "test%3u "
"(%5u byte blocks,%5u bytes per update,%4u updates): ",
i, speed[i].blen, speed[i].plen, speed[i].blen / speed[i].plen);
@@ -688,12 +691,12 @@ static void test_ahash_speed(const char *algo, unsigned int sec,
break;
}
+ schedule();
pr_info("test%3u "
"(%5u byte blocks,%5u bytes per update,%4u updates): ",
i, speed[i].blen, speed[i].plen, speed[i].blen / speed[i].plen);
ahash_request_set_crypt(req, sg, output, speed[i].plen);
-
if (sec)
ret = test_ahash_jiffies(req, speed[i].blen,
speed[i].plen, output, sec);
@@ -853,6 +856,7 @@ static void test_acipher_speed(const char *algo, int enc, unsigned int sec,
goto out_free_req;
}
+ schedule();
pr_info("test %u (%d bit key, %d byte blocks): ", i,
*keysize * 8, *b_size);
@@ -934,6 +938,7 @@ static void test_available(void)
printk("alg %s ", *name);
printk(crypto_has_alg(*name, 0, 0) ?
"found\n" : "not found\n");
+ schedule();
name++;
}
}
Signed-off-by: Jay Monkman <jay.monkman@freescale.com>
(cherry picked from commit 2dc1e6a900df2b575914a7c58fc08e4b072c0e67)
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In order to support the dual video use-case, the current CMA reserved size is
not enough now, need enlarge the CMA size from 256M to 320M by default.
Signed-off-by: Jason Liu <r64343@freescale.com>
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The usdhc of i.MX6Q/DL can work well under low power mode without
request high bus freq. So we do not need request bus freq for i.MX6Q/DL.
It can save power for i.MX6D/DL due to it saves a lot busfreq switch
cost as well as the CPU time runing on high bus freq after switch
during low power mode.
A new flag ESDHC_FLAG_BUSFREQ is added to indicated this requirement.
Currently only i.MX6SL is using it.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit 075196777d00bf9507d68a76bf25f6c7e776102f)
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slow issue"
The root cause of playback slow issue should be trying to get DSPCLK_DIV
before enabling SYSCLK of WM8962. Since we have a patch fixed it, we can
revert this work round.
This reverts commit 49a3ca545a88cdf4aa597c4dd7d904b4faaea555.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit a4d253a8ab038661f515d72a175eb11688774874)
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Set a default slot number in startup() so that those who use I2S or other
2-channel DAI format would not need to call set_dai_tdm_slot() in their
machine drivers.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit eb22fac84c62cccb98dc4503bc9a537c435d216b)
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If disabling SSI when SSI is already in the working state, the whole running
substream would be broken. Thus we here replace it to a safer way -- saving
the current SSIEN value and restore it afterward.
This patch also adds a slot number checking code before setting slot number.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 2f71335a5b39afec4cf976b45683e5de1baed31d)
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Leaving clk_set_rate() in hw_params() is a bit dangerous when handling two
substreams. So we let set_sysclk() finish the clk_set_rate() directly.
This patch also adds spinlock to protect the baud clock configuration so
that it won't be broken during race.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit d3818ba35e4cbb6a3fa769eb83ceb7335b7c19e6)
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Since we introduced symmetric_channels and symmetric_samplebits, we can
implement these new feature to SSI synchronous mode and drop the useless
code accordingly.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 63a818ebd8fa88d8a91faa491c4f7909e7c8bdd5)
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DSPCLK_DIV can be only generated correctly after enabling SYSCLK. But if the
current bias_level hasn't reached SND_SOC_BIAS_ON, DAPM won't enable SYSCLK,
which would cause the calculation result from DSPCLK_DIV invalid since bit
DSPCLK_DIV will be finally turned to its true value after DAPM enables SYSCLK
while the driver won't calculate it again for the current instance. In this
circumstance, a playback which needs non-zero DSPCLK_DIV would be distorted
due to unexpected clock frequency resulted from an invalid DSPCLK_DIV value.
So this patch provisionally enables the SYSCLK to get a valid DSPCLK_DIV for
calculation and then disables it afterward.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 75704ecfbb4124139b78b71dd603f05d61abe689)
(cherry picked from commit 46ff60a75d0db92848913435bc345def2a2ccc5e)
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