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Use universal equation and 25C's calibration data to
get thermal sensor's ratio on i.MX6DL.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Use universal equation and 25C's calibration data to
get thermal sensor's ratio.
If want to use old calibration method, please add
"use_calibration" into kernel command line.
Signed-off-by: Anson Huang <b20788@freescale.com>
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use regulator _sel interface set to support auto delay,
as when regulator's voltage go up, it will take some time
to ramp up to the required voltage, so the delay is necessary.
_sel interface set support such function, now we switch to this
interface set.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Lily Zhang
Conflicts:
drivers/regulator/pfuze100-regulator.c
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1.LDO ramp up time may be modified by ROM code
according to fuse setting, cpu freq driver use
fixed delay time which assume the LDO ramp up time
is the reset value of ANATOP register, need to set
it to reset value in regulator init.
2.The regulator set voltage should take care of
the ramp up time, calculate the ramp up time based
of register setting and to the delay, make sure that
when the set voltage function return, the voltage is
stable enough.
3.CPUFreq no need to use delay, it is already taken
care by regulator voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Lily Zhang
Conflicts:
arch/arm/mach-mx6/cpu_regulator-mx6.c
arch/arm/mach-mx6/mx6_anatop_regulator.c
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HDMI hardware fix: signal of HDMI DMA DONE is hard connected to SDMA
event line. SDMA event is triggered by edge. If the HDMI DMA done is
already 1 before start, there would be no SDMA event being trigged after
HDMI generates another HDMI DONE signal.
In this patch, clear HDMI DONE bit before start HDMI audio DMA.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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Hwcomposer check this return value and will crash due to init failure rarely.
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Lily Zhang
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Enable the EDO mode for mx6q.
The following is the test result with the same nand chip (Micron MT29F32G08QAA)
in mode 4:
The test result without enable the EDO mode:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
page size 4096, count of eraseblocks 400,
pages per eraseblock 128, OOB size 218
mtd_speedtest: scanned 400 eraseblocks, 6 are bad
mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 1945 KiB/s
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 3384 KiB/s
mtd_speedtest: testing page write speed
mtd_speedtest: page write speed is 1841 KiB/s
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 3136 KiB/s
mtd_speedtest: testing 2 page write speed
mtd_speedtest: 2 page write speed is 1853 KiB/s
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 3164 KiB/s
mtd_speedtest: Testing erase speed
mtd_speedtest: erase speed is 145441 KiB/s
mtd_speedtest: Testing 2x multi-block erase speed
mtd_speedtest: 2x multi-block erase speed is 146711 KiB/s
mtd_speedtest: Testing 4x multi-block erase speed
mtd_speedtest: 4x multi-block erase speed is 147139 KiB/s
mtd_speedtest: Testing 8x multi-block erase speed
mtd_speedtest: 8x multi-block erase speed is 147786 KiB/s
mtd_speedtest: Testing 16x multi-block erase speed
mtd_speedtest: 16x multi-block erase speed is 147569 KiB/s
mtd_speedtest: Testing 32x multi-block erase speed
mtd_speedtest: 32x multi-block erase speed is 147677 KiB/s
mtd_speedtest: Testing 64x multi-block erase speed
mtd_speedtest: 64x multi-block erase speed is 147677 KiB/s
mtd_speedtest: finished
=================================================
The test result enable the EDO mode:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
page size 4096, count of eraseblocks 400,
pages per eraseblock 128, OOB size 218
mtd_speedtest: scanned 400 eraseblocks, 6 are bad
mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 3733 KiB/s
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 20413 KiB/s
mtd_speedtest: testing page write speed
mtd_speedtest: page write speed is 3603 KiB/s
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 18966 KiB/s
mtd_speedtest: testing 2 page write speed
mtd_speedtest: 2 page write speed is 3668 KiB/s
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 19686 KiB/s
mtd_speedtest: Testing erase speed
mtd_speedtest: erase speed is 146604 KiB/s
mtd_speedtest: Testing 2x multi-block erase speed
mtd_speedtest: 2x multi-block erase speed is 147354 KiB/s
mtd_speedtest: Testing 4x multi-block erase speed
mtd_speedtest: 4x multi-block erase speed is 147677 KiB/s
mtd_speedtest: Testing 8x multi-block erase speed
mtd_speedtest: 8x multi-block erase speed is 148002 KiB/s
mtd_speedtest: Testing 16x multi-block erase speed
mtd_speedtest: 16x multi-block erase speed is 147894 KiB/s
mtd_speedtest: Testing 32x multi-block erase speed
mtd_speedtest: 32x multi-block erase speed is 148329 KiB/s
mtd_speedtest: Testing 64x multi-block erase speed
mtd_speedtest: 64x multi-block erase speed is 148220 KiB/s
mtd_speedtest: finished
=================================================
We can see that there is 6 times performance improvement for reading
when we enable the EDO mode.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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add the WRN_DLY_SEL field for HW_GPMI_CTRL1.
This field is used as delay for gpmi write strobe.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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The current code will gets the clock frequency which is used by
gpmi_nfc_compute_hardware_timing(). It makes the code a little mess.
So move the `get clock frequency` code to the
gpmi_nfc_compute_hardware_timing() itself. This makes the code tidy
and clean.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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The gpmi_nfc_compute_hardware_timing{} should contains all the
fields setting for gpmi timing registers. It already contains the fields
for HW_GPMI_TIMING0 and HW_GPMI_CTRL1.
So it is better to add a new field setting for HW_GPMI_TIMING1 in
this data structure. This makes the code more clear in logic.
This patch also changs some comments to make the code more readable.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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HDMI audio driver is responsible for add IEC header into audio sample.
In HDMI audio driver, a variable named rtd->appl_bytes is maintained to
stand for how many audio sample have already processed. appl_bytes
stands for how many audio sample the user space have already feed into
kernel driver. So we use the connt = appl_bytes - rtd->appl_bytes to
decide how many data need to be processed. And the processed data would
be write into an preallocated buffer called hw_buf in driver.
When doing seek operation, the appl_bytes changes in an wide range. So
it is possible that the count value is far larger than the size of
hw_buf and the memory access un-existed address error would happens.
In this patch, Add check operation for count to avoid kernel panic.
Kernel panic log:
seeking: 0:00:18.000000000/0:03:0Unable to handle kernel paging request
at virtual address ffdf0000
pgd = 80004000
[ffdf0000] *pgd=71e35811, *pte=00000000, *ppte=00000000
Internal error: Oops: 7 [#1] PREEMPT SMP
Modules linked in: vivante drm galcore
CPU: 0 Not tainted (3.0.35-2014-g7a9337b #1)
PC is at hdmi_dma_mmap_copy+0x134/0x190
LR is at hdmi_dma_mmap_copy+0x5c/0x190
pc : [<803e1e4c>] lr : [<803e1d74>] psr: 800f0193
sp : 80a61e98 ip : ffdf0000 fp : ffdeffc0
r10: 00000055 r9 : ffdeff80 r8 : 0029b450
r7 : 00000060 r6 : ffdf0200 r5 : 00000240 r4 : 00000120
r3 : 00000000 r2 : ffdf0000 r1 : 00000000 r0 : 00000090
Flags: Nzcv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 6d28804a DAC: 00000015
Process swapper (pid: 0, stack limit = 0x80a602f0)
Stack: (0x80a61e98 to 0x80a62000)
1e80: 00000002
000037f1
1ea0: 00006000 e1d3a7e4 a00f0193 e1d3a780 e1dcab00 00a83100 00a83100
00006000
1ec0: 00006000 803e24f4 413187b9 00000000 0073001a e1dd1e00 00000001
00000001
1ee0: 00000080 00000093 80ac7070 80a66a80 00000001 800a5ca8 8c80e568
efb3e7b9
1f00: 00000055 80a66a80 80a66acc e1ea9bc0 00000093 00000000 80a60000
00000000
1f20: 00000000 800a5e14 80a66a80 80a66acc 0000107f 800a8198 80a71cc0
80038c00
1f40: 80a60000 800a5610 000001f0 80040830 ffffffff f2a00100 00000093
00000002
1f60: 00000001 8003f9cc 80ac5f60 800f0093 00000001 00000000 80a60000
80abeb64
1f80: 804e1a54 80a74e7c 1000406a 412fc09a 00000000 00000000 00000000
80a61fb0
1fa0: 8004d52c 80040ac4 400f0013 ffffffff 80040aa0 80040cbc 00000001
80a71b3c
1fc0: 80abeac0 8002e3c4 8c80b140 80008868 800082f8 00000000 00000000
8002e3c4
1fe0: 00000000 10c53c7d 80a71a6c 8002e3c0 80a74e74 10008040 00000000
00000000
[<803e1e4c>] (hdmi_dma_mmap_copy+0x134/0x190) from [<803e24f4>]
(hdmi_dma_isr+0x17c/0x1a0)
[<803e24f4>] (hdmi_dma_isr+0x17c/0x1a0) from [<800a5ca8>]
(handle_irq_event_percpu+0x50/0x180)
[<800a5ca8>] (handle_irq_event_percpu+0x50/0x180) from [<800a5e14>]
(handle_irq_event+0x3c/0x5c)
[<800a5e14>] (handle_irq_event+0x3c/0x5c) from [<800a8198>]
(handle_fasteoi_irq+0xbc/0x154)
[<800a8198>] (handle_fasteoi_irq+0xbc/0x154) from [<800a5610>]
(generic_handle_irq+0x28/0x3c)
[<800a5610>] (generic_handle_irq+0x28/0x3c) from [<80040830>]
(handle_IRQ+0x4c/0xac)
[<80040830>] (handle_IRQ+0x4c/0xac) from [<8003f9cc>]
(__irq_svc+0x4c/0xe8)
[<8003f9cc>] (__irq_svc+0x4c/0xe8) from [<80040ac4>]
(default_idle+0x24/0x28)
[<80040ac4>] (default_idle+0x24/0x28) from [<80040cbc>]
(cpu_idle+0xbc/0xfc)
[<80040cbc>] (cpu_idle+0xbc/0xfc) from [<80008868>]
(start_kernel+0x248/0x288)
[<80008868>] (start_kernel+0x248/0x288) from [<10008040>] (0x10008040)
Code: c1a0c009 c08b6005 c1a0200b da00000a (e0d230b2)
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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lrclk trigger settings between ssi and wm8962 are different,
which causes L/R channel swap.
Signed-off-by: Gary Zhang <b13634@freescale.com>
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lrclk trigger settings between ssi and wm8962 are different,
which causes L/R channel swap.
Signed-off-by: Gary Zhang <b13634@freescale.com>
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Enable ahash feature in mx6q config.
Signed-off-by: Terry Lv <r65388@freescale.com>
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correct typo for wm8962 description in Kconfig
Signed-off-by: Gary Zhang <b13634@freescale.com>
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After doing some suspend/resuem test, secondary cores BogoMIPs
will be wrong, the root cause is that when cpufreq is changed,
we only update the online cpus' loops_per_jiffy, and when secondary
cores back to online, we skip the loops_per_jiffy calibration. During
suspend/resume, the cpufreq can be changed during disabling/enabling
secondary cores, which will make secondary cores loops_per_jiffy
wrong, so here we need to update all possible cpus' loops_per_jiffy
when cpufreq is changed.
Signed-off-by: Anson Huang <b20788@freescale.com>
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i2c device (isl29023) can not suspend once during hdmi
audio suspend/resume test, and print log:
pm_op(): i2c_device_pm_suspend+0x0/0x38 returns -4 PM: Device
2-0044 failed to suspend: error -4 PM: Some devices failed to
suspend PM: resume of devices complete after 40.936 msecs
Restarting tasks ... done.
Because suspend function in isl29023 driver requires i2c bus
to write isl29023 device. I2C apdater driver process any signal
as exception during waiting the bus idle, so once user space sent
out signal during suspend, I2C device cannot request bus.
Using "fatal_signal_pending()" instead of "signal_pending()"
to avoid the waiting of bus idle to be terminated by general
signals except SIGKILL. After the change, i2c adapter can be
terminated by kill signal from user space with "CTRL+C" or
kill command operation.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Ethernet performance is downgraded when wait mode on in
100Mbps mode.
wait mode off:
100Mbps mode: tx bandwidth is 94Mbps
rx bandwidth is 94Mbps
wait mode on:
100Mbps mode: tx bandwidth is 30Mbps
rx bandwidth is 94Mbps
After apply the patch:
wait mode on:
100Mbps mode: tx bandwidth is 94Mbps
rx bandwidth is 94Mbps
Wait mode on cause enet interrupt has long latency, which
results in BD entries are full and stop tx queue, so cpus
have more chance to enter wait mode.
Incresing TX BD entries can properly accommodate the blance
between BD request before tx packets and BD release after tx
completion in interrupt process.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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If in the early suspend mode without any other
wakelock except the gadget one, user unplug the
usb cable, the gadget udc suspend callback will
be called, and it releases the wakelock immediately.
At this time, the wake_unlock function will wakeup
the suspend workqueue to do system suspend, and
udc driver's status change can not be finished
before suspend. This causes replug in the usb cable
after resume, WinXP can not start the MTP correctly.
Just re-lock that wakelock for about 500ms in the
udc suspend callback does fix this issue.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Ethernet performance is downgraded when wait mode on in
100Mbps mode.
wait mode off:
100Mbps mode: tx bandwidth is 94Mbps
rx bandwidth is 94Mbps
wait mode on:
100Mbps mode: tx bandwidth is 30Mbps
rx bandwidth is 94Mbps
After apply the patch:
wait mode on:
100Mbps mode: tx bandwidth is 94Mbps
rx bandwidth is 94Mbps
Wait mode on cause enet interrupt has long latency, which
results in BD entries are full and stop tx queue, so cpus
have more chance to enter wait mode.
Incresing TX BD entries can properly accommodate the blance
between BD request before tx packets and BD release after tx
complete in interrupt process.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Conflicts:
arch/arm/mach-mx6/pm.c
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We should make sure clk_enable is called after clk_get.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Previous temperature range is -25C ~ 125C, according to latest
datasheet, change it to -40C to 125C.
Signed-off-by: Anson Huang <b20788@freescale.com>
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If GPU2D used PLL3 as root, we need enable PLL
during GPU power up flow so that we can power up
GPU2D properly.
Till now, this issue can only be duplicated on
Android.
Signed-off-by: Loren Huang <b02279@freescale.com>
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BUILD WARNING:
WARNING: arch/arm/mach-mx6/built-in.o(.data+0x7e44): Section mismatch in
reference from the variable sab_audio_data to the (unknown reference)
.init.rodata:(unknown) The variable sab_audio_data references the
(unknown reference) __initconst (unknown) If the reference is valid then
annotate the variable with __init* or __refdata (see linux/init.h) or
name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
In this patch, remove esai_p2p struct with init attribute.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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Fix HDMI build warning.
drivers/video/mxc_hdmi.c: In function 'mxc_hdmi_set_mode':
drivers/video/mxc_hdmi.c:1659: warning: assignment discards
qualifiers from pointer target type
drivers/video/mxc_hdmi.c: At top level:
driver/video/mxc_hdmi.c:1398: warning: 'mxc_hdmi_enable_pins'
defined but not used
Remove unused function mxc_hdmi_enable_pins() and mxc_hdmi_disable_pins()
from code. Fix defined but unused function build warning.
Added pointer conversion from const poniter to non-const pointer.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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--New sabresd(RevB4 ane above) change the ONOFF key(SW1) design,
the SW1 now connect to GPIO_3_29, so map it as the power key,
and map SW5 as the volume down key which being mapped to power
key for new boards.
--Old sabresd such as RevB or older still use SW5 as the power key
--Add SOC version check to identify different board revsion. It is the
simplest way to achive this before board id/rev are defined clearly.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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This commit resolve the merge error.
As PDK's IRQ trigger is enabled, so during merge
3way merge will combine them together, brings redundant
codes.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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1.config gpio dok for AC charger as wake up irq, config gpio uok
for USB charger as wake up irq.
2.add AC/USB charger detect in resume,fix charger detect status update
missing after attach AC/USB charger and resume system
Signed-off-by: Rong Dian <b38775@freescale.com>
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consider ripple, IR drop and pfuze tolerance, we need incrase VDDARM_IN and
VDDSOC_IN to 1.475V.
Signed-off-by: Robin Gong <B38343@freescale.com>
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Fix below build warning:
arch/arm/mach-mx6/irq.c: In function 'mx6_init_irq':
arch/arm/mach-mx6/irq.c:106: warning: unused variable 'reg'
arch/arm/mach-mx6/clock_mx6sl.c:1807:
warning: function declaration isn't a prototype
arch/arm/mach-mx6/clock_mx6sl.c:1535:
warning: 'tzasc1_clk' defined but not used
arch/arm/mach-mx6/clock_mx6sl.c:1576:
warning: 'mx6per2_clk' defined but not used
arch/arm/mach-mx6/clock_mx6sl.c:1708:
warning: 'ocram_clk' defined but not used
Signed-off-by: Anson Huang <b20788@freescale.com>
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HDMI PHY init function will been called four times during system resume.
The first call before pixel clock enable, so it will print
PHY PLL unlock message, but the PHY PLL will locked in the next
three times called. It will not affect HDMI PHY function.
Change message print function dev_err to dev_dbg.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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In MX6 series, HDMI audio driver is responsible for add IEC header to
audio samples. Driver would maintain variables to cover this work.
The old driver would cause memory access exceeding issue:
1. Resume from an playback. In this case, variable maintained by ALSA is
updated while variable maintained by HDMI driver is not updated. The
mmap copy operation would run into error state due to misalignment.
2. underrun!!! The same error would happens as the items above.
In this patch, add variable check while adding IED header.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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* Fix i2c3 pad settings, i2c3 conflicts with weim-nor and
spi-nor only in rev b target boards.
* For rev B targets setup extra pads.
* Fix indentation.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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* For rev_b target board add extra pads table,
separate pad definitions from I2C3 pad array
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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dump_reg() in msc_spdif.c will cause kernel BUG during Suspend/Resume,
because of calling clk_enable() in an interrupt for playback.
There's also a simular issue in capture case.
Capture'd be stopped after resume for suspending.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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On MX6Q/DL , there is only two set point of VDDSOC/VDDPU, one is 1.25V(1GHz),
another is 1.175V. And in arch/arm/plat-mxc/cpufreq.c will judge whether the
current cpu frequency is the highest set point(1G) or not to set the right
VDDSOC/VDDPU. The logic is also match to dynamic ldo bypass function, since the
change point is the highest set point too. But there is three set points of
VDDSOC/VDDPU in MX6SL , so the logic in cpufreq.c need to change. Now
VDDSOC/VDDPU will track with VDDARM fully.
Signed-off-by: Robin Gong <B38343@freescale.com>
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PLL1 was enabled without incrementing the usecount, and was
thus not getting disabled under certain conditions.
This causes 2 issues:
1. Increases the power.
2. Causes crashes on MX6SL in audio mode as ARM is switched
to PLL1 assuming its in bypass when entering WAIT mode. But PLL1
is enabled and not in bypass state.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add enough nops to suspend code when exiting due to a pending
interrupt. This is required so that we can guarantee that the
prefetch unit will not bring DDR out of self-refresh before
all of the DDR's IO pads are restored.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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This patch changes pwm backlight max density from 255 to 248
to workaround Hannstar LVDS panel unstable backlight issue
when density is set to 250 or 251.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 8747626ca0bcdb6c9525e28d3fbb170db462a299)
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Ensure that the transtion from low bus freq mode to
audio bus freq mode happens instantly. Don't schedule
the delayed work in this case else there will be a pause
in the audio playback.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Need to ensure that no page table walk occurs in DDR when it is in
self refresh and its IO pads are floated during suspend.
Hence we need to make sure that the translation of all the
addresses that the suspend code will access is in the TLB before
DDR cannot be accessed anymore.
So do a dummy read of IOMUX, MMDC, SRC and ANATOP regsiters.
Also need to add a dsb to drain all the write buffers before
DDR enters self-refresh.
Also ensure that the LDO bypass enable is reset if an interrupt
is pending before the system enters suspend.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fix couple of race-conditions associated with low power IDLE code:
1. Ensure that bus freq mutex is used in the suspend/resume function
2. Ensure that the usecount of pll2 is incremented/decremented when
ARM is switched to run from PLL2_PFD_400. And PLL2 is enabled/disabled
when necessary.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Need to ensure that the ARM_CLK rate stays exactly the same
when moving ARM_CLK from PLL2_PFD_400 to PLL1 when system
enters 24MHz state. Also need to ensure that PLL1 is enabled
before relocking the PLL to the correct rate.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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1) In the interrupt handler, we access sync interrupt
control registers 2 times, and each time with spin
lock being held and then released, which may cause
potential racing on the registers. We see that
as long as the racing happens with two displays
enabled on the same IPU, one IPU display channel
will lose EOF interrupt and it makes its fb's pan
display ioctrl fail with timeout. This patch changes
to hold the spin lock one time for the whole irq
handler, as the handler should return quickly.
Holding and releasing the spin lock unnecessarily
may bring performance penalty as well.
2) We do not need to use spin_lock_irqsave() and
spin_unlock_irqrestore() in the interrupt handler,
as we are already in the hard irq context. Using
spin_lock() and spin_unlock() is enough to protect
the registers.
3) Clear an interrupt control bit as soon as its related
handler finishes.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit c5d3731fa0880a65efafb4826d3722aacb79edd5)
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There're two imx6q_add_ecspi() defines, remove one.
Signed-off-by: Robby Cai <R63905@freescale.com>
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As we define ERR interrupt with 0 irq resource id and SYNC
interrupt with 1 irq resource id in platform-imx_ipuv3.c,
we wrongly assign them in IPUv3 driver.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 52c9fc323e0f72e53de6fe0c6f7012fe7adf14b4)
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Need to ensure that check for usecount in clk_set_parent
occurs within the protection of the clock mutex. Else
there is a chance that the usecount can be decremented
(and the clock disabled) after the check.
Also add back the code to maintain the correct usecount
for pll2_pfd_400.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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