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offset high_bus_count+1 when m4 is enabled
Signed-off-by: Teo Hall <teo.hall@freescale.com>
(cherry picked from commit 58983b6522c324affdbbeaa5b7b192a673c615a7)
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The spi nor port1 is used by m4 on imx6sx sabreauto board.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
(cherry picked from commit 75eb4493d701fc068a2969b038cb0254ddc84b2c)
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Current driver will meet the following warning on MX6SL platform which does
not support ADMA.
It is caused by the driver is using fixed scatter gather DMA not matter whether
the host supports or not. Then the host without ADMA capability will warning
if found the DMA sg_count is non-1.
Change the driver a bit to avoid multi DMA scatter list if found the
host->max_segs is only 1 to fix the issue.
root@imx6slevk:~# udhcpc -i wlan0
udhcpc (v1.23.1) started
Sending discover...
Sending select for 192.168.1.11...
Lease of 192.168.1.11 obtained, lease time 86400
/etc/udhcpc.d/50default: Adding DNS 192.168.1.1
root@imx6slevk:~# ------------[ cut here ]------------
WARNING: CPU: 0 PID: 954 at /home/jenkins/jobs/Standalone-X11_with_mfgtools/workspace/temp_build_dir/build_fsl-imx-internal-x11/tmp/work-shared/imx6slevk/kernel-source/drivers/mmc/host/sdhci.c:839 sdhci_send_command+0xc64/0xd10()
Modules linked in: bcmdhd evbug [last unloaded: bcmdhd]
CPU: 0 PID: 954 Comm: dhd_dpc Tainted: G W 3.14.52-1.1.0_ga+g76946e8 #1
[<80014a68>] (unwind_backtrace) from [<80011758>] (show_stack+0x10/0x14)
[<80011758>] (show_stack) from [<80720180>] (dump_stack+0x7c/0xbc)
[<80720180>] (dump_stack) from [<80031df8>] (warn_slowpath_common+0x70/0x8c)
[<80031df8>] (warn_slowpath_common) from [<80031eb0>] (warn_slowpath_null+0x1c/0x24)
[<80031eb0>] (warn_slowpath_null) from [<804d5d2c>] (sdhci_send_command+0xc64/0xd10)
[<804d5d2c>] (sdhci_send_command) from [<804d74e8>] (sdhci_request+0xc0/0x1f0)
[<804d74e8>] (sdhci_request) from [<804c218c>] (__mmc_start_req+0x60/0x84)
[<804c218c>] (__mmc_start_req) from [<804c25a4>] (mmc_wait_for_req+0x10/0x20)
[<804c25a4>] (mmc_wait_for_req) from [<7f27ff6c>] (sdioh_request_packet_chain+0x368/0x400 [bcmdhd])
[<7f27ff6c>] (sdioh_request_packet_chain [bcmdhd]) from [<7f280da4>] (sdioh_request_buffer+0x124/0x294 [bcmdhd])
[<7f280da4>] (sdioh_request_buffer [bcmdhd]) from [<7f27f6dc>] (bcmsdh_send_buf+0x94/0x108 [bcmdhd])
[<7f27f6dc>] (bcmsdh_send_buf [bcmdhd]) from [<7f28e98c>] (dhd_bcmsdh_send_buf.constprop.25+0x80/0x220 [bcmdhd])
[<7f28e98c>] (dhd_bcmsdh_send_buf.constprop.25 [bcmdhd]) from [<7f28f454>] (dhdsdio_txpkt.constprop.24+0x928/0xa2c [bcmdhd])
[<7f28f454>] (dhdsdio_txpkt.constprop.24 [bcmdhd]) from [<7f28f6b0>] (dhdsdio_sendfromq+0x158/0x3c4 [bcmdhd])
[<7f28f6b0>] (dhdsdio_sendfromq [bcmdhd]) from [<7f2913d4>] (dhdsdio_dpc+0x2e8/0x1034 [bcmdhd])
[<7f2913d4>] (dhdsdio_dpc [bcmdhd]) from [<7f24a270>] (dhd_dpc_thread+0xe8/0x124 [bcmdhd])
[<7f24a270>] (dhd_dpc_thread [bcmdhd]) from [<8004ca6c>] (kthread+0xcc/0xe4)
[<8004ca6c>] (kthread) from [<8000e500>] (ret_from_fork+0x14/0x34)
Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com>
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The previous fb buffer management has two problems:
1. After reallocate a bigger buffer and free the old buffer,
user space app doesn't know this and may continue accessing
the old buffer.
2. The freed buffer contents will be lost.
So, this patch allocates a big enough fb buffer(32MB) from the
beginning and never reallocates it.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
(cherry picked from commit c76a37e342369675aa9ef2efde6373d288c2f013)
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The timeout_clk calculation code for SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK case
is common and could be moved into common sdhci_do_set_ios, then platform code
which is not using sdhci_set_clock does not need to write the same code again.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 03d6f5ffc5c469e66bfe0a7d8120d29d4c3c07c9)
Conflicts:
drivers/mmc/host/sdhci.c
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The timeout_clk calculation code in sdhci_add_host is meaningless for
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK.
So only execute them with no SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK set.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 28aab053396125c8e191537ec2b9781ec0174b04)
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The default sdhci driver write 0xE into timeout counter register to
set the maximum timeout. The value is not correct for uSDHC since the
max counter value for uSDHC is 0xF.
Instead of using common timeout code in sdhci, we implement esdhc_set_timeout
to handle the difference between eSDHC and uSDHC.
Currently we simply set the max timeout value as before.
But in the future, we probably may implement IMX specific timeout
setting algorithm and use suitable timeout for different CMDs.
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit e33eb8e2818c9a7b41bac68a1c83ee4c136af9ba)
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Currently the common code assume 0xE is the maximum timeout counter
value and use it to write into the timeout counter register.
However, it's fairly possible that some other SoCs may have different
max timeout register value. That means 0xE may be incorrect and
becomes meaningless.
It's also possible that other platforms has different timeout
calculation algorithm. To be flexible, this patch provides a .set_timeout
hook for those platforms to set the timeout on their way if they need.
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit b45e668af4439bfc52ed92af44b6400661ba7ec8)
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The default sdhci code use the 1 << 27 as the max timeout counter to
to calculate the max_busy_timeout, however it's not correct for uSDHC
since its the max counter is 1 << 28.
Implement esdhc_get_max_timeout_cout to handle it correctly.
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 10fd0ad967c05cda16b25f862e2a45eb63d83a21)
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Currently the max timeout count is hardcode to 1 << 27 for calcuate
the max_busy_timeout, however, for some platforms the max timeout
count may not be 1 << 27, e.g. i.MX uSDHC is 1 << 28.
Thus 1 << 27 is not correct for such platform.
It is also possible that other platforms may have different values.
To be flexible, we add a get_max_timeout_count hook to get the correct
maximum timeout value for these platforms.
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit a6ff5aeb9b31f7b71a8566f8e130ad66bd103d20)
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Rename host->max_discard_to to host->max_busy_timeout, to reflect that
it tells the mmc core layer about the maximum supported busy detection
timeout by the host.
This timeout is at the moment only applicable to erase/trim/discard
commands. By the renaming we provide the option of make use of it for
other commands that cares about busy detection. In other words, those
commands that wants an R1B response, like for example the mmc switch
command.
Do note that the max_busy_timeout is supposed to be specified only by
hosts supporting MMC_CAP_WAIT_WHILE_BUSY.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit 68eb80e06bfa06035d0304686124974780308fae)
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when SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK is set, timeout_clk is sdclk.
We need to update it when we change sdclk in sdhci_set_clock.
This allow to have a more precisse timeout and max_busy_timeout. This
can help for command that need a big busy wait (erase, ...).
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit fac6a52fe9b14851d56b3c19c3d5a95790c46fac)
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counter"
Revert the patch and using upstream version instead.
This reverts commit 056ef389fba70e2de8d1c5d976a1c1bd0578d381.
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SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER"
Revert the patch and use upstream version instead.
This reverts commit a9935446d897ff68167af82eca30b96fb96f0f7a.
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Checks EXT_CSD_PARTITION_SETTING_COMPLETED bit before
computing enhanced user area offset and size, and
adding mmc general purpose partitions. The two needs
EXT_CSD_PARTITION_SETTING_COMPLETED bit be set to be
valid (as described in JEDEC standard).
Warn user in case of misconfiguration.
Signed-off-by: Grégory Soutadé <gsoutade@neotion.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Replace ext_csd "enhanced_area_en" attribute by
"partition_setting_completed". It was used whether or
not enhanced user area is defined and without checks of
EXT_CSD_PARTITION_SETTING_COMPLETED bit.
Signed-off-by: Grégory Soutadé <gsoutade@neotion.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Move code that manages user area and general purpose
partitions into functions.
Signed-off-by: Grégory Soutadé <gsoutade@neotion.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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According to schematic, the pad used for CAN STBY signal
should be EPDC_DATA14, not GPIO1_IO07. So correct it.
And due to pin is conflict with epdc, so we also update
the imx7d-sdb-epdc.dts.
Reported-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com>
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M4 will use UART2, and RDC is configured that kernel can not
access. If still enable it, kernel will panic.
To validation board, disable gpio-keys, since m4 will use volume keys.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit ccd54fd2096b8f3443bafd0b86499e1eda027fc9)
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Attempt to read volatile register when cache_only is set will return
EBUSY. After playback/record, wm8962_runtime_suspend function will set
cache_only flag, so the volitale register ALC2 can't be read from cache.
Separate ALC Coefficients to four reigsters, the volatile register ALC2
will be read from hardware instead of cache.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
(cherry picked from commit 5ec8878be12530517b4c8ae307441a0ac16071a3)
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After removing idle_bias_off, it will not set bias to off after playback,
it just set bias to standby, and will not power down codec VREF, so it can
decrease the obvious pop noise at the first second.
Only in suspend, it will set codec bias to off.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
(cherry picked from commit ca7958ba19f5cee32215894fc7664b3451f7e9e6)
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There is a substantial amount of drivers that in go to SND_SOC_BIAS_OFF on
suspend and go back to SND_SOC_BIAS_SUSPEND on resume (Often this is even
the only thing done in the suspend and resume handlers). This patch
introduces a new suspend_bias_off flag, which when set by a driver will let
the ASoC core automatically put the device's DAPM context at the
SND_SOC_BIAS_OFF level during suspend. Once the device is resumed the DAPM
context will go back to SND_SOC_BIAS_STANDBY (if the context is idle,
otherwise to SND_SOC_BIAS_ON).
This will allow us to remove a fair bit of duplicated code from the drivers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 86dbf2ac6fcb2d2932d4610f2dfe0954aa0633f7)
Conflicts:
sound/soc/soc-core.c
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On i.MX6QP SabreSD board, VDDCORE is from PFuze's SW2, this
is different from i.MX6QDL SabreSD board, which is from SW1A/B.
Signed-off-by: Anson Huang <Anson.Huang@freescale.com>
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Sim card CVCC is determined by the gpio value from sim controller.
How the CVCC is controlled on both post card boards is decribed below.
NCN8025:Vcc=ACTIVE_HIGH?5V:3V
TDA8035:Vcc=ACTIVE_HIGH?5V:1.8V
Different sim cards have different CVCC range. To support all cards
with same dts, this patch set gpio active high.
Signed-off-by: Gao Pan <b54642@freescale.com>
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Change pad settings to improve signal quality.
Signed-off-by: Gao Pan <b54642@freescale.com>
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sim_activate() process is contained in the cold reset.
Thus, it is redundant and should be removed.
This patch also adds comments to cold reset process.
Signed-off-by: Gao Pan <b54642@freescale.com>
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wlreg_on regulator always on will make WiFi module unable to do reset
during rmmod, then the re-insmod will fail.
In stead of make wlreg_on always on, we make vmmc regulator always on
for BT to work properly.
Then WiFi can still function well on wlreg_on regulator enable/disable.
Fixes: commit f17b5e5be (dts: mx6ul evk: set regulator wlreg_on always on)
Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com>
(cherry picked from commit e92b727494b10c7a13e9491f55fc07a7ed7622a3)
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because the registers are reset to default value in interrupt handler,
we need reinitialize lut_stat to 0 otherwise the LUT registers will
not be set due to the following logic judgement in pxp_set_lut():
if ((pxp->lut_state == lut_op) &&
!(use_cmap && pxp_conf->proc_data.lut_map_updated))
return;
lut setting here...
pxp->lut_state == lut_op;
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit 67c3aa3d256bda575911d3079507185f7d649287)
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make savedefconfig shows CONFIG_KEYBOARD_SNVS_PWRKEY and
CONFIG_MXC_MLB150 also needs to be removed.
So remove them together.
Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com>
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The default gpio flag is 0 which actually means ACTIVE_HIGH.
However, it should be ACTIVE_LOW.
Change it using correct macro directly.
Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com>
(cherry picked from commit 54705942f95d1adeace336a1b67240572538fb24)
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The TF card slot on uSDHC2 does not support CD function,
so add non-removable property.
Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com>
(cherry picked from commit 803f8063be535de42316bbc1faadc6a117f7cadb)
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Remove unnecessary workqueue for rx path to reduce the latency.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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SNVS clk now is enabled/disabled dynamically in order to save
SNVS domain power, before suspend, its clk is enabled for
register access, better to disable it after resume to make
sure SNVS power is low enough in case there is no SNVS clk
disable during driver resume phase.
Signed-off-by: Anson Huang <Anson.Huang@freescale.com>
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Murata adapter VDDIO is derived from sd slot VMMC supply, if usdhc cannot
detect sd/sdio card, VMMC is shutdown that causes VDDIO has no voltage, and
bt cannot work. So BT depends on VDDIO/VMMC.
Now the workaround is set wlreg_on alwasys on, usdhc can detect wifi card
and supply VMMC 3.3V voltage, so that Murata adapter VDDIO has power supply.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add Murata Type ZP module support for 9x9 evk.
Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com>
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non GPIO function before lpsr suspend
It's hardware issue that if there are interrupts in GPIO1, the system
will not enter lpsr suspend state.
gpio1_12 pin is used as headphone detect pin for wm8958 sound card. If
headphone is not plugged in, the gpio1_12 pin is high level. When lpsr
suspend without headphone plugged in, gpio will be powered down and
there will be a interrupt in the gpio1_12 pin.
So we should avoid thus interrupt. We fix this issue by configuring
gpio1_12 pin to non GPIO function before lpsr suspend.
Because ALSA will set SAI pins to sleep state before suspend, and will
not set them to default state after resume if cpu dai is not active. So
we'd better remove non SAI pins from SAI pin group, and let iomuxc to
control the gpio pin state.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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add an empty sentinel entry to avoid the struct of_device_id is not
terminated with a NULL entry issue.
Signed-off-by: Han Xu <b45815@freescale.com>
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In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.
In non-small y resolution cases(>9 lines), we choose to check the STORE_BLOCK_Y
field of the register HW_PRE_STRORE_ENGINE_STATUS to determine the bad window
to update the SDW_UDPATE bit of the PRE_CTRL register. According to the
description of the STRORE_BLOCK_Y field in block mode, the field indicates the
Y coordinate of the block currently being rendered. Thus, we should round up
the real display y resolution to 4 lines to align with the block high(the out-
standing lines are cropped by PRG and IPU). To maximize the safe window, we
just need to avoid updating the shadow bit during the last block of lines.
To conclude, the bad window for block mode is (store_block_y == 0 ||
store_block_y >= DIV_ROUND_UP(y_resolution, 4) - 1).
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 1e21175555e4f35f87130a5f8839fac6a3e998b5)
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fix the bch setting issue when system suspend/resume, the bch geometry
only need to be saved to debugfs in driver initial stage
Signed-off-by: Han Xu <b45815@freescale.com>
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Add mipi dsi to imx7d 19x19 ddr3 arm board dts file.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Keep SNVS clock before poweroff by SW, otherwise PMIC_ON_REQ can't be pulled
up if ONOFF key pressed next time. This is design limitation.
Signed-off-by: Robin Gong <b38343@freescale.com>
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The 'OR' operation should be '||', so fix it.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit 9d592bb4453fc1769cff503b1533d0124a9a60bc)
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Remove the non-existed dts file from Makefile.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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The patch re-enable Murata BT as commit 117ba2ebb3fd define.
Since commit:76946e805b5d don't set murata bt/wifi as default in dtb and
add extra dts file to support Murata BT/WIFI, to align with this commit,
move BT support in the extra dts file.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Since commit:76946e805b5d don't set murata bt/wifi as default in dtb, to align
with this commit, firstly revert the previous murata BT support patch, and then
add bt support in imx6*-btwifi.dts.
Revert "MLK-11694 ARM: dts: imx6x: add Murata BT ZP (bcm4339) module support"
This reverts commit 117ba2ebb3fdf537379268786d5626cbe4b4799b.
Conflicts:
arch/arm/boot/dts/Makefile
Signed-off-by: Fugang Duan <B38611@freescale.com>
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suspend/resume
This reverts commit 12fee3d24574bd084e8b6fa1dcaf84a084298c9a.
The commit:12fee3d24574 intruduce MDIO read/write timeout when Ethernet
down and up after Mega/Fast off. The patch just revert the patch.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Since the version of the imx6qp's ahci controller
is same to the version of imx6q ahci controller.
So, this work-around should be applied to imx6qp
ahci too.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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enable sata support on imx6qp sdb board.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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Add Murata Type ZP (BCM4339) module support on below platforms:
- i.MX6Q/DL/QP SabreSD(SD2 slot) + Murata adapter V2.0
- i.MX6SX SDB (SD3+SD2 slot) + Murata adapter V1.0 & SD EXT card
- i.MX6SL EVK (SD1+SD3 slot) + Murata adapter V1.0 & SD EXT card
- i.MX6UL SDB RevC (SD1 slot) + Murata adapter V2.0
Note: MX6Q/DL/QP SabreSD board requires HW rework.
Please refer to rework guide specified in schematic.
Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com>
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Remove the timestamp usage in the 'MXCFB_WAIT_FOR_VSYNC'
ioctl handler, since the 64 bit timestamp would cause
data overflow when writing it to user memory.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
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