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Change-Id: I30872e9905b7bdf1cca56e53089e5cfde7586798
Reviewed-on: http://git-master/r/1026
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Change-Id: Iffad8a511bb6434b26e58d8dacf24a5751c23610
Reviewed-on: http://git-master/r/1028
Reviewed-by: Acorn Pooley <apooley@nvidia.com>
Tested-by: Acorn Pooley <apooley@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Normally, when the system goes into suspend, all the storage cards are
removed and later re-enumerated upon resume. During re-enumeration the
device name and number are not guaranteed to be the same as they were
during bootup. This can cause issues if rootfs falls on one such
device.
When the MMC_UNSAFE_RESUME config is enabled, it will prevent kernel
from unmounting the mmc cards before suspend. Upon resume the cards
will still be using the same device id as they were before suspend.
Change-Id: Ibc1511c5feb0391dc644df2d710e386ec0d353ce
Reviewed-on: http://git-master/r/994
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Updated VDE clock configuration policy - allowed to use high frequency
PLLC for VDE targets within 100MHz-200MHz range. This range was covered
by low frequency PLLP0, but better divider granularity achieved with PLLC
results in lower voltage requirements.
Change-Id: I922dbd8db19dc19339db5bfbf2651604e28e789d
Reviewed-on: http://git-master/r/1007
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Sharad Ranjan <shranjan@nvidia.com>
Tested-by: Sharad Ranjan <shranjan@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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As per the harmony power tree VDDIO_PEX_CLK is the T20's
3.3V PCIe supply. It is sourced from LDO0 of the PMU. By
default, LDO0 is off.
VDD_1V5 is the 1.5V supply for the PCI Express Mini Card
connectors. It turns on automatically in tandem with the
general-purpose 3.3V domain.
If there are no active pcie devices on the bus turn off
the VDD_1V5 power rail.
Change-Id: I518368937aa36e7c73fbb93c28a39706903a614d
Reviewed-on: http://git-master/r/1019
Reviewed-by: Kenneth A Radtke <kradtke@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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This fix corrects the pinmux configuration so UART-A is mapped to SDIO1 pins
when ULPI is used. AP will be able to communicate with the ULPI modem through
both UART and ULPI.
Change-Id: I268a76496bd5371c2b757b0133eb0f276234504f
Reviewed-on: http://git-master/r/1005
Tested-by: Szming Lin <stlin@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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With CL#5705540 USB host functionality on OTG port has broken
on Whistler.Also Device dis-connection and connection on root
port(USB3),makes host functionality broken. So this needs to
debugged further. However for Harmony both USB1 device and USB3
integrated hub are working fine with-out any issue. So reverting
the change for Whistler configuration only.
Bug 669288 :[AP20/Android/Whistler]: USB devices not working.
Tested on : Whistler and Harmony
Tested for USB host functionality on OTG port
Tested for USB host functionality on USB3 with
multiple connection/dis-conenction.
Change-Id: Id1c2157d796e095ff66e5002b5d00958a89a7bf7
Reviewed-on: http://git-master/r/1008
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Fixed an incorrect calculation for skipping to the next byte of bond-out
information. Bailing out of a byte early would result in an incorrect offset
being used for subsequent module ids resulting in incorrect modules being
marked as bonded out.
Change-Id: Ia5cb449006c2d3b825097c852c21f4e1346e6696
Reviewed-on: http://git-master/r/1024
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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- Don't signal the shutdown thread until the thread
process the SNDRV_PCM_TRIGGER_STOP call. The Kthread_stop()
call is a blocking call that waits until the kthread_should_stop()
returns.
- Set the prtd->state to SNDRV_PCM_TRIGGER_STOP in pcm_common_close
specifically to ensure proper clean-up and to handle the case
where application exits without triggering the STOP call.
- wait for the buffer done notification for the buffers queued in
before setting mixer state to stop.
- For Bug 667787 [LDK/Whistler/ALSA]"arecord" app hung
with DVD quality .raw audio recording (Mono/Stereo).
Change-Id: Id9c13bbd2dd0b5f90b3c545677eddfa05849c45f
Reviewed-on: http://git-master/r/997
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Tested-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Change-Id: I1db2c4cba29e0d4c34cc7d34c4a1be0cfb13caa5
Reviewed-on: http://git-master/r/1002
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Moved AVP low corner to 36MHz (from 24MHz) and EMC low corner for LPDDR2
platforms to 18MHz (from 50MHz), as determined by audio use case testing.
Increased low corner detection hysteresis for CPU to 4MHz (from 1MHz),
and removed half of activity margin from low corner hit requirements in
case when no starvation/busy hints are present.
Change-Id: Ia3ccbaefb542066a20a1ac238e88026655c76223
Reviewed-on: http://git-master/r/985
Reviewed-by: Niranjan Wartikar <nwartikar@nvidia.com>
Tested-by: Niranjan Wartikar <nwartikar@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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add LP2 (CPU power-gated) and LP3 (CPU flow-controlled) idle states
for Tegra 2 CPUs through the kernel cpuidle interface
exit latency for LP2 mode is a very rough approximation; the actual
latency is dependend on the CPU frequency
Change-Id: I115a3be6a065bcdad4149ce90cf4139b42062a43
Reviewed-on: http://git-master/r/951
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Change-Id: I5dacba846a7c979cf556470699c4b1e036c72ede
Reviewed-on: http://git-master/r/970
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Use CONFIG_ARCH_TEGRA_XX_SOC defines for differentiating
between various tegra SOCs instead of getting the SOC caps
from the RM. With this change enabling quirks for various
chips would be much simpler.
Tested on Android, whistler.
Bug 661035 SD 3.0 support in the linux native driver.
Change-Id: I0a85f3464d00080673a351d1614f311f1855bdae
Reviewed-on: http://git-master/r/969
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Normally, when the system goes into suspend, all the storage cards are
removed and later re-enumerated upon resume. During re-enumeration the
device name and number are not guaranteed to be the same as they were
during bootup. This can cause issues if rootfs falls on one such
device.
When the MMC_UNSAFE_RESUME config is enabled, it will prevent kernel
from unmounting the mmc cards before suspend. Upon resume the cards
will still be using the same device id as they were before suspend.
Change-Id: I2821b20bbd3ecb753bdc8c90297e41c396c66364
Reviewed-on: http://git-master/r/988
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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bug 642072: Power Aware NvRM Daemon
Use blocking sysfs reads to notify from pm_notifier (kernel) to
nvrm_daemon (userspace).
Change-Id: I9119733994613ac38c547ec7808c6afc811a25c2
Reviewed-on: http://git-master/r/984
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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With this change, display comes up with a single key press; but the catch is
that it only works with "Windows" and "F3" keys. This limitation is posed by
Android and not EC.
NOTE that for other than "Windows" and "F3" key presses, the system does wake up,
but an additional "Windows"/"F3" key press is still required to get the display up.
Also, explicitly letting EC know that it should allow any keyboard/mouse event
for wake-up. This is the default behavior, but still wanted to explicitly
specify.
Change-Id: I2a1e7d90fbbfd810f2334ee3832e193bfb5e45b1
Reviewed-on: http://git-master/r/986
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Change-Id: I316f614ae6d866f642a1ae5f6b1e19b37e50cae2
Reviewed-on: http://git-master/r/973
Tested-by: Sheshagiri Shenoy <sshenoy@nvidia.com>
Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Change-Id: Ie798a5dac7b450fd987f90d839549015c24ba2ce
Reviewed-on: http://git-master/r/875
Tested-by: Sheshagiri Shenoy <sshenoy@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Tested-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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add ARCH_HAS_CPU_IDLE_WAIT and ARCH_HAS_DEFAULT_IDLE configuration,
and expose default_idle and cpu_idle_wait
cpu_idle_wait implementation based on the implementation in the x86 tree
Change-Id: Ie24b6336db833cc638868abfdba822889646d0a8
Reviewed-on: http://git-master/r/950
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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In the case where cpuidle_idle_call() returns before changing state due to
a need_resched(), it was returning with IRQs disabled.
The idle path assumes that the platform specific idle code returns with
interrupts enabled (although this too is undocumented AFAICT) and on ARM
we have a WARN_ON(!(irqs_disabled()) when returning from the idle loop, so
the user-visible effects were only a warning since interrupts were
eventually re-enabled later.
On x86, this same problem exists, but there is no WARN_ON() to detect it.
As on ARM, the interrupts are eventually re-enabled, so I'm not sure of
any actual bugs triggered by this. It's primarily a
correctness/consistency fix.
This patch ensures IRQs are (re)enabled before returning.
Reported-by: Hemanth V <hemanthv@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Len Brown <len.brown@intel.com>
Cc: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
Tested-by: Martin Michlmayr <tbm@cyrius.com>
Cc: <stable@kernel.org> [2.6.31.x]
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Change-Id: Ide8e1fe20ba7b30ae321f520b620dfb2e3614022
Reviewed-on: http://git-master/r/982
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Updated graphics clock control: added 2D/EPP frequency scaling following
EMC clock, and reduced Host1x clock to 108 MHz to make sure it can be
run at low voltage always (per previous evaluation Host1x at 83MHz works
well with 240MHz cap on modules behind Host, hence 108MHz setting with
current 300 MHz module cap).
Change-Id: I9d5d89b38f08b99a805ad22459a84cb580dce05c
Reviewed-on: http://git-master/r/981
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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1. Making Battery and AC present as a wakeup source
2. Registering battery events:present, charging, remaining capacity
3. Handling battery odm flags and events in nvec_battery.c
Change-Id: I814960ab5f065e6aaad72ea1c403ad9c8d6a1af8
Reviewed-on: http://git-master/r/907
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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The scratch registers had to be shuffled around a bit
to match the bootrom's scratch map.
Change-Id: Iddcefbd23fdaccb2215b70bc5f188fadaf8ec194
Reviewed-on: http://git-master/r/918
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Currenttly to check the board type E1108 in nvodm_query.c, function
NvOdmIsE1108Hynix() is used. That is EMC DFS specific, so it is
replaced with the generic check
"NvOdmPeripheralGetBoardInfo(BOARD_ID_WHISTLER_E1108, &BoardInfo)".
Bug 666427 : [whistler/android/power] - suspend power has increased
by 4mW
Tested on :Whistler E1108
Change-Id: I7c8cdb9da2891d3b8ade738509024a78f6f6d38b
Reviewed-on: http://git-master/r/943
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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squash hotplug code into platsmp file, to limit overall spaghettiness
Change-Id: I6704323837ad545564a0dcfd47894835f2adeb1a
Reviewed-on: http://git-master/r/948
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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On platform with no PMU property CPU PowerGood timer was loaded from
uninitialized stack variable, instead of default delay - fixed.
Change-Id: I5c29199d40e0e39b095c72c0cb64f4ceda51013d
Reviewed-on: http://git-master/r/963
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Clipped target pixel clock frequency to display h/w maximum, instead of
asserting when target is above the limit. It would allow to complete
clock configuration if low boundary of tolerance range is below maximum.
Change-Id: I5167dd0d680e08dba6511a259425814e712c4b0d
Reviewed-on: http://git-master/r/920
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Swapped the order low corner (LC) limit and starvation hint are applied.
After this commit, LC is applied 1st. Thus, it is guaranteed that initial
starvation boost is always on top of LC (and not "under water").
Change-Id: I6bd8f2ec9f04fb51d7098a8702e4f1cf7779f4c8
Reviewed-on: http://git-master/r/935
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Re-arranged clock control locking scheme, so that clock configuration or
control operations and voltage control operations are locked sequentially
(was nested). The former operation is guarded by the spin-lock, the latter
- by the scheduler mutex (shared with DVFS and PMU transport).
Implemented preview mode to determine in advance if core voltage should
be raised before clock h/w is configured. Added pending voltage change
mechanism to "bridge" the preemptive gap between preview and actual h/w
configuration. Exceptions from the above scheme are clocks that share
PLL h/w resources with DVFS (not just voltage control): Display/DSI and
VDE. For these clocks old nesting scheme is used. This commit minimized
calls to the scheduler from clock control/configuration APIs; addressed
bug 650476 and bug 656965
Change-Id: I5b758af0badc75c1bd05d360702d13289cfcef5d
Reviewed-on: http://git-master/r/953
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Enabling USB port suspend, when they is no activity happening on the on
port. Example: For an usb port, when a USB hub is conneted without any
devices on down stream, then hub upstream port can be suspended until
device(s) connected on down stream to hub. We enabled this feature for
whistler and harmony by enabling config paramater CONFIG_USB_SUSPEND.
Bug XXXXXX : Enabling auto suspend for USB host
Tested on : Harmony and Whistler E1108
Tested on Harmony by conneting 7 port hub to port2 of SMSC LAN hub
Tested on Whistler by connecting 7 port hub on USB3.
Change-Id: Icaf7648c5014161f6652cbb8c3347732b4651d8c
Reviewed-on: http://git-master/r/946
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Change-Id: I6d5beb3962de5bef1109f4c8d57c7c8a0f5f98fb
Reviewed-on: http://git-master/r/952
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
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replace the existing timer code with a kernel-style implementation
reset the lp2 spare trigger to 0 following an lp2 wakeup, to prevent
a spurious interrupt from triggering if the wakeup source was not
the lp2 timer.
Change-Id: I4af642b15f024e43cf88f19751bdaad5279ebd9b
Reviewed-on: http://git-master/r/936
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Despite the claim in struct irq_chip header: "disable: disable the
interrupt (defaults to chip->mask if NULL)", it is not happening as
default_disable is empty. Fixed it. Should also fix bug 667376.
Change-Id: If0c39e3b4344701bbf235201c180d9c8ce56c489
Reviewed-on: http://git-master/r/947
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Since CONFIG_TEGRA_OTG is not defined in the whistler linux def config file
OTG driver is not getting loaded and causing the USB core to malfunction.
This is fixed by enabling the usb odm property mode as OTG only based on the
CONFIG_TEGRA_OTG. If OTG is not enabled then USB1 port behaves as device by
default.
Bug 664864:[Mobile LDK\LP1] unable to run LP1
Tested on ap20/whistler/android
Change-Id: I0e97596b1341a82652b57afb003c715dd0b7724b
Reviewed-on: http://git-master/r/944
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Tested-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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implement a keyboard input driver for tegra's internal matrix keyboard
controller (16x8 support on Tegra 2 class processors).
supports
* power management
* limit wakeup to a subset of keys
* platform-defined remapping of key to keycode
* platform-defined pin configuration
add support for converting tegra ODM kit APIs to kbc platform data, so
existing clients will continue to function
Change-Id: If1496e7ada4f6f18a3e98a15ebc5f925f254bf65
Reviewed-on: http://git-master/r/933
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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fix broken build of nvodm_kbc.c caused by path changes during initial
p4 to git merge
keyboard should be a wake event when the KEYBOARD_TEGRA driver is
compiled into the kernel
reduce the repeat and debouce times; the keyboard was nearly
unusable with a repeat ping time of 100ms
fix the row and column numbers for the select wakeup keys: the values
need to be absolute row & column offsets, not the harmony-local GPIO
enumerants (in which columns have numbers above rows), and the values
previously defined ([0,0] and [1,1]) aren't actually keys on the
satellite keyboard; change the values to the ESC and Windows keys.
Change-Id: I50bca7eee5c9101163b01e08457606cb4a5f32de
Reviewed-on: http://git-master/r/932
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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reimplement interrupt controllers following the kernel coding
conventions
propogate set_irq_wake signal from gpio chip to the primary chip
use IRQ_WAKEUP status to control masking and unmasking of interrupts
when entering low-power modes; non-wakeup interrupts are disabled
using with disable_irq, and are re-enabled after wakeup with enable_irq
ODM kit wakeup pads are configured with enable_irq_wake during the
board initialization
move context save & restore for the GPIO and interrupt controllers out
of power-context-t2.c and into their respective drivers; no distinction
is made between LP0 and LP1 context currently; if there is enough of a
performance difference to warrant reintroducing it, this can be done at
a later time.
delete now-deprecated NVIDIA GPIO IRQ code
bug 656008
Change-Id: I68f98f2442c50a93a7ad9cdfef87b630e8c132a9
Reviewed-on: http://git-master/r/931
Tested-by: Gary King <gking@nvidia.com>
Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Add mmap callback in alsa to support mmap mode.
For Bug:66326 [LDK/Whistler/ALSA] Add the mmap
support in ALSA.
Change-Id: Iecc128374ff365ef4fb92034d6256c6378bd1f20
Reviewed-on: http://git-master/r/909
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Manjula Gupta <magupta@nvidia.com>
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Added mechanism to reconfigure Maxim PMU power enable (PWREN)
input on Whistler necessary for LP0 core voltage control.
Change-Id: If7ee20956b39a96093da4094eda9ab64bce54503
Reviewed-on: http://git-master/r/923
Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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An ioctl to disable fb used to exist and called from
the nvrm daemon code. This was partially removed sometime
back and there are still traces of that code causing some
confusion which is cleaned up by this commit.
ioctl define is left as-is so maintain compatibility
to user mode code.
Change-Id: I3f792d6be075a8754ea448d588e484afc67bd8ba
Reviewed-on: http://git-master/r/878
Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
Tested-by: Venkata (Muni) Anda <vanda@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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are happening though a device connection on host port.
Currently for harmony, an intergrated SMSC hub present on USB3. Because
of this device connection is present on USB3 and USB power busy hints
are always on. To avoid this, for host by default busy hints are off and
USB busy hints will be on for :
1.Bulk and isochronus transfers
2.Interrupts transfers with buffer length >= 256.
Busy hint will be on for pre-defined amount of time
and after that busy hints will be off automatically.
With this in idle state power is reduced.
Tested on : Harmony
Enumeartion is happening fine.
LAN and USB HID devices are working fine
Change-Id: Ifd653bebfb52c7702f7d24bf11ccf93e62ea0f66
Reviewed-on: http://git-master/r/915
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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NvRm Gpio driver will be wrapper on the native gpio driver such that it
will provide the same existing api and implementation will be use the
native gpio driver. In this approach, it does not need to change the
existing gpio client driver.
Tested on whistler with sdcard insert/remove, touch panel and scroll wheel.
Tested on harmony with the suspend/resume.
Change-Id: I2fa98f8f62a111a1463c1e5b1034e145eaae42a3
Reviewed-on: http://git-master/r/851
Tested-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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- Remove using signal.
- fix bug 664864: unable to run LP1
- see also bug 642072: Power Aware NvRM Daemon
Change-Id: I952b8aa0aa4ea0c4c289fa1d20fc0bae3a98cac7
Reviewed-on: http://git-master/r/914
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Kaz Fukuoka <kfukuoka@nvidia.com>
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Separated EMC frequency low corners for LPDDR2 and DDR2. For now, kept
both limits the same as common floor before (50MHz).
Change-Id: Ieaa238f78ceb5a7f4f238ffe78c576bb7d5840b1
Reviewed-on: http://git-master/r/906
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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USB host is getting enabled when the odm usb property is set to None.
During the system initialization host enable condition was not checked properly
when Odm USB mode property is set to "NvOdmUsbModeType_None". Due to the wrong
condition, host controller is turned on and consuming the power.
Bug 665409: [whistler/android/power] - USB power consumption has increased
Tested on AP20 whistler
Change-Id: I47622e1da6ca2c9edd107df9b5e6de3953260f5c
Reviewed-on: http://git-master/r/908
Tested-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Integarting SMSC v1.01.06.03 (03/18/2010) LAN driver to tegra.
This new version is a power aware driver and support suspend/resume
functionality.
Bug 635375 : [AP20 \ Android] SMSC Ethernet LAN(9514) 3rd Party driver
power management in Android
Tested on : Harmony
Change-Id: I112a8d9805f3ce6fed45999130c7c8004865bb98
Change-Id: I112a8d9805f3ce6fed45999130c7c8004865bb98
Reviewed-on: http://git-master/r/884
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Implement suspend/resume functionality for the tegra-sdhci driver.
Call the sdhci_suspend/resume functions which handles the power off
and re-enumeration of sd memory cards. We ignore suspend/resume
requests for all sdio devices asssuming that the individual drivers
will manage their own power.
For tegra devices, the wifi driver implements its own early suspend
model and hence is ignored by the sdhci driver.
Change-Id: I5041d314123bac958da7775ee24bd2dc1be55ab5
Change-Id: I5041d314123bac958da7775ee24bd2dc1be55ab5
Reviewed-on: http://git-master/r/852
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Rahul Bansal <rbansal@nvidia.com>
Tested-by: Rahul Bansal <rbansal@nvidia.com>
Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
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- when mouse is not present or connected to board,
do not register the mouse driver with EC bus driver.
- Bug 663803
Change-Id: Iec11af103c4ab00a9d01e66969fceb6161cec1e2
Reviewed-on: http://git-master/r/862
Reviewed-by: Ninad Malwade <nmalwade@nvidia.com>
Tested-by: Ninad Malwade <nmalwade@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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AP20 pop chip is not having USB3 ID pin. Currently both pop and
non-pop whistler are using same odm query with Idpin type
as "Cable Id". Since, it is not reflecting correct Id pin type for
pop, causing the issue.
With this change based on the board type, proper id pin type is
returned as part of usb odm query for USB3. Without ID pin dynamic
detection of devices is not possible, so host functionality is
disabled for USB3 on pop boards. With this change USB3 host is
working for non-pop modules and no hang is seen with pop modules.
Bug 655520 : [AP20/Android/Whistler]: Device hangs after connecting
USB devices(mouse/keyboard).
Tested on : whistler E1109 and whistlerE1008
Change-Id: I5cd67c54756666e58cbc778da2b1015df27c14c6
Reviewed-on: http://git-master/r/795
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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