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2012-03-22ARM: tegra: clock: Fix Tegra3 EMC clock change procedureAlex Frid
Fixed EMC clock change procedure to skip XM2CLKPADCTRL register during shadow burst write, and set it within unshadowed section. Bug 836260 Original-Change-Id: Ief92c7d3957c9685b8c528297da2e905159a530d Reviewed-on: http://git-master/r/40748 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R5016ffd224db2b3eb6639a6b33063d1c27456b24
2012-03-22tegra: clocks: Remove shared clocks from sku_limitsmchourasia
"avp.sclk" and "bsea.sclk" are shared clocks and should be removed from sku_limits table as shared clocks are registered later and not available at the time of putting rate limits. Original-Change-Id: Idc85d37a06e764e03f08e31582dbd16c77ae4b16 Reviewed-on: http://git-master/r/38271 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6c4d95bbf32d713a3e78201f49bc612423e8b35c
2012-03-22ARM: tegra: add support for hardware statistic counterPrashant Gaikwad
Tegra2 chip has a hardware statistic counter for CPU/AVP/VDE/SYS modules. This commit adds the support for AVP statistics gathering and controlling avp clock during video playback. Bug 831892 Reviewed-on: http://git-master/r/35647 (cherry picked from commit 145885b03cd9fc625f2ff3460c59ebbb3d93c98e) Original-Change-Id: I441acbaf2cb8dd776529bafd4e13f50e31849afa Reviewed-on: http://git-master/r/39657 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R7271973f142f14fc8a11bdbc33ae6f76f6fd38b0
2012-03-22arm: tegra: renaming tegra3_mc_stats to tegra3_mcDonghan Ryu
tegra3_mc_stats is memory controller profiler for tegra3. it is originated from tegra2_mc and having different file name convention is pretty confusing. This change change the name of the files for tegra3. Original-Change-Id: Icd8c1f834e4af0daa8d8de6412b953274750883f Reviewed-on: http://git-master/r/38252 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R191a5bd02e389ad2594a012bcfd82712ac5f3c76
2012-03-22ARM: tegra: clock: Add Tegra3 emc high voltage bridgeAlex Frid
On Tegra3 platforms emc configurations for DDR3 rates below 300MHz can not work at high core voltage; the intermediate step (bridge) is mandatory when core voltage is crossing the 1.2V threshold (fixed for Tegra3 arch). In addition emc must run above bridge rate if any other than emc clock requires high voltage. EMC bridge is implemented as a special emc shared user: its rate is set once during emc dvfs table initialization; then, the bridge is enabled or disabled when sbus and/or cbus voltage requirement is crossing the threshold (sbus and cbus together include all clocks that may require voltage above threshold - other peripherals can reach their maximum rates below threshold). Bug 846693 Change-Id: Ib17448877583453250cf11adf6c5c94dab0fadcf Reviewed-on: http://git-master/r/39919 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Re546be46958b6bf8e491553679b1637eaf3786ff
2012-03-22arm: tegra: enterprise: init modem according to modem_idSteve Lin
Init baseband modems according to the modem_id passed from the bootloader. Bug 842870 Original-Change-Id: Ib8cd37877eb50ac67a337ef20dd6c6f631169578 Reviewed-on: http://git-master/r/39273 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rb3484d422dd0fbfbd80ac5ef62fe1aa7fa574c52
2012-03-22ARM: tegra: clock: Update Tegra3 PLLE spread settingsAlex Frid
Bug 818305 Original-Change-Id: I2560c342c1ad152f1563a29d7a3618c50ded7ef2 Reviewed-on: http://git-master/r/40113 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rec5fdd633170b8dba0ac4236618e503c8b1f761a
2012-03-22arm: tegra: dvfs: use 1.1 v for usbWen Yi
Set the working voltage for USB to 1.1 v. Bug 796594 Reviewed-on: http://git-master/r/30219 (cherry picked from commit af08f51a8c51b7b8d3f25ee7a2372f9d423b78e7) Original-Change-Id: I71332eaa238c1116bcb2c2555654ea65a648c702 Reviewed-on: http://git-master/r/40305 Reviewed-by: Xin Xie <xxie@nvidia.com> Tested-by: Xin Xie <xxie@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R17971c5c60e28d8816955cf6d834df4c7d3c272b
2012-03-22arm: tegra: fuse: support to burn fuses on the fieldVarun Wadekar
- follow the new sequence shared by the hardware team - merge Tegra2 and Tegra3.0 odm fuse burning into a single file Bug 796825 Original-Change-Id: Ia06d589eba95254a410016dce244375f27e22be0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/38404 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R740d7bd47eaa6231954ae98686272a755a4bce14
2012-03-22arm: tegra: remove unnecessary arm_pm_restart = tegra_pm_restartMayuresh Kulkarni
this is because, tegra_pm_restart internally calls arm_machine_restart(). however, arm_pm_restart is already set to arm_machine_restart() in arch/arm/kernel/process.c. the above was needed when the console flush code did not used kernel's reboot notifier mechanism. now it does use that mechanism, making the assignment arm_pm_restart = tegra_pm_restart redundent. Original-Change-Id: I4f2ef51740d7934f3dfe5e6ce749ee6f135f8106 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/37331 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rda63b4e0e0138ccfe2196cb4820315f6b543f4f5
2012-03-22ARM: tegra: clock: Use bus lock to protect shared bus updateAlex Frid
Protected shared bus update with bus lock - common for all shared bus users (update procedure was already covered by individual shared users locks, but it did not prevent concurrent access to shared rates list). Original-Change-Id: Ia0e6886265aff1f624802e0415fe8cecb887b507 Reviewed-on: http://git-master/r/39918 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R0e0ee997ce9347470e207910f7b4f6c42143717f
2012-03-22arm: tegra: dvfs: add fuse_burn to the dvfs tableVarun Wadekar
Bug 796825 Original-Change-Id: I8835427940905d90ca04955b5efe1605761c5554 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/38403 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R3dc69edfa374a47bcdd35e7acfd85d98ca7d66dc
2012-03-22arm: tegra: clocks: add fuse and fuse_burn clocksVarun Wadekar
keep fuse clock always enabled to allow fuse read writes from multiple clients Bug 796825 Original-Change-Id: Icb2693d791d08ca7083f9a61ab833425d2ab83b4 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/36504 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Re192b5ff54aea3ce762bd103b1a9a62ef718b81c
2012-03-22ARM: tegra: power: Powergate PCIE and SATA partitions on tegra 3Karan Jhavar
By defalut PCIE and SATA partitions are powergated. If needed, respective drivers should un-powergate these partitions. Also 3D,3D1 and MPE are not powergated at startup. Original-Change-Id: Ibc74868eb59af7c0e8b5a1ecd78e6f993dd5d3a6 Reviewed-on: http://git-master/r/35955 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Ra55d87d7d816d7cf0bea0d28e7865fa7760f869f
2012-03-22ARM: tegra: clock: Save/restore Tegra3 audio sync clocksAlex Frid
Save/restore Tegra3 audio sync clocks on entry/exit to/from deep sleep. Original-Change-Id: I3a6ddd3d7291760e6b36731d1ec7e401b8081690 Reviewed-on: http://git-master/r/40125 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rb26a85d1d08725e6b357a50b53ef1f61d3f52ce4
2012-03-22ARM: tegra: clock: Save/restore Tegra3 PLLD and PLLD2Alex Frid
Save/restore Tegra3 PLLD and PLLD2 on entry/exit to/from deep sleep. Bug 846707 Original-Change-Id: Ie3e558157fd4bcbe1b1e7f7c75ec1086a6742b79 Reviewed-on: http://git-master/r/40123 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Raddaa7cd52cae2dc75ea72e02bf7e15fad263d67
2012-03-22ARM: tegra: power: Restore Tegra3 EMC power setting after deep sleepAlex Frid
Bug 836334 Original-Change-Id: I19587e97af0addc62217466ee977c5afc33a6028 Reviewed-on: http://git-master/r/39854 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R2748dbb3f7308ae491e137062e2b0f940fb8185e
2012-03-22arm: tegra: devices: Set emc rate for avpPrashant Gaikwad
Set emc clock rate for avp client as required by the platform. Original-Change-Id: I10374e1967cda6a9f497ba0a95bd62c3b58ecc40 Reviewed-on: http://git-master/r/40167 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R54697789f03d9465339029b49cba336cb9592c88
2012-03-22ARM: tegra: la: Add support for latency allowance.vdumpa
Original-Change-Id: Ia6593fd6720e38f9bb0635fabe236675764cee91 Reviewed-on: http://git-master/r/36570 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R338465e38b998b4c6a8bfa4efc89003eac90d8b9
2012-03-22arm: tegra: gpio_get_value can read output gpioSeongho Joo
gpio_get_value only supports input pin. extend the usage for output pin. Bug 839772 Original-Change-Id: I5a8f5572148afde23e082af18f2e37377ae50bd1 Reviewed-on: http://git-master/r/36758 Tested-by: Seongho Joo <sjoo@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R021e8ff272e4cecd855a574b008dbf8663378970
2012-03-22arm: tegra: Fix build warningsScott Williams
Fixes "warning: passing argument 1 of 'param_get_uint' discards qualifiers from pointer target type" and "note: expected 'char *' but argument is of type 'const char *'" messages. Original-Change-Id: I7610dc0bde0cf3b9a7597f3892b09f7c31a156d1 Reviewed-on: http://git-master/r/36560 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R87f617932a52d873aa237072e14339627300cf5d
2012-03-22tegra: clocks: Fix in clock settingsmchourasia
clk_disable_locked should not be called when clk_enable_locked is failed. Original-Change-Id: I2524ec0198f62de2487723676ca7657d15757eda Reviewed-on: http://git-master/r/38273 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R1598bf84619449922c599d611a84dec791047837
2012-03-22arm: tegra: cardhu: Fix the issue of boot screen corruption.Kevin Huang
- The issue is due to the corruption of bootloader fb during kernel initialization. This change reserves the bootloader fb and then frees it until bootloader fb is copied to fb for Cardhu, Ventana, Whistler, Enterprise and Aruba. - Change color depth of Cardhu and Harmony to 32-bit. Bug 828271 Bug 832016 Original-Change-Id: I05ef5930ee68dcbd672a5cb59b4568a2c88a2e55 Reviewed-on: http://git-master/r/34966 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R92cd2153c44ac907fdf153a028429e7a5fa3fc23
2012-03-22arm: tegra: tsensor: driver instantiationBitan Biswas
Tegra internal tsensor driver supported for fuse revision 0.8 and above. Bug 661228 Original-Change-Id: I820f6b5f20c20bb2d1ba04266148f5969ab84444 Reviewed-on: http://git-master/r/36054 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R62574ff1667ad009dcf13f98e00b7af0ecca2016
2012-03-22arm:tegra:tsensor: device definitionsBitan Biswas
Tegra internal temperature sensor addresses defined Bug 661228 Original-Change-Id: I061ac9e7da3115d1e832e645582353f93378d291 Reviewed-on: http://git-master/r/36119 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Tested-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R62de8521a55164f582eb2b0f8ad5a83bbc02876c
2012-03-22video: tegra: nvmap: fix GART pin lockupsKirill Artamonov
Fix GART lockups caused by fragmentation by evicting mapped areas from iovm space after unsuccessful array pinning attempt. Fix double unpin error happening during interrupted submit. Fix possible sleep in atomic context in iovmm code (semaphore inside spinlock) by replacing spinlock with mutex. Fix race between handle_unpin and pin_handle. bug 838579 bug 838073 bug 818058 Original-Change-Id: I420447ffb4e02fb78a7987e22a537eefc16ff524 Reviewed-on: http://git-master/r/36129 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rd7c287d1a2ad3da50188788324ad908e19f34bb8
2012-03-22ARM: tegra: sysfs write permission for user onlyManoj Gangwal
Giving read-write permission for user only for sysfs attributes. Group and other will have only read permission. -clock: syncevents Bug 828100 Original-Change-Id: I14affc209e954a58de055e291093e31dc1dbfe16 Reviewed-on: http://git-master/r/39364 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R97f4eadb711717e788be7c4e4e8993d048cf1428
2012-03-22ARM: tegra: dvfs: Update Tegra3 CPU and core voltage dependenciesAlex Frid
Updated implementation of CPU and core voltage dependencies so that range limits can be changed for different versions of Tegra3 (rather than use fixed limits across entire Tegra3 architecture). Decoupled safe VDD step definition from range limit, and changed the step from 300mV to 100mV. Bug 841286 Original-Change-Id: I63e0bc9751048741a47a40410b54863984f91aca Reviewed-on: http://git-master/r/38179 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R665a6f859aa744e1b64a19d9ba5aa2f37581103e
2012-03-22ARM: tegra: power: Refactored kernel powergate codeKaran Jhavar
This change provides a centralized location for powergating modules. It would take care of switching on/off clocks while un-powergating/ powergating modules respectively. Bug: 814267 Original-Change-Id: Ic80dc517f634c29085c8e089bdaa32c6fd742710 Reviewed-on: http://git-master/r/31776 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Re0c233ed4bacc27feb7b210cddc6ff3e487c528f
2012-03-22tegra: power: correct LP0 sequenceJay Cheng
Change-Id: I5f548f11059039cbd830be483ecfa0c6671002e7 Reviewed-on: http://git-master/r/47365 Tested-by: Cho-Che Cheng <jacheng@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd7ef967c8b40295a04a0447eb8bbc8e2d577a48e
2012-03-22ARM: tegra: power: setup TTB0 for cacheable memoryJin Qian
Bug 862494 Change-Id: Ib7875ded150b3e9dc288a9ed90f6ded0a37014a3 Reviewed-on: http://git-master/r/47246 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R11be58a9cf3a46fadf985e209e26dc00a8d87c58
2012-03-22ARM: tegra2: power: fix LP2 statistics reportingJin Qian
Bug 863108 Change-Id: I5cc4e3ba58daeaeb527871026c85bdca5f6362f2 Reviewed-on: http://git-master/r/47232 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R843a5cf74874bad3999bc55caa0eb8cad04cc555
2012-03-22ARM: tegra: Fix build error when CONFIG_SMP is not selectedScott Williams
Change-Id: I2420730290c7ecb407e6f30c8a6159ceadfabbbe Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/47589 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rb177b1e8ed9ce89c732319f49525588c5c0dd9d0
2012-03-22ARM: tegra: Delete obsolete tegra_audio_device declarationScott Williams
Change-Id: I119fdbbc2440f8a7e64e2f3b5cec2ae4b182ee36 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/47592 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R891ed7225b634dc01aaf3f13dbe79fc1eae1c27c
2012-03-22ARM: tegra: Fix build error when CONFIG_PM_SLEEP is not selectedScott Williams
Change-Id: I65e18395eef3a36f6dd537d64d98ab970f166460 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/47590 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2643d7665780442e71444999f21d96a508c7a062
2012-03-22ARM: tegra: workqueue: Unify spelling of 'freeze'+'able' to 'freezable'Gaurav Sarode
In K39 , 'freezeable' is changed to 'freezable'. Reference Commit Id 58a69cb47ec6991bf006a3e5d202e8571b0327a4. Change-Id: Ie3f95db453205c05da4cf4e655ba8b12a126255b Reviewed-on: http://git-master/r/47487 Tested-by: Gaurav Sarode <gsarode@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R530643b91e8c252eb606ce7e789cfe34101f6edd
2012-03-22arm: tegra: Use new platform typesYudong Tan
This change is needed to support three different platforms, silicon, fpga and simulation. Change-Id: I407853e1d86accbe3686deb4f34571fe6b10bcce Reviewed-on: http://git-master/r/36351 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc4b424f1a55ffb71245f3a8330559258124e2a19
2012-03-22arm: tegra: Add platform types for TegraYudong Tan
Change-Id: Ib9ef42efcbc24d1424a1b43e7d4ad46b97255aaa Reviewed-on: http://git-master/r/36350 Reviewed-by: Yudong Tan <ytan@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R99f25c1b92fe4a9322d83e00c9560fc7ada2b641
2012-03-22ARM: tegra: clock: Change default sampling period to 12msTom Cherry
Bug 845349 Original-Change-Id: I0ce1a5da9a80cea6a4e55bc92490e6ae8508e22f Reviewed-on: http://git-master/r/39704 Tested-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rfc2bfc89082778e43d15406b0b5e53bdf845f08e
2012-03-22ARM: tegra: power: Restore cpufreq governor targetAlex Frid
Restored cpufreq governor target frequency on exit from suspend. Otherwise, CPU would stay at frequency set underneath the governor by tegra driver on suspend entry. Original-Change-Id: Iad96c7771bf89b78cdeb3e8f4e2c40b36e845b57 Reviewed-on: http://git-master/r/38390 Reviewed-by: Alex Courbot <acourbot@nvidia.com> Tested-by: Alex Courbot <acourbot@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R12135cc7f8f940eac1653432786826bf2affec16
2012-03-22ARM: tegra: clock: Add/convert Tegra3 shared bus usersAlex Frid
- Convert display users of emc shared bus from shared floor users to shared bandwidth users - Add shared ceiling user to each supported shared bus (cbus, sbus, emc) Bug 837005 Original-Change-Id: I526d06a7ddd6072ec8ac750c4ffbfb7aa1890ec8 Reviewed-on: http://git-master/r/39140 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Raaca80423e60ee4c37e16c993641c2a5062bfd69
2012-03-22ARM: tegra: clock: Expand Tegra3 shared bus modesAlex Frid
Implemented 3 different modes of combining rate requests from shared bus users : - SHARED_FLOOR: cumulative floor request is determined by maximum rate among all users in this mode and minimum bus rate - SHARED_BW: cumulative bandwidth request is determined by adding rates of all users in this mode together - SHRED_CEILING: cumulative ceiling request is determined by minimum rate among all users in this mode and maximum bus rate Final shared bus rate is determined as minimum rate between cumulative ceiling request and maximum of floor or bandwidth cumulative requests. Up to now shared bus clocks supported only SHARED_FLOOR mode, and this mode is kept as default mode for all users. Hence, no change in actual shared bus operations. Bug 837005 Original-Change-Id: I29f8215ba7bab4998fdd23b74c4f96611f5848fe Reviewed-on: http://git-master/r/39139 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Re9f9f87d58419a6756b7985c59743356c6a634bc
2012-03-22ARM: tegra: dvfs: Set Tegra3 EMC max rate at 1.0V to 408MHzAlex Frid
Bug 836260 Original-Change-Id: I381619f6084a558f4c16142f8f0dfa3565ca2e94 Reviewed-on: http://git-master/r/39247 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Mandar Potdar <mpotdar@nvidia.com> Rebase-Id: R0d2d4bd478f526d116a741916de5c2fc2df7a998
2012-03-22ARM: tegra: mcstats: Enable overall bandwidth measurement.Heechul Yun
Allow users to measure overall bandwidth of the system. Original-Change-Id: I5bb19609451a464c0a2335f05033cd9c87927a40 Reviewed-on: http://git-master/r/37687 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R57b747cb81514336fdc45a3eeff17d6d00e154b1
2012-03-22arm: tegra: Add sysfs entries for SMMU debuggingHiro Sugawara
CONFIG_TEGRA_SMMU_SYSFS enables /sys/devices/smmu/* entries to update various SMMU register contents from user's land. Default is "n" to allow only displaying the current values but not updating except SMMU TLB/PTC statistics enabling and disabling bits. Original-Change-Id: Icb4574c08d89006cb09da1d8d60c7ab40fefd1b1 Reviewed-on: http://git-master/r/37118 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R647d1f9a59edbbc8a60b7393cb0572a927bd6d32
2012-03-22ARM: tegra: dvfs: Update Tegra3 cpufreq table selectionAlex Frid
- For selection of cpufreq scaling table used top-most rate in G CPU dvfs table, instead of G CPU max rate. Commonly the above rates are the same, however, in case when PMU limitations on core voltage indirectly (VDD_CPU on VDD_CORE dependency) lower cpu max rate, the top-most dvfs rate should be used for table selection, and the max rate clipped to table entry. - Replaced BUGs in table selection implementation with errors. Thus, when no table is found cpufreq is not installed, but the system boots with respective error messages. - Step up suspend frequency index in cpufreq tables to reduce suspend entry latency (the selected rate is still low enough to work under Vmin voltage setting). Original-Change-Id: I45db19dbf5b48cef80db35663db2df3b68473993 Reviewed-on: http://git-master/r/37415 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R59fb213db14d868bec0ca701e1c73dd9d1918e82
2012-03-22ARM: tegra: Fixed the wrong 'if' statement.Jubeom Kim
Removed the semicolon after 'if'. (cherry picked from commit 9a118fd001bfbe23a7b825aa66cb19ebe7c12c7c) Original-Change-Id: I058d58f6bad2ec08cf5a509361dbc3fc52801ce1 Reviewed-on: http://git-master/r/38228 Tested-by: Jubeom Kim <jubeomk@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Rebase-Id: R1221658aa101f439a88df3cdae8a2d8c9c659cfb
2012-03-22arm: tegra3: pinmux: Adding SFIO3 mode for VI_MCLKHarry Hong
SFIO3 on VI_MCLK pin is needed to output vi_sensor clk. bug 839517 Original-Change-Id: Ied7408a8711b0256b8fe98eea67c873a7b168bcb Reviewed-on: http://git-master/r/37426 Tested-by: Harry Hong <hhong@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com> Rebase-Id: Ra0c9550efc2ff7af8075eaf7962be94f2d299c2b
2012-03-22arm: tegra: clock: clock fix for lp0Luke Huang
Since clock is required when resetting devices, always enable pllc and plla at the beginning of clock restore routine. The actual value will be restored back after reset. Original-Change-Id: Ic141ddb8cde5958d4e0f8b1154b8204a68c0ca50 Reviewed-on: http://git-master/r/38388 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R254cf377d4cde1863f560867fafc10b4f37a87c9
2012-03-22ARM: tegra: clock: Add shared bus users rate printoutAlex Frid
Original-Change-Id: Icb1a5028d575155427f1fd7fa5b3ee2a145934f4 Reviewed-on: http://git-master/r/38421 Tested-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Gerrit_Virtual_Submit Reviewed-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Rebase-Id: Rf473061330e8b6d63948c9a0ed247e37e3534a52
generated by cgit v1.2.3 (git 2.0.4) at 2025-01-15 18:04:18 +0000