| Age | Commit message (Collapse) | Author |
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Remove Rigel's 200M working point to align with Arik
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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This patch sets PLL3_PFD_540M clock frequency to 540MHz
so that IPU and VPU clock can reach 270MHz.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it
can run at 270MHz on MX6DL/S. This is required for improving
VPU performance.
Change AXI_CLK to be sourced from periph_clk just before the DDR
freq is going to be dropped to 24MHz/50MHz. Change it back
to PLL3_PFD1_540 when the DDR freq is back at 400MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Since Logitech Quickcam E3500 is defaultly listed in usb_quirk_list on current
linux kernel. So the USB camera only supports reset resume, but doesn't support
normal usb suspend/resume. Actually, the USB camera works abnormally after USB
reset resume, but it works well after doing normal suspend/resume.
Signed-off-by: make shi <b15407@freescale.com>
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Vsync-pre irq is invalid for IPU overlay channel. The fb driver code
wrongly registers Vsync-pre for overlay channel with an un-initialized
irq number(0), which is conflict with CSI EOF irq number and causes
capture function broken. This patch avoids registering vsync-pre irq
for overlay channel.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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- invalid data preparation is a reasonable path, so no need to set to
WARNING level, change it to DEBUG level.
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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In suspend/resume and HDMI plugin/plugout stress test,
sometimes fbcon will call fb_set_par with
parameter fb_var_screeninfo that xres anfd yres is zero.
MX frame buffer driver can not correct handle this casue,
it will cause IPU pixel clock gating/ungating mismatch.
Check fb_var_screeninfo parameter in mxcfb_check_var and
mxcfb_set_par function, returned if xres,yres zero.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Test Env:
1. MX6DL SabreSD board.
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52MHz.
3. Test commands:
3.1 Writing command:
# dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
3.2 Reading command:
# echo 1 > /proc/sys/vm/drop_caches
# echo 1 > /proc/sys/vm/drop_caches
# sleep 1
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100
Performance result with this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~11MB/s (w) | ~5MB/s (w) | ~11MB/s (w) |
| | ~25MB/s (r) | ~25MB/s (r) | ~23MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~5MB/s (w) | ~9MB/s (w) |
| | ~16MB/s (r) | ~20MB/s (r) | ~13MB/s (r) |
-------------------------------------------------------
Performance result without this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~10MB/s (w) | ~5MB/s (w) | ~10MB/s (w) |
| | ~22MB/s (r) | ~23MB/s (r) | ~22MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~4MB/s (w) | ~8MB/s (w) |
| | ~13MB/s (r) | ~16MB/s (r) | ~11MB/s (r) |
-------------------------------------------------------
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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- set bounce buffer to 512KB from 64K, which is hw max seg size for
fsl sd host controller
- by enlarging the size of bounce buffer, it will reduce the number
of irq on writing by merging small requests into a large one, which
will improve writing throughput.
- the side effect is that the reading throughput of 512KB bounce buffer
is lower than the one of 64KB bounce buffer, when cpu freq is at 200Mhz.
Test Env:
1. MX6DL SabreSD board
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52Mhz
3. Test commands:
3.1 Writing test command:
# dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
3.2 Reading test command:
# echo 1 > /proc/sys/vm/drop_caches
# echo 1 > /proc/sys/vm/drop_caches
# sleep 1
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100
Performance result:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~10MB/s (w) | ~5MB/s (w) | ~10MB/s (w) |
| | ~22MB/s (r) | ~23MB/s (r) | ~22MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~4MB/s (w) | ~8MB/s (w) |
| | ~13MB/s (r) | ~16MB/s (r) | ~11MB/s (r) |
-------------------------------------------------------
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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Disable GPU IRQ trigger for CPU governor to save power
Current GPU trigger will let CPU work at 1G no matter any 3D draw
that make much power waste, to balance power and performance
we desire to disable GPU trigger for CPU governor, this change
will impact some benchmark performance but the drop is acceptable,
android will add performance mode, for any demo or customer who care
performance more than power please select performance mode.
Signed-off-by: Richard Liu <r66033@freescale.com>
Acked-by: Lily Zhang
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If we use the late_initcall(), then there is a time slot between
the exit of early uart console and the real console:
-->late_initcall(mxc_early_uart_console_disable)
......
-->imx_startup()
In this time slot, the clock will be closed, so the log printed during
the time slot is buffered, this is why we can not see the NFS's log.
Change the late_initcall() to late_initcall_sync() which eliminates the
time slot.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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1. BUS freq's set low bus setpoint using delat work, which
didn't have mutex lock, so in some scenarios, set high bus
freq function can be called at the same time, we need to move
mutex lock into these two routine;
2. Using pm notify to make sure bus freq set to high setpoint
before supend and restore after resume.
3. Clear build warning.
Signed-off-by: Anson Huang <b20788@freescale.com>
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1.Avoiding system wrong reboot caused by error temperature without
cancel_delayed_work before entering into suspend,so to cancel
thermal_zone_device temperature polling temperature delayed_work
before entering into suspend, reenable polling temperature delayed_work
after entering into resume.
2.In anatop_thermal_suspend, turn off alarm firstly
Signed-off-by: Rong Dian <b38775@freescale.com>
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Original design is VPU lib API StartOneFrame() enables clock, and VPU
driver disables clock after codec done interrupt has been received.
However there are known issues of interrupt handling as below:
- VPU interrupt handling callback is not scheduled in time causing work
queue overflow
- JPU done interrupt is not received because JPU issues it while JPU
buffer empty interrupt is still being served
- VPU finishes a frame (!vpu_IsBusy) but VPU done interrupt is not
received
All above will cause clk_disable in interrupt handling not called,
thus VPU clock count increases by 1.
So I plan to resolve clock unbalance issue first by removing
clk_disable from VPU driver interrupt handling. Interrupt problem
will not affect clock issue any longer.
1. Driver: remove clk_disable from vpu_worker_callback
2.1. Lib: remove clk_enable from API GetOutputInfo
2.2. Lib: avoid disabling VPU clock when VPU is busy in SWReset
3. Test: replace GetOutputInfo with SWReset in decoder_close /
encoder_close
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
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SOC/PU voltage need to following some rules according to latest
datasheet:
1. SOC/PU CAP voltage must be 1.15V <= SOC/PU <= 1.3V;
2. SOC and PU must be same as they don't have level shift;
3. Adjust previous wrong voltage setting.
If SOC/PU voltage is too low, may cause system crash on some
chips, we have a board that easily crash with GPU working and
doing some tar operation, with this voltage adjust, this issue
fixed.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Fix not able to set high bus frequency from low bus frequency.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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System will report oops as below. To fix it we will move mx6_timer_rate to
clock.c, so that we can avoid use clk_get_sys which cause schedule after
spin_lock.
oops log:
BUG: scheduling while atomic: kinteractiveup/1403/0x00000002
Modules linked in:
(unwind_backtrace+0x0/0xfc) from [<804f05f0>] (__schedule+0x4b8/0x6b0)
(__schedule+0x4b8/0x6b0) from [<804f12ac>] (__mutex_lock_slowpath+0x138/0x208)
(__mutex_lock_slowpath+0x138/0x208) from [<804f13b4>] (mutex_lock+0x38/0x3c)
mutex_lock+0x38/0x3c) from [<803b9134>] (clk_get_sys+0x1c/0xec)
(clk_get_sys+0x1c/0xec) from [<8005f814>] (mx6_timer_rate+0x14/0x7c)
(mx6_timer_rate+0x14/0x7c) from [<80056a20>] (_clk_gpt_get_rate+0x18/0x2c)
(_clk_gpt_get_rate+0x18/0x2c) from [<8005e89c>] (clk_get_rate+0x34/0x40)
(clk_get_rate+0x34/0x40) from [<80055f3c>] (_clk_pll_enable+0xa8/0x1ec)
(_clk_pll_enable+0xa8/0x1ec) from [<80056088>] (_clk_pll1_enable+0x8/0x20)
(_clk_pll1_enable+0x8/0x20) from [<80056998>] (_clk_arm_set_rate+0x278/0x2e8)
(_clk_arm_set_rate+0x278/0x2e8) from [<8005e824>] (clk_set_rate+0x54/0x68)
(clk_set_rate+0x54/0x68) from [<80061660>] (set_cpu_freq+0xb8/0x160)
(set_cpu_freq+0xb8/0x160) from [<800618b4>] (mxc_set_target+0xf0/0x20c)
(mxc_set_target+0xf0/0x20c) from [<80372388>](__cpufreq_driver_target+0x54/0x60)
Signed-off-by: Robin Gong <b38343@freescale.com>
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1.add new cpu setpoint: replace 498Mhz with 672Mhz,and remove 198Mhz.
but now 498Mhz seems not stable enough, comment now, test enough to
add it. Rigel kept unchange now.
2.support adjusting VDDSOC/VDDPU when cpu frequency change.
Signed-off-by: Robin Gong <b38343@freescale.com>
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This patch changes to use original sync mechanism for eof
irq, which may improve pan-display or alpha buffer update
performance.
1) Initialize flip_completion and alpha_flip_completion
only once when fb is initialized instead of initializing
it every time when pan display is called.
2) Clear and enable eof irq after selecting buffer ready.
In this way, we have no chance to lose an interrupt, as
selecting a new buffer ready doesn't make the eof irq
come(from the newly selected buffer) before we clear the irq
status and enable the irq. Otherwise, if we clear the irq
status and enable the irq before we doing down in pan-display
or alpha buffer update, we have chance(users call pan-display or
alpha buffer update faster than vsync frequency and blocks at
down()) to clear an unhandled irq, which may cause performance
issue.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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add vsync uevent report for user space.
add a IOCTL to enable/disable vsync uevent report to user space.
VSYNC uevent can let user space start draw just receive VSYNC irq,
and keep the draw within 16.7 ms that make the draw will show in
this frame, enhance the draw speed after receive input event.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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This patch sets CABC_EN0/1 to low to disable LVDS panel
CABC function so that LVDS backlight will not be turned
by the LVDS panel automatically so that we may avoid
annoying unstable backlight issue.
Signed-off-by: Rong Dian <b38775@freescale.com>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch configures NANDF_CS2/3 to be GPIO_6_15/16 to
support LVDS CABC_EN0/1.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Currently, we support 2 cameras, which are relevant to
2 video devices respectively. This patch checks if video
device is opened to determine whether we need to power
down/on relevant camera when doing suspend/resume.
Also, this patch protects capture resources with busy
lock semaphore.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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When android doing suspend/resume, we may meet the issue of
backlight is not on (pwm pin no signal) after system wakeup.
The root cause is PWM sample can not be set into the PWMSAR
register after pwm being used and disabled for a while.
The value read back after write is 0 when this issue happens.
Do a software reset after pwm disable can resolve this
issue, this makes sure the next sample update is correct.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Add a 1ms debounce to the gpio key to avoid
unexpected gpio status read from gpio_key driver's
workqueue. This issue happens on android's resume stage,
sometimes the framework get more than one up key even
user press the power key once.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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fix battery coulomb data for power down system ,define low battery
voltage for power down system is 3.42V
Signed-off-by: Rong Dian <b38775@freescale.com>
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All vpu memory requests go through GPU video allocator
Unify the reserved memory for GPU & VPU to ultize memory with max efficiency
Will use ION to implement GPU video memory managment later
Signed-off-by: Xianzhong <b07117@freescale.com>
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Add CPU governor trigger for GPU2D and GPUVG core, without these trigger
some benchmark show performance drop when enable CPU governor
Signed-off-by: Richard Liu <r66033@freescale.com>
Acked-by: Lily Zhang
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Add on-demand governor's threshold for FEC to improves performance.
i.mx6q TO1.1 tx throughput only is 64Mbps in 100Mbps mode on sabresd
platform, after the change, the throughput can reach to 95Mbps for tx.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit d24d1feb0d6243506696c7e5b3462b10f858d4e9)
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This reverts commit 6c65604f0fe6e60b50bb204fc05a0134f8ced60b.
Enable the busfreq by default
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Early versions of this driver used a set of entropy generation parameters
inherited from QorIQ devices. Those parameters were a hardcoded set
based upon internally-suggested values, and worked well on QorIQ. However,
for certain mx6 devices, oscillator values were found to be exceeding
the upper limit, and so RNG instantiation was failing in those cases.
This code improves initialization by (a) making sure the oscillator
divider is set to a known value, and (b) converting the parameter selection
to a symbolic compiler-generated form, instead of using embedded
magic number constants.
The calculation is now based on the definition of RNG4_ENT_CLOCKS_SAMPLE,
which defaults to 1600 unless overridden by something. The lower limit
is then set as /4, and the upper limit set to *8.
Tested-by: Minnick Michael-B21710 <b21710@freescale.com>
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
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DL TO1.1 has fixed the ipg glitch issue which will
cause DSM mode resume fail, so now we enable DSM mode
on DL.
Signed-off-by: Anson Huang <b20788@freescale.com>
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All bus freq related variables and function calls need to be protected by
mutex, or these variables may be wrong and result in triggering bus freq
change by mistake, it will impact many modules function.
Signed-off-by: Anson Huang <b20788@freescale.com>
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CPUs may be waked up by SMP broadcast, and for this scenario, CPUs
can enter idle again directly to avoid run a long way to re-enter
idle, adding this interrupt check can minish SMP impact on peripheral
devices' performance.
Signed-off-by: Anson Huang <b20788@freescale.com>
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fix Kconfig waring of defaults for choice values not supported
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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update default build config, build back ground overlay driver based
on ipu device driver instead of the former prp_view finder driver.
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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Kernel dump when do wifi stress test with suspend and resume as below:
eth0: tx queue full!.
remove wake up source irq 103
PM: resume of devices complete after 348.934 msecs
Restarting tasks ... done.
------------[ cut here ]------------
WARNING: at net/sched/sch_generic.c:255 dev_watchdog+0x284/0x2a8()
NETDEV WATCHDOG: eth0 (fec): transmit queue 0 timed out
Modules linked in: ar6000
[<8004482c>] (unwind_backtrace+0x0/0xf8) from
[<80068cd0>] (warn_slowpath_common+0x4c/0x64)
[<80068cd0>] (warn_slowpath_common+0x4c/0x64)from
[<80068d7c>] (warn_slowpath_fmt+0x30/0x40)
[<80068d7c>] (warn_slowpath_fmt+0x30/0x40) from
[<803f0c50>] (dev_watchdog+0x284/0x2a8)
[<803f0c50>] (dev_watchdog+0x284/0x2a8) from
[<80074430>] (run_timer_softirq+0xec/0x214)
[<80074430>] (run_timer_softirq+0xec/0x214) from
[<8006e524>] (__do_softirq+0xac/0x140)
[<8006e524>] (__do_softirq+0xac/0x140) from
[<8006ea60>] (irq_exit+0x94/0x9c)
[<8006ea60>] (irq_exit+0x94/0x9c) from
[<80039240>] (do_local_timer+0x54/0x70)
[<80039240>] (do_local_timer+0x54/0x70) from
[<8003ea0c>] (__irq_svc+0x4c/0xe8)
Exception stack(0x80a2bf68 to 0x80a2bfb0)
bf60: 0000001f 80a3babc 80a2bfb0 00000000 80a2a000 80a7b8e4
bf80: 804befcc 80a3ee7c 1000406a 412fc09a 00000000 00000000 80a81440 80a2bfb0
bfa0: 8003fa64 8003fa68 60000013 ffffffff
[<8003ea0c>] (__irq_svc+0x4c/0xe8) from [<8003fa68>] (default_idle+0x24/0x28)
[<8003fa68>] (default_idle+0x24/0x28) from [<8003fc60>] (cpu_idle+0xbc/0xfc)
[<8003fc60>] (cpu_idle+0xbc/0xfc) from [<80008878>] (start_kernel+0x258/0x29c)
[<80008878>] (start_kernel+0x258/0x29c) from [<10008040>] (0x10008040)
---[ end trace 30671ac42e272c2d ]---
But ethernet and system still be alive. In sometime,the issue
will cause system hang like "nfs: server 10.192.242.179 not
responding, still trying".
The root cause is tx buffer descriptors are not cleaned when
ethernet resume back.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Show video to IPU DP/fb0 when bootup, the color space incorrect
It needs to set the correct SRM_MODE when enable DP.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Revert ENGR00212529 MX6x show video to fb0 when bootup,
the color space incorrect.
Update IPU DP CSC setting should not change the DP FG window's position setting,
it can be update when enabling IPU DP channel.
Otherwise, it will appear NFB4EOF_ERR and flip irq timeout errors.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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the original low memory killer only take care of system memory accounting,
but for so large shared memory occupy by GPU, and each process memory
killer account become unfair, very large 3D game will not killed firstly
if it going to background.
Add this account to let real large memory user get killed if going to background
eg, the "angry bird Space" will acquire 68,215,360 GPU memory for 1-6 toll-gate.
The test show it can quicker recovery from memory shortage situation,
since it's very like to be killed after add so much GPU memory for such 3D game.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
Acked-by: Lily Zhang
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Add ipu device queue processing for overlay, and make it default.
This will instead prp_viewfinder work flow in the most user case.
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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Replace CSI_PRP_VF_MEM channel with CSI_MEM, then using ipu device
to do the processing or directly send to framebuffer if no processing
need to be perform.
Add the foreground overlay driver file name ipu_fg_overlay_sdc.c correspondding
to the former ipu_prp_vf_sdc.c
Discard the cam->vf_rotation parametter when uing the ipu device for processing
in the overlay, share the cam->rotation parametter with pp.
Signed-off-by: Yuxi sun <b36102@freescale.com>
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If using mxcfb1 for HDMI display, it will print
'PHY PLL not locked'.
Fixed it with setting HDMI default to blank state.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Replace mx6q_version() check with hdmi_SDMA_check() to add support
for HDMI_SDMA in RIGEL TO1.1.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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Replace mx6q_version() check with hdmi_SDMA_check() to add support
for HDMI_SDMA in RIGEL TO1.1.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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Replace mx6q_version() check with hdmi_SDMA_check() to add support for
HDMI_SDMA in RIGEL TO1.1.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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In RIGEL TO1.1, the same HDMI_SDMA fix is introduced as ARIK TO1.2. Add
support for RIGEL TO1.1 for HDMI_SDMA functionality.
In this patch:
1.Add hdmi_SDMA_check() interface to judge whether MX6 chip
support HDMI_SDMA.
2.Replace mx6q_version() check with hdmi_SDMA_check() to support
both ARIK To1.2 and RIGEL TO1.1.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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the original low memory killer only take care of system memory accounting,
but for so large shared memory occupy by GPU, and each process memory
killer account become unfair, very large 3D game will not killed firstly
if it going to background.
Add this account to let real large memory user get killed if going to background
eg, the "angry bird Space" will acquire 68,215,360 GPU memory for 1-6 toll-gate.
The test show it can quicker recovery from memory shortage situation,
since it's very like to be killed after add so much GPU memory for such 3D game.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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