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This patch avoids TVE framebuffer cause black flash issue or potential
black flash issue on one other framebuffer device which connects with
the same di when the system boots up or video mode is changed.
Signed-off-by: Liu Ying <b17645@freescale.com>
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mx23/mx28 otg port host mode will not enable internal
phy clock (portsc1 PHCD1), in that case, if the user loads
the gadget firstly, then, unloads the gadget module.
The host will not work due to gadget disable internal
phy clock after its unload process, but host doesn't enable it
at its initialization.
This fix will add enable internal phy clock at otg initialization process,
and disable it at de-initialization process.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Add support for MX508 to enter STOP mode. The DDR needs to put into
self-refresh manually, hence suspend code needs to run from OCRAM.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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memstore should be freed properly. a following change will be prepared to
improve the alloc/free logic for device memstore.
Signed-off-by: Jie Zhou <b30303@freescale.com>
Acked-by: Rob Herring <r.herring@freescale.com>
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A better way to check for devices that support USB remote
wakeup. If the device supports remote wakeup, then the
wake_up_enable function is defined in usb_xx.c, check on that
definition, rather than a cpu_is_xx() call.
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
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User can get eMMC partitions info from user space layer in
linux OS enviroment.
User can do switch operations between the eMMC boot partitions
and the user partition.
User can access the eMMC boot partitions from user space layer
in linux OS enviroment.
NOTE:This func had been verified on TOSHIBA eMMC44 card only.
Signed-off-by: Richard Zhu <r65037@freescale.com>
Signed-off-by: Rob Herring <r.herring@freescale.com>
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Add apll and pfd support.
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
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Move pswitch-pressed time checking routine into a delayed work for
mx28 EVK pswitch power-down and suspend function
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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Adjust the Target dll value to support the TOSHIBA eMMC44 card.
Make sure that IPG, HLK, PER are enabled, and SDCLK is disabled.
SDCLKFS can't be set to zero on esdhc V3 IP.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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The current model does not allow to put a pad into different modes
once a pins is allocated. Remove the resource handling.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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also, check for a valid pad_ctrl_ofs before changing the
pad control register.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The old defines leaked in from an old version of the patch.
Change the defines to match the register layout of the iomuxer.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The ENET IEEE1588 Timer have a correction counter, and it can
slow down or speed up the timer.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
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Add UART2 for mx23 EVK board. EVK board needs rework.
Add console support for application uart according to customer requirement
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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Add UART2 for mx23 EVK board. EVK board needs rework.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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Fix the following problem at compile-time.
WARNING: vmlinux.o(.data+0x2b8b4): Section mismatch in reference from
the variable pxp_device to the (unknown reference) .devinit.text:(unknown)
The variable pxp_device references
the (unknown reference) __devinit (unknown)
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*driver, *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
Signed-off-by: Robby Cai <R63905@freescale.com>
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Fix the following problem at compile-time.
WARNING: arch/arm/mach-mx5/built-in.o(.data+0xd354): Section mismatch in
reference from the variable max17135_pdata to the (unknown reference)
.init.data:(unknown)
The variable max17135_pdata references
the (unknown reference) __initdata (unknown)
Signed-off-by: Robby Cai <R63905@freescale.com>
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Use the platform_device_unregister instead of platform_device_put,
to remove the device from the audio subsystem, when it fails to reigster
the cs42888 card.
Signed-off-by: William Lai<b04597@freescale.com>
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If set both double buffer ready for VDI case, there will come out
NFB4EOF error.
Signed-off-by: Jason Chen <b02280@freescale.com>
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Change pgprot_noncached to pgprot_writecombine in gsl_kmod_mmap to
improve performance
Signed-off-by: Thomas Peng <r80085@freescale.com>
Signed-off-by: Jie Zhou <b30303@freescale.com>
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Judge the codec memeber of the snd_soc_card_imx_3stack after the
platform_device_add function, as only after this function, the
cs42888_codec pointer will be passed to.
Signed-off-by: William Lai <b04597@freescale.com>
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There would be a small silent stop in the audio playback
when insert the cards into the slot during the audio playback.
The root cause is the mis-spell delay that would be 10 times larger
than expection. Change the delay back to original expection.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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With latest VG/GL fix integration from RC16/EA, there will be some problems
as below, which can be solved by this patch:
- ENGR00124884 will happen again
- suspend/resume will not be supported in gpu driver
Signed-off-by: Jie Zhou <b30303@freescale.com>
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Clk tree make default di1_clk's parent clk as pll3 when tve clk disable,
ipu disp module will re-calculate ipu pixel clk if di clk's parent clk
is not tve_clk. If blanks tve-fb0, di1 clk's parent will set to pll3,
unblank tve-fb0 need re-calculate tve clk.
Signed-off-by: Jason Chen <b02280@freescale.com>
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If do input right-side crop and input/output are in the same size, v4l2
driver will enable ic_bypass, but after enable it, the output is not
correct.
Signed-off-by: Jason Chen <b02280@freescale.com>
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change the unlock position in ipu_disable_channel.
Signed-off-by: Jason Chen <b02280@freescale.com>
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It should avoid the NFB4EOF error.
Signed-off-by: Jason Chen <b02280@freescale.com>
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Fix the VG/GL issue in GPU kernel module when running VG/GL at the same time
Signed-off-by: Gene Chouiniere <Gene.Chouiniere@amd.com>
Signed-off-by: r80085 <thomas.peng@freescale.com>
Acked-by: Rob Herring <r.herring@freescale.com>
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Random artifacts were caused by corruption of the EPDC working
buffer. This occurred because the working buffer was being
allocated too small. This meant other accesses to FB-maintained
buffers was corrupting the working buffer and causing random
data to be drawn to the display. Fixing the working buffer size
causes the artifacts to disappear.
Signed-off-by: Danny Nold <dannynold@freescale.com>
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The CS42888 can only playback or record the multiple 44k streams,
as there is only the 22.579MHz Osc on the board. Enable the
ALSA plugin or ASRC when try to playback or record multiple 48k
streams.
Signed-off-by: William Lai <b04597@freescale.com>
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Avoid of registering the audio sub-system when the codec does
not exist.
Signed-off-by: William Lai <b04597@freescale.com>
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one wire master driver is coming from upstream.
clock name is owire, not owire_clk
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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Add "w1" setup at mx50 pin defination because 1wire pin used
for usb over current default.
Fix multi w1_setup problem at many i.MX platform. Only first one
is run by main.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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1. At reset_irq, the status of port reset is unsure, maybe the reset
process(hardware does it) is finished, and the status of port reset
is also cleared by usb controller. So it only needs to compare to USBSTS
at usb irq process.
2. Due to mx35/mx25 phy's bug, it needs to reset phy when re-open
usb clock next time(Begin to use usb next time)
3. mdelay 100 seconds is too long for resume process, as this code
is only added for mx37, add arch macro for this mdelay. This can
minimize the effect for other platforms.
4. Compile is ok for all imx platform, functional tests are finished
for mx35 and mx23.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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The platform related codes' modifications
when enable the eMMC44 DDR mode on MX53 EVK board
Signed-off-by: Richard Zhu <r65037@freescale.com>
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The driver related codes' modifications
when enable the eMMC44 DDR mode on MX53 EVK board
Signed-off-by: Richard Zhu <r65037@freescale.com>
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The modifications of linux kernel common codes
when enable the eMMC44 DDR mode
Signed-off-by: Richard Zhu <r65037@freescale.com>
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The clock prescaler can not be 0 for esdhc v3 in MX50.
(The smallest value should be 1).
Change the clock setting part to cover this special case.
Signed-off-by: Aisheng.Dong <b29396@freescale.com>
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Add IOMUX and configuration data for esdhc3
Signed-off-by: Aisheng.Dong <b29396@freescale.com>
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1) Support ELCDIF framebuffer driver.
2) Change CLAA WVGA LCD driver to make it co-work with ELCDIF driver.
Signed-off-by: Liu Ying <b17645@freescale.com>
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Set pixel clock rate for CLAA-WVGA LCD panel for 27MHz and
set the display frequency to be 57Hz. This makes the panel
to get rid of water wave glitch issue on MX50 platform.
Signed-off-by: Liu Ying <b17645@freescale.com>
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1) Enable keepers for LCDIF pads.
2) Remove input path selection for LCDIF pads.
Signed-off-by: Liu Ying <b17645@freescale.com>
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1. adjust lp_clk, ddr_clk MX53 and MX51 uses different one
2. adjust cpu rate in cpu_wp_table
3. enable clock divider handshaking when ddr clock changing
4. add AHB_MED_SET_POINT to ldb_di_clk
5. adjust the bit define about CCDR register
Signed-off-by: Shen Yong <b00984@freescale.com>
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Build as module by default.
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
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Build as module by default.
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
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Migrate from RC14 with freescale changes.
Signed-off-by: Gene Chouiniere <Gene.Chouiniere@amd.com>
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Acked-by: Rob Herring <r.herring@freescale.com>
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The stat check wait will add ipu operation time which degrade the ipu
performance.
Signed-off-by: Jason Chen <b02280@freescale.com>
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During DP swap, other fb operation should not happen.
Signed-off-by: Jason Chen <b02280@freescale.com>
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The memory mmap by ipu device is write-back, so user space need sync
method.
Signed-off-by: Jason Chen <b02280@freescale.com>
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1. Adjust VDDGP for 1GHZ as 1.15v
2. Adjust VDDGP for 800MHZ as 1.05v
3. Not all current MX53 boards can run up to 1GHZ. So one limitation is
added into clock.c to limit 1GHZ working point. To enable 1GHZ
working point in kernel, please increase the GP voltage and type the
command "clk core 1000" in uboot console to switch CPU core to 1GHZ.
This limitation will be removed after all boards support 1GHZ.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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