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i.MX8qxp uses two LDB(one primary, one auxiliary) to support dual
channel mode. This patch adds DT property descriptions for those
properties needed by this case.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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Add the device-tree bindings for the display node eLCDIF
on i.MX platforms.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
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This patch adds DPR support for fetchdecode in the DPU base driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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The Display Prefetch Resolve(DPR) is a processor of fetching display data
before the display pipeline which needs data to drive pixels in the active
display region. The data is transformed, or resolved from a variety of
tiled buffer formats into linear format. The DPR transaction sequences are
issued with a high level of DRAM efficiency. This patch adds the base
driver support for i.MX8qm/qxp DPR.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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The Pretch Resolve Gasket(PRG) is a digital core function as a gasket
interface between RTRAM controller and DPU. The main function of PRG
is to convert the AXI interface to RTRAM interface and remapping the
ARADDR to a RTRAM address. This patch adds the base driver support
for i.MX8qm/qxp PRG.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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To allow the PLL to become stable before enabling the clocks, we may
need a delay. This patch adds a new property to specify this delay from
DTS file.
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
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Add a new dt property to the nwl_dsi-imx driver: sync-pol.
This property represents the sync polarity of the input signal to it's
internal DPI-to-DSI block.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Currently, the Northwest Logic MIPI-DSI controller host specific code
resides under drm/bridge, but is not a real drm_bridge. It creates a
drm_bridge and adds itself to the drm_encoder that handles this file,
but this is wrong, since it does not implement the drm_bridge_funcs.
The correct way to implement a drm_bridge is to add the drm_bridge and
let other components (another bridge or a drm_encoder) to attach to this
bridge.
Since we are doing this, a new compatible strings can be used for this
driver: "nwl,mipi-dsi".
Since this was used by nwl_dsi-imx.c, update that driver to use this
bridge correctly.
This is needed in order to add support for MIPI-DSI on 8MQ. The IMX_NWL
driver will either add a DSI encoder to DRM, or a DSI bridge.
The encoder will be used by imx-drm-core driver, while the bridge
will be used by MXSFB driver (which creates a simple display pipe).
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
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Add support for the NorthWest Logic MIPI-DSI controller found
in the following i.MX8 platforms: i.MX8qm, i.MX8qxp and i.MX8mq.
This is the MIPI-DSI encoder containing the platform specific changes
and it uses the NWL MIPI-DSI bridge.
Currently only qm and qxp are tested with this driver. The mq support
will be added later.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
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This patch adds base suport for i.MX8M's Display Controller
subsystem(DCSS). It has built-in DPR, Scaler and HDR10 modules. Also, it
features a video Decompression and Tile to Raster Conversion (DTRC) unit,
as well as a graphics pixel decompression infrastracture (DEC400D).
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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This patch adds i.MX8qxp LDB support.
Logics are added to make i.MX8qxp LDB cope with Mixel LVDS combo PHY.
Also, logics are added to handle pixel link quirks for i.MX8qxp LDB.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds i.MX8qm LDB support.
Logics are added to make i.MX8qm LDB cope with Mixel LVDS PHY.
Also, logics are added to handle pixel link padding quirks for i.MX8qm LDB.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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DPU is the display processing unit embedded in i.MX8qm and i.MX8qxp.
It was originally designed by Fujitsu.
The first revision has capture controller, display controller and blit engine.
The second revision is a lite one and has display controller and blit engine.
This patch adds a base driver for DPU, which provides a thin register wrapper,
interrurpt support and client platform device register for the upper layer to
use. Currently, the driver only supports the display controller at the pixel
processing level and only the fetchdecodes are supported/tested as the fetch
units.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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Document the ddc-i2c-bus property used by imx-ldb driver to read EDID
information via I2C interface.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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This is a quite large renaming to consolidate display related bindings
into a single "display" directory from various scattered locations of
video, drm, gpu, fb, mipi, and panel. The prior location was somewhat
based on the Linux driver location, but bindings should be independent
of that.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
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