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This is the 5.4.193 stable release
Conflicts:
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
drivers/edac/synopsys_edac.c
drivers/mmc/host/sdhci-esdhc-imx.c
drivers/mmc/host/sdhci.c
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
sound/soc/codecs/msm8916-wcd-analog.c
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commit 640f35b871d29cd685ce0ea0762636381beeb98a upstream.
This property was already mentioned in the old textual bindings
amlogic,meson-vpu.txt, but got dropped during conversion.
Adding it back similar to amlogic,gx-vdec.yaml.
Fixes: 6b9ebf1e0e67 ("dt-bindings: display: amlogic, meson-vpu: convert to yaml")
Signed-off-by: Alexander Stein <alexander.stein@mailbox.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211219094155.177206-1-alexander.stein@mailbox.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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commit 22bf4047d26980807611b7e2030803db375afd87 upstream.
This is used in meson-gx and meson-g12. Add the property to the binding.
This fixes the dtschema warning:
hdmi-tx@c883a000: 'sound-name-prefix' does not match any of the
regexes: 'pinctrl-[0-9]+'
Signed-off-by: Alexander Stein <alexander.stein@mailbox.org>
Fixes: 376bf52deef5 ("dt-bindings: display: amlogic, meson-dw-hdmi: convert to yaml")
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211223122434.39378-2-alexander.stein@mailbox.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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The driver got converted to a I2C device, DDC/EDID and HPD handling is added.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 35be57f246f14c96cbd0889d8bd49f233cd6e731)
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The Lontium LT8912 MIPI-DSI to LVDS and HDMI/MHL bridge features a
single-channel MIPI D-PHY receiver front-end configuration with 4 data
lanes per channel operating at 1.5Gbps per data lane and a maximum
input bandwidth of 6Gbps.
Change-Id: I7733ea5f33094151bb62e62406561cc0025cf900
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Import and forward port to 4.9 (API change of_get_drm_display_mode() )
from https://github.com/rockchip-linux/kernel/commit/230f7f061036a99fc02d2cd7d20f66f7f0efae99
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
drop drm_atomic_helper_connector_dpms, see 7d902c05b drm: Nuke drm_atomic_helper_connector_dpms
(cherry picked from commit 265fac62bf9defe0de5c1ce088013b61c9b46fb7)
(cherry picked from commit 7d2bdcf5aa35191aa0810884ea8eef944059269c)
(cherry picked from commit 35243d334a8610385cc3f830f90ab18fd7e7edc5)
Conflicts:
Documentation/devicetree/bindings/vendor-prefixes.txt
drivers/gpu/drm/bridge/Kconfig
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* tag 'v5.4.70': (3051 commits)
Linux 5.4.70
netfilter: ctnetlink: add a range check for l3/l4 protonum
ep_create_wakeup_source(): dentry name can change under you...
...
Conflicts:
arch/arm/mach-imx/pm-imx6.c
arch/arm64/boot/dts/freescale/imx8mm-evk.dts
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
drivers/crypto/caam/caamalg.c
drivers/gpu/drm/imx/dw_hdmi-imx.c
drivers/gpu/drm/imx/imx-ldb.c
drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c
drivers/mmc/host/sdhci-esdhc-imx.c
drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
drivers/net/ethernet/freescale/enetc/enetc.c
drivers/net/ethernet/freescale/enetc/enetc_pf.c
drivers/thermal/imx_thermal.c
drivers/usb/cdns3/ep0.c
drivers/xen/swiotlb-xen.c
sound/soc/fsl/fsl_esai.c
sound/soc/fsl/fsl_sai.c
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
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Add a new compatible string "raydium,rm67199" for the new version of
this panel, similar with rm67191 which is also supported by the same
driver.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Add dt-bindings documentation for WKS 101wx001 paralel LCD panel.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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[ Upstream commit b0ff9b590733079f7f9453e5976a9dd2630949e3 ]
Add property "pinctrl-names" to swap pin mode between gpio and dpi mode.
Set the dpi pins to gpio mode and output-low to avoid leakage current
when dpi disabled.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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This is an adapter card made for the 4.3", 800x480, LCD panel Seiko
43WVFIG. The LCD panel is a 24bit DPI bus, while the adapter card has
two ports: 18-bit and 24-bit data input. For the 18-bit data input, the
adapter card is demuxing some of the data lines, in order to feed all of
the 24 lines needed by the LCD.
This driver handles both this use-cases.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
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DPU found in i.MX8qxp SoC may drive a parallel display through
pixel link to LCDIF mux. This patch adds the device tree binding
documentation for LCDIF mux display.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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Add documentation for a new clock 'phy_parent'. This clock is optional
and is used to re-parent the PHY related clocks (phy_ref, tx_esc and
rx_esc) to a valid parent. This clock is needed, in order to make the
re-parenting in driver, since the default re-parenting in dts node
(using assigned-clock-parents) may break the LVDS block, which has it's
PHY shared with MIPI-DSI.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
(cherry picked from commit 7ed3b8738e3103396a5f3a9268c66f11f78cab03)
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Add devicetree bindings for i.MX8mp LDB controller.
The controller supports two four data lane LVDS channels and supports
single/dual channel mode. The controller connects with LCDIFv3 on
i.MX8mp SoC.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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* origin/display/panel:
drm/panel: rm67191: Add dev_err for reset gpio
drm/panel: simple: Add support for JDI TX26D202VM0BWA panel
dt-bindings: display: Add JDI TX26D202VM0BWA LCD panel bindings
drm/panel: rm67191: Remove CLOCK_NON_CONTINUOUS flag
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* origin/display/nwl-dsi: (14 commits)
drm/bridge: nwl-dsi Correct the DSI init sequence
drm/bridge: nwl-dsi: Fix find_panel_or_bridge
drm/bridge: nwl-dsi: Add support for 8QM and 8QXP
drm/bridge: nwl-dsi: Add support for component framework
phy: imx8-mipi-dphy: Add support for 8QM and 8QXP
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* origin/display/mxsfb: (14 commits)
drm/mxsfb: Add support for live pixel format change
drm/mxsfb: Add support for horizontal stride
drm/mxsfb: Clear OUTSTANDING_REQS bits
drm/mxsfb: Improve the axi clock usage
drm/mxsfb: Update mxsfb to support LCD reset
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* origin/display/mali:
drm/arm/mali-dp: Add display QoS interface configuration for Mali DP500
dt/bindings: display: Add optional property node define for Mali DP500
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* origin/display/ldb: (11 commits)
drm/imx: ldb: Add dual channel mode support for i.MX8QXP
dt-bindings: display: imx: ldb: Add i.MX8qxp LDB dual channel mode documentation
dt-bindings: display: imx: ldb: Correct pixel and bypass clock description
drm/imx: ldb: Add system power management support
MLK-21876-23 drm/imx: ldb: fix incorrect color displayed for mx8qxp
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* origin/display/dpu: (73 commits)
gpu: imx: framegen: Use crtc_clock instead of mode clock
gpu: imx: dpu: common: Initialize SCU misc settings in dpu_resume()
LF-73 gpu: imx: dpu: sc misc: Initialze KACHUNK_CNT as needed by blit engine
gpu: imx: dpu: sc misc: Rename dpu_pxlink_init() to dpu_sc_misc_init()
gpu: imx: dpu: sc misc: Rename dpu_sc_misc_init() to dpu_sc_misc_get_handle()
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* origin/display/dcss: (25 commits)
drm/imx/dcss: Release DTRC IRQs in case of failure
drm/imx/dcss: fix crash in DTRC exit routine
dt-bindings: display: imx8mq-dcss: add bindings for DTRC interrupts
drm/imx/dcss: add support for tiled formats on overlay planes
drm/imx/dcss: change HDR10 pipes config handling
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Add optional property node 'arm,malidp-arqos-value' for the Mali DP500.
This property describe the ARQoS levels of DP500's QoS signaling.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
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The DTRC module triggers an interrupt when each bank finished processing. So,
they are needed if video compressed formats are to be played.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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This adds dt bindings for pll_src and pll_phy_ref, used when output is on HDMI.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Add bindings for iMX8MQ Display Controller Subsystem.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Add documentation for a new property: 'fsl,clock-drop-level'.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
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Add documentation for a new clock 'video_pll'.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
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The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
Signed-off-by: Guido Günther <agx@sigxcpu.org>
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The JDI TX26D202VM0BWA LCD panel is a 10.1" panel
with a 1920x1200 (WUXGA) resolution.
The panel has dual LVDS channels.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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The DSI-HDMI converter, ADV7535, driver uses four i2c memory maps: MAIN,
DSI-CEC, EDID and PACKET.
While the MAIN address is hard-coded in the ROM chip, the other three
can be programmed into the MAIN memory map.
Currently, the three memory maps addresses, that can be programmed, are
hard-coded into the code.
In order to avoid conflicts with other i2c clients on the bus, update
the driver to use configurable addresses specified in DTS file.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
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Add a new property "adi,dsi-channel" to allow the user specify the DSI
channel to be used when communicating with DSI peripheral.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Added "adi,adv7535" to the adv7511 drm bridge and adi,adv7511.txt doc,
since the driver can also support the ADV7535 chipset (upgrade of ADV7533).
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
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Add a new property 'pref-rate' support which can be used to
assign a different clock frequency for the DPHY PLL reference
clock in the dtb file. And if this property does not exist,
the default clock frequency for the reference clock will be
used. And according to the spec, the DPHY PLL reference clk
frequency should be in [6MHz, 300MHz] range.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
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Add the device-tree bindings for the display bridge
Samsung MIPI DSIM on i.MX platforms.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
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This patch adds device tree binding for ITE IT6263 LVDS to HDMI transmitter.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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Add new optional property 'max-memory-bandwidth', to limit the maximum
bandwidth used by the MXSFB_DRM driver.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Rob Herring <robh@kernel.org>
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i.MX8qxp LDB dual channel mode uses two LDB channels from two LDB
instances, while all other LDB variants in other SoCs use two LDB
channels from one LDB instance. This patch adds documentation
for the special case of i.MX8qxp LDB dual channel mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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Not only i.MX8qm LDB requires pixel and bypass clocks, but also
i.MX8qxp LDB does. This patch corrects pixel and bypass clock
description by explicitly saying that i.MX8qxp LDB requires
the clocks.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds device tree binding support for i.MXqxp LDB,
including compatible string and additional properties.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds device tree binding support for i.MXqm LDB,
including compatible string and additional properties.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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Pixel combiner found in i.MX8 SoCs may combine two display
streams(one master and the other slave) to drive a high
pixel rate display. This patch adds DT property descriptions
in imx-drm device tree documentation for pixel combiner.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds DPR channel property to dpu binding doc.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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support
The Display Prefetch Resolve(DPR) is a processor of fetching display data
before the display pipeline which needs data to drive pixels in the active
display region. The data is transformed, or resolved from a variety of
tiled buffer formats into linear format. The DPR transaction sequences are
issued with a high level of DRAM efficiency. This patch adds device tree
binding doc support for i.MX8qm/qxp DPR.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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support
The Pretch Resolve Gasket(PRG) is a digital core function as a gasket
interface between RTRAM controller and DPU. The main function of PRG
is to convert the AXI interface to RTRAM interface and remapping the
ARADDR to a RTRAM address. This patch adds device tree binding doc
support for i.MX8qm/qxp PRG.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds device tree binding for the Display Processing Unit(DPU),
as found in i.MX8qxp SoC.
The DPU is comprised of two main components that include a blit engine
for 2D graphics accelertations and a display controller for display
output processing, as well as a command sequencer.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch update describe panel/port links, including
unit addresses in documentation of device tree bindings
for the rockchip DSI controller based on the Synopsys
DesignWare MIPI DSI host controller.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
[this seems to have gotten lost when the original dsi-series was applied]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20181001123845.11818-5-heiko@sntech.de
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The NEC NL8048HL11 is a 10.4cm WVGA (800x480) panel with a 24-bit RGB
parallel data interface and an SPI control interface.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190813201101.30980-4-laurent.pinchart@ideasonboard.com
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Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic Display Controller over to YAML schemas.
The original example has a leftover "dmc" memory cell, that has been
removed in the yaml rewrite.
The port connection table has been dropped in favor of a description
of each port.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190808085522.21950-3-narmstrong@baylibre.com
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Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic Synopsys DW-HDMI specifics over to YAML schemas.
The original example and usage of clock-names uses a reversed "isfr"
and "iahb" clock-names, the rewritten YAML bindings uses the reversed
instead of fixing the device trees order.
The #sound-dai-cells optional property has been added to match this node
as a sound dai.
The port connection table has been dropped in favor of a description
of each port.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190808085522.21950-2-narmstrong@baylibre.com
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Some Allwinner SoC using boards (Orange Pi 3 for example) need to enable
on-board voltage shifting logic for the DDC bus using a gpio to be able
to access DDC bus. Use ddc-en-gpios property on the hdmi-connector to
model this.
Add binding documentation for optional ddc-en-gpios property.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190806155744.10263-3-megous@megous.com
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