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QORIQ LS1028A soc used fsl,vf610-edma, but it has a little bit different
from others, so add new compatible to distinguish them.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Link: https://lore.kernel.org/r/20191212033714.4090-3-peng.ma@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit f8dd1f395d1fbba049900ed48c09d76df49be712)
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* origin/dma/sdma: (23 commits)
LF-301: dmaengine: imx-sdma: Add once more loading firmware
LF-246: dmaengine: imx-sdma: correct is_ram_script checking
MLK-23005: dmaengine: imx-sdma: correct data size of channel context
MLK-22972 dmaengine: imx-sdma: correct the script number for v3
dma: imx-sdma: Add pm_ops to support suspend & resume
...
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Add power domains for each dma channel so that edma channel could
know the power state of every dma channel anytime and clear easily
unexpected interrupt which triggered before the last partition reset.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: S.j. Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 0b6da46b7bdb2284e24757d48466268b9feb5b7c)
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Since the imx8qm/qxp hsio only supports up to 32bit
dma capability.
Add the 32bit dma limitation into dma binding document.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
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Since there are multi edmav3 instances on i.mx8, every edma channel name
is better unique.But so far, all edma channel name is 'edma-channel(id)-
tx',thus some edma channels which share the same channel id but different
edma instance will show the same channel name in kernel and this is not
friendly to debug in kernel.
Now the edma channel name(interrupt-names property) is define in dts
as below:
"edmaX-chanX-Xx"
| | |---> receive/transmit, r or t
| |---> channel id, the max number is 32
|---> edma controller instance, 0, 1, 2,..etc
and get below correct name with 'cat /proc/interrupts':
43: 0 0 0 0 GICv3 466 Level edma0-chan8-rx
44: 0 0 0 0 GICv3 467 Level edma0-chan9-tx
45: 79 0 0 0 GICv3 468 Level edma0-chan10-rx
46: 311 0 0 0 GICv3 469 Level edma0-chan11-tx
47: 0 0 0 0 GICv3 470 Level edma0-chan12-rx
48: 0 0 0 0 GICv3 471 Level edma0-chan13-tx
49: 0 0 0 0 GICv3 472 Level edma0-chan14-rx
50: 0 0 0 0 GICv3 473 Level edma0-chan15-tx
51: 0 0 0 0 GICv3 406 Level edma2-chan0-tx
52: 0 0 0 0 GICv3 407 Level edma2-chan1-tx
53: 0 0 0 0 GICv3 408 Level edma2-chan2-tx
54: 0 0 0 0 GICv3 409 Level edma2-chan3-tx
55: 0 0 0 0 GICv3 410 Level edma2-chan4-tx
56: 0 0 0 0 GICv3 411 Level edma2-chan5-tx
57: 0 0 0 0 GICv3 442 Level edma2-chan6-rx, edma2-chan7-tx
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit af8e197a92c9c024ec4fbfcf543d744e81748773)
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There is Audio dual fifo cause that fill fifo one by one and
loop back after every minor loop:
-- fill the first 32bit width fifo
-- fill the next 32bit width fifo
-- +MLOFF signed offset after the above two FIFOs filled
-- loop back to the first step to handle the next minor loop.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit 5aa5e9663bb3a834444b75ea086bef8c37ecb636)
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For dual fifo case, fsl-edma-v3 need add another cell. It's not friendly
for user and it's possible other cells maybe added to other use cases,
so combine two cells into one now, and for some special use cases such as
dual fifo property can directly be passed by one bit of cell3 rather than
another cell.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit 3ecd1b3382e2c746728842fb2c084fbb030eb5de)
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update fsl_edma_v3 document for #dma-cell is changed
one more cell is added, which is for local/remote access.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 65543fb7fefbdb7df4cb60931a88f61507c5073f)
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Add edma-v3 driver on i.mx8qm.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit d0ac0971c2e637ebddc853f12f71d130f5df4f91)
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update sdma script for multi fifo SAI on i.mx8MQ. Besides,Add
new cell for sw_done/sw_done_selector, because PDM need enable
software done feature in sdma script(same multi fifo script).
The new fourth cell defined as below:
Bit31: sw_done
Bit15~bit0: selector
For example: 0x80000000 means sw_done enabled for done0 sector which
is for PDM on i.mx8mm.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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Add hdmi audio support.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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Add i.mx6ul and i.mx6sx compatible name.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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The commit b37e3534ac42 ("dt-bindings: dmaengine: Add YAML schemas
for the generic DMA bindings") changed the property from
dma-channel-mask to dma-channel-masks. So, this patch fixes it.
Fixes: b37e3534ac42 ("dt-bindings: dmaengine: Add YAML schemas for the generic DMA bindings")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1566988223-14657-1-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Rename the device tree bindings for renesas "Type-AXI" NBPFAXI* DMA
controllers from nbpfaxi.txt to renesas,nbpfaxi.txt.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link: https://lore.kernel.org/r/20190819135244.18183-1-horms+renesas@verge.net.au
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Rename the bindings documentation file for shdma
from shdma.txt to renesas,shdma.txt.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link: https://lore.kernel.org/r/20190724114946.14021-1-horms+renesas@verge.net.au
[vkoul: add subsystem name]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The newer Allwinner SoCs have a DMA controller supported in Linux, with a
matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://lore.kernel.org/r/20190720092607.31095-3-maxime.ripard@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The older Allwinner SoCs have a DMA controller supported in Linux, with a
matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://lore.kernel.org/r/20190720092607.31095-2-maxime.ripard@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The DMA controllers and consumers have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20190720092607.31095-1-maxime.ripard@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Pull ARM Devicetree updates from Olof Johansson:
"We continue to see a lot of new material. I've highlighted some of it
below, but there's been more beyond that as well.
One of the sweeping changes is that many boards have seen their ARM
Mali GPU devices added to device trees, since the DRM drivers have now
been merged.
So, with the caveat that I have surely missed several great
contributions, here's a collection of the material this time around:
New SoCs:
- Mediatek mt8183 (4x Cortex-A73 + 4x Cortex-A53)
- TI J721E (2x Cortex-A72 + 3x Cortex-R5F + 3 DSPs + MMA)
- Amlogic G12B (4x Cortex-A73 + 2x Cortex-A53)
New Boards / platforms:
- Aspeed BMC support for a number of new server platforms
- Kontron SMARC SoM (several i.MX6 versions)
- Novtech's Meerkat96 (i.MX7)
- ST Micro Avenger96 board
- Hardkernel ODROID-N2 (Amlogic G12B)
- Purism Librem5 devkit (i.MX8MQ)
- Google Cheza (Qualcomm SDM845)
- Qualcomm Dragonboard 845c (Qualcomm SDM845)
- Hugsun X99 TV Box (Rockchip RK3399)
- Khadas Edge/Edge-V/Captain (Rockchip RK3399)
Updated / expanded boards and platforms:
- Renesas r7s9210 has a lot of new peripherals added
- Fixes and polish for Rockchip-based Chromebooks
- Amlogic G12A has a lot of peripherals added
- Nvidia Jetson Nano sees various fixes and improvements, and is now
at feature parity with TX1"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (586 commits)
ARM: dts: gemini: Set DIR-685 SPI CS as active low
ARM: dts: exynos: Adjust buck[78] regulators to supported values on Arndale Octa
ARM: dts: exynos: Adjust buck[78] regulators to supported values on Odroid XU3 family
ARM: dts: exynos: Move Mali400 GPU node to "/soc"
ARM: dts: exynos: Fix imprecise abort on Mali GPU probe on Exynos4210
arm64: dts: qcom: qcs404: Add missing space for cooling-cells property
arm64: dts: rockchip: Fix USB3 Type-C on rk3399-sapphire
arm64: dts: rockchip: Update DWC3 modules on RK3399 SoCs
arm64: dts: rockchip: enable rk3328 watchdog clock
ARM: dts: rockchip: add display nodes for rk322x
ARM: dts: rockchip: fix vop iommu-cells on rk322x
arm64: dts: rockchip: Add support for Hugsun X99 TV Box
arm64: dts: rockchip: Define values for the IPA governor for rock960
arm64: dts: rockchip: Fix multiple thermal zones conflict in rk3399.dtsi
arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
arm64: dts: rockchip: improve rk3328-roc-cc rgmii performance.
Revert "ARM: dts: rockchip: set PWM delay backlight settings for Minnie"
ARM: dts: rockchip: Configure BT_DEV_WAKE in on rk3288-veyron
arm64: dts: qcom: sdm845-cheza: add initial cheza dt
ARM: dts: msm8974-FP2: Add vibration motor
...
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More channel interrupts, one more clock, and only one
dmamux on i.mx7ulp-edma.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Tested-by: Angelo Dureghello <angelo@sysam.it>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add LS1028A qDMA controller bindings to fsl-qdma bindings.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add the optional resets property the pl330 dma node.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The filename matches mtk-uart-apdma.c.
So using "mtk-uart-apdma.txt" should be better.
And add some property.
Signed-off-by: Long Cheng <long.cheng@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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DMA in H6 is similar to other DMA controller, except it is first which
supports more than 32 request sources and has 16 channels. It also needs
additional clock to be enabled.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Pull ARM Device-tree updates from Olof Johansson:
"Besides new bindings and additional descriptions of hardware blocks
for various SoCs and boards, the main new contents here is:
SoCs:
- Intel Agilex (SoCFPGA)
- NXP i.MX8MM (Quad Cortex-A53 with media/graphics focus)
New boards:
- Allwinner:
+ RerVision H3-DVK (H3)
+ Oceanic 5205 5inMFD (H6)
+ Beelink GS2 (H6)
+ Orange Pi 3 (H6)
- Rockchip:
+ Orange Pi RK3399
+ Nanopi NEO4
+ Veyron-Mighty Chromebook variant
- Amlogic:
+ SEI Robotics SEI510
- ST Micro:
+ stm32mp157a discovery1
+ stm32mp157c discovery2
- NXP:
+ Eckelmann ci4x10 (i.MX6DL)
+ i.MX8MM EVK (i.MX8MM)
+ ZII i.MX7 RPU2 (i.MX7)
+ ZII SPB4 (VF610)
+ Zii Ultra (i.MX8M)
+ TQ TQMa7S (i.MX7Solo)
+ TQ TQMa7D (i.MX7Dual)
+ Kobo Aura (i.MX50)
+ Menlosystems M53 (i.MX53)j
- Nvidia:
+ Jetson Nano (Tegra T210)"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (593 commits)
arm64: dts: bitmain: Add UART pinctrl support for Sophon Edge
arm64: dts: bitmain: Add pinctrl support for BM1880 SoC
arm64: dts: bitmain: Add GPIO Line names for Sophon Edge board
arm64: dts: bitmain: Add GPIO support for BM1880 SoC
ARM: dts: gemini: Indent DIR-685 partition table
dt-bindings: hwmon (pwm-fan) Remove dead "cooling-*-state" properties
ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY
arm64: dts: msm8998: thermal: Restrict thermal zone name length to under 20
arm64: dts: msm8998: thermal: Fix number of supported sensors
arm64: dts: msm8998-mtp: thermal: Remove skin and battery thermal zones
arm64: dts: exynos: Move fixed-clocks out of soc
arm64: dts: exynos: Move pmu and timer nodes out of soc
ARM: dts: s5pv210: Fix camera clock provider on Goni board
ARM: dts: exynos: Properly override node to use MDMA0 on Universal C210
ARM: dts: exynos: Move fixed-clocks out of soc on Exynos3250
ARM: dts: exynos: Remove unneeded address/size cells from fixed-clock on Exynos3250
ARM: dts: exynos: Move pmu and timer nodes out of soc
arm64: dts: rockchip: fix IO domain voltage setting of APIO5 on rockpro64
arm64: dts: db820c: Add sound card support
arm64: dts: apq8096-db820c: Add HDMI display support
...
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Tegra186 Audio DMA controller has new updates from Tegra210 version.
Thus add new compatibility binding string and the same can be used
by Tegra194 as well.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Some synthesis time configuration parameters of the DMA controller can be
inferred from the hardware itself.
Use this information as it is more reliably than the information specified
in the devicetree which might be outdated if the HDL project got changed.
Deprecate the devicetree properties that can be inferred from the hardware
itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add imx8mq sdma support.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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specifier
For Spreadtrum DMA engine, all channels are equal, which means slave can
request any channels with setting a unique slave id to trigger this channel.
Thus we can remove the channel id from device tree to assign the channel
dynamically, moreover we should add the slave id in device tree.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Some dma channels can be reserved for secure mode or other
hardware on the SoC, so provide a binding for a bitmask
listing the available channels for the kernel to use.
This follows the pre-existing bcm,dma-channel-mask binding.
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tanglei Han <hantanglei@huawei.com>
Cc: Zhuangluan Su <suzhuangluan@hisilicon.com>
Cc: Ryan Grachek <ryan@edited.us>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: dmaengine@vger.kernel.org
Cc: devicetree@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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hisi-asp
Extend the k3dma driver binding to support hisi-asp hardware
variants.
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Zhuangluan Su <suzhuangluan@hisilicon.com>
Cc: Tanglei Han <hantanglei@huawei.com>
Cc: Ryan Grachek <ryan@edited.us>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: dmaengine@vger.kernel.org
Cc: devicetree@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Youlin Wang <wwx575822@notesmail.huawei.com>
Signed-off-by: Tanglei Han <hantanglei@huawei.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The commit a9ddb575d6d6
("dmaengine: dw_dmac: Enhance device tree support")
introduces is_private property in uncertain understanding what does it mean.
First of all, documentation defines DMA_PRIVATE capability as
Documentation/crypto/async-tx-api.txt:
The DMA_PRIVATE capability flag is used to tag dma devices that should not be
used by the general-purpose allocator. It can be set at initialization time
if it is known that a channel will always be private. Alternatively,
it is set when dma_request_channel() finds an unused "public" channel.
A couple caveats to note when implementing a driver and consumer:
1/ Once a channel has been privately allocated it will no longer be
considered by the general-purpose allocator even after a call to
dma_release_channel().
2/ Since capabilities are specified at the device level a dma_device with
multiple channels will either have all channels public, or all channels
private.
Documentation/driver-api/dmaengine/provider.rst:
- DMA_PRIVATE
The devices only supports slave transfers, and as such isn't available
for async transfers.
The capability had been introduced by the commit 59b5ec21446b
("dmaengine: introduce dma_request_channel and private channels")
and some code didn't changed from that times ever.
Taking into consideration above and the fact that on all known platforms
Synopsys DesignWare DMA engine is attached to serve slave transfers,
the DMA_PRIVATE capability must be enabled for this device unconditionally.
Otherwise, as rightfully noticed in drivers/dma/at_xdmac.c:
/*
* Without DMA_PRIVATE the driver is not able to allocate more than
* one channel, second allocation fails in private_candidate.
*/
because of of a caveats mentioned in above documentation excerpts.
So, remove conditional around DMA_PRIVATE followed by removal leftovers.
If someone wonders, DMA_PRIVATE can be not used if and only if the all channels
of the DMA controller are supposed to serve memory-to-memory like operations.
For example, EP93xx has two controllers, one of which can only perform
memory-to-memory transfers
Note, this change doesn't affect dmatest to be able to test such controllers.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (maintainer:SERIAL DRIVERS)
Cc: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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This property is not needed anymore, because the driver now autodetects it.
Delete references in documentation.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The width of the "length register" cannot be autodetected, and it is now
specified with a DT property. Add documentation for it.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Reviewed-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Document the devicetree bindings for NXP Layerscape qDMA controller
which could be found on NXP QorIQ Layerscape SoCs.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Pull dmaengine updates from Vinod Koul:
"This includes a new driver, removes R-Mobile APE6 as it is no longer
used, sprd cyclic dma support, last batch of dma_slave_config
direction removal and random updates to bunch of drivers.
Summary:
- New driver for UniPhier MIO DMA controller
- Remove R-Mobile APE6 support
- Sprd driver updates and support for cyclic link-list
- Remove dma_slave_config direction usage from rest of drivers
- Minor updates to dmatest, dw-dmac, zynqmp and bcm dma drivers"
* tag 'dmaengine-4.21-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (48 commits)
dmaengine: qcom_hidma: convert to DEFINE_SHOW_ATTRIBUTE
dmaengine: pxa: remove DBGFS_FUNC_DECL()
dmaengine: mic_x100_dma: convert to DEFINE_SHOW_ATTRIBUTE
dmaengine: amba-pl08x: convert to DEFINE_SHOW_ATTRIBUTE
dmaengine: Documentation: Add documentation for multi chan testing
dmaengine: dmatest: Add transfer_size parameter
dmaengine: dmatest: Add alignment parameter
dmaengine: dmatest: Use fixed point div to calculate iops
dmaengine: dmatest: Add support for multi channel testing
dmaengine: rcar-dmac: Document R8A774C0 bindings
dt-bindings: dmaengine: usb-dmac: Add binding for r8a774c0
dmaengine: zynqmp_dma: replace spin_lock_bh with spin_lock_irqsave
dmaengine: sprd: Add me as one of the module authors
dmaengine: sprd: Support DMA 2-stage transfer mode
dmaengine: sprd: Support DMA link-list cyclic callback
dmaengine: sprd: Set cur_desc as NULL when free or terminate one dma channel
dmaengine: sprd: Fix the last link-list configuration
dmaengine: sprd: Get transfer residue depending on the transfer direction
dmaengine: sprd: Remove direction usage from struct dma_slave_config
dmaengine: dmatest: fix a small memory leak in dmatest_func()
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Renesas' RZ/G2E (R8A774C0) SoC has DMA controllers compatible
with this driver, therefore document RZ/G2E specific bindings.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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This patch adds bindings for the r8a774c0 (RZ/G2E).
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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add uart dma bindings
Signed-off-by: Long Cheng <long.cheng@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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This patch for the DesignWare AHB Central
Direct Memory Access Controller adds the dma
protection control property:
"snps,dma-protection-control"
as well as the properties specific values defines into
a new include file: include/dt-bindings/dma/dw-dmac.h
Note: The protection control signals are one-to-one
mapped to the AHB HPROT[1:3] signals for this controller.
The HPROT0 (Data Access) is always hardwired to 1.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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This patch adds binding for r8a774a1 (RZ/G2M).
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Renesas' RZ/G2M (R8A774A1) SoC has DMA controllers compatible
with this driver, therefore document RZ/G2M specific bindings.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The MIO DMAC (Media IO DMA Controller) is used in UniPhier LD4,
Pro4, and sLD8 SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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This patch adds usb high-speed dmac binding for r8a77470 (RZ/G1C) SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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