| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-08-30 | PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable ↵ | Bharat Kumar Gogada | |
| memory space Updating device tree documentation with prefetchable memory sapce. Configuration space shifted to 64-bit address space. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> | |||
| 2016-03-11 | PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller | Bharat Kumar Gogada | |
| Add PCIe Root Port driver for Xilinx PCIe NWL bridge IP. [bhelgaas: wait for link like dw_pcie_wait_for_link(), simplify bitmap error path, typos, whitespace, fold in Dan Carpenter's PTR_ERR() fix] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Rob Herring <robh@kernel.org> | |||
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index : linux-toradex.git | |
| Linux kernel for Apalis and Colibri modules | Marcel Ziswiler |
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