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Add DT binding documentation for Sierra PHY. The PHY supports
a number of different protocols, including PCIe and USB.
The PHY lanes may be configured as single or multi-lane links.
Each link is treated as a separate sub-node. For example, if
there are 4 lanes in total the first 2 might be configured as
a multi-lane PCIe link while the other two are single lane
USB links, and in this case there would be 3 sub-nodes.
There are two resets for the PHY block (one for APB register
access, one for the PHY link) and separate resets for each
link. For multi-lane links, the reset corresponds to the
reset line on the master lane, the resets on other lanes
have no effect.
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Rob Herring <robh@kernel.org>
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