Age | Commit message (Collapse) | Author | |
---|---|---|---|
2020-07-01 | dt-bindings: phy: zynqmp-psgtr: Fix example's numbers of cells in reg | Laurent Pinchart | |
The DT examples are by default compiled in a parent that has #address-cells and #size-cells both set to 1. Fix the example accordingly, even if it doesn't match the actual hardware, as this is the recommended practice for DT bindings examples. Fixes: cea0f76a483d ("dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY") Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200701134853.30656-1-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org> | |||
2020-06-29 | dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY | Anurag Kumar Vulisha | |
Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed Processing System Gigabit Transceiver which provides PHY capabilities to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org> |