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This commit adds two properties to control the RX DLL and TX DLL
2ns delay on RXC/TXC RGMII clock lines. This is especially needed
if the MAC does not provide TXC delay by itself.
Related-to: ELB-1299
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
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Add support for Microchip Technology KSZ9131 10/100/1000 Ethernet PHY
Signed-off-by: Yuiko Oshino <yuiko.oshino@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit bff5b4b3737219195ca0caef4ff7884303cb5dc1)
Related-to: ELB-1299
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
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toradex_4.9-2.3.x-imx-next
Conflicts:
sound/soc/codecs/sgtl5000.c
sound/soc/fsl/imx-sgtl5000.c
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This is the 4.9.220 stable release
Conflicts:
arch/arm/Kconfig.debug
arch/arm/boot/dts/imx7s.dtsi
arch/arm/mach-imx/common.h
arch/arm/mach-imx/cpuidle-imx6q.c
arch/arm/mach-imx/cpuidle-imx6sx.c
arch/arm/mach-imx/suspend-imx6.S
block/blk-core.c
drivers/crypto/caam/caamalg.c
drivers/crypto/mxs-dcp.c
drivers/dma/imx-sdma.c
drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
drivers/input/keyboard/imx_keypad.c
drivers/input/keyboard/snvs_pwrkey.c
drivers/mmc/host/sdhci.c
drivers/net/can/flexcan.c
drivers/net/ethernet/freescale/fec_main.c
drivers/net/phy/phy_device.c
drivers/net/wireless/ath/ath10k/pci.c
drivers/tty/serial/imx.c
drivers/usb/dwc3/gadget.c
drivers/usb/host/xhci.c
include/linux/blkdev.h
include/linux/cpu.h
include/linux/platform_data/dma-imx-sdma.h
kernel/cpu.c
net/wireless/util.c
sound/soc/fsl/Kconfig
sound/soc/fsl/fsl_esai.c
sound/soc/fsl/fsl_sai.c
sound/soc/fsl/imx-sgtl5000.c
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This adds the devicetree bindings for the STMPE ADC. This also corrects
a typo in st,sample-time it is rather "6 -> 124 clocks" according
to the datasheet and not 144.
We need to use the naming stmpe_adc in devicetree because this is given
by the mfd device.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
(cherry-picked from commit 81cdab79818988d27d8aeb162b7988c9e6dde936)
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This patch reformats the parameter list for stmpe device in a
table-style so it is more clear to read.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
(cherry-picked from 270a60bcc8f23254d749987f3d2acb79ea5c599e)
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Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
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[ Upstream commit 26d5bb9e4c4b541c475751e015072eb2cbf70d15 ]
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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[ Upstream commit 73852e56827f5cb5db9d6e8dd8191fc2f2e8f424 ]
The abracon,tc-resistor property value is in kOhm.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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commit c737abc193d16e62e23e2fb585b8b7398ab380d8 upstream.
Armada-37xx UART0 registers are 0x200 bytes wide. Right next to them are
the UART1 registers that should not be declared in this node.
Update the example in DT bindings document accordingly.
Signed-off-by: allen yan <yanwei@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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[ Upstream commit 0df82dcd55832a99363ab7f9fab954fcacdac3ae ]
Fully compatible with mcp2515, the mcp25625 have integrated transceiver.
This patch add the mcp25625 to the device tree bindings documentation.
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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toradex_4.9-2.3.x-imx-next
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This is the 4.9.166 stable release
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commit 6c0c5dc33ff42af49243e94842d0ebdb153189ea upstream.
Add new compatible to the device tree bindings.
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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Introduce the "lrclk-strength" property to allow LRCLK pad drive strength
to be changed via device tree.
When running a stress playback loop test on a mx6dl wandboard channel
swap can be noticed on about 10% of the times.
While debugging this issue I noticed that when probing the SGTL5000
LRCLK pin with the scope the swap did not happen. After removing
the probe the swap started to happen again.
After changing the LRCLK pad drive strength to the maximum value the
issue is gone.
Same fix works on a mx6dl Colibri board as well.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 91dca475d4368bef170fe9b20bb2005b241cc4bc)
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On some systems the sdhci capabilty register is incorrect for one
reason or another.
The sdhci-caps-mask property specifies which bits in the register
are incorrect and should be turned off before using sdhci-caps to turn
on bits.
The sdhci-caps property specifies which bits should be turned on.
Signed-off-by: Zach Brown <zach.brown@ni.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 426ad975237e880c5ecdc1b74f0a4c34b93d3e14)
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Provide support for controlling reset pin. If this is not driven
correctly the device will be held in reset and will not respond.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
(cherry picked from commit f657b00df22e231da217ca0162a75db452475e8f)
Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com>
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From the i.MX 7 reference manual the drive strenght field
is defined as follows:
00 DSE_0_X1
01 DSE_1_X4
10 DSE_2_X2
11 DSE_3_X6
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
(cherry picked from commit 38524d73583e8f7fc61c8acd57b77c0a29889616)
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
(cherry picked from commit 16692ff50af0d7a216d71ff39b69d8971b08b690)
(cherry picked from commit 6f88e1d8c28585002d51f4c4232abea61a022763)
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The m41t0 variant is very similar to the already supported m41t00
variant, with the notable exception of the oscillator fail bit.
The data sheet notes:
If the oscillator fail (OF) bit is internally set to a '1,' this
indicates that the oscillator has either stopped, or was stopped
for some period of time and can be used to judge the validity of
the clock and date data.
The bit will get cleared with a regular write of the system time,
so no changes are needed to clear it.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
(cherry picked from commit 8566f70c8a90f3914b06e934852596ba94aaa381)
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The current imx-sgtl5000 driver always attaches the cpu-dai to ssi while
in fact it could be attached to other cpu-dais like SAI. Thus this patch
use a general code to support another cpu-dai. And meanwhile update the
devicetree for i.MX6 Series.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit f9302eb42ad8f597b46e681b5ad402af3fb7dd9d)
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This is the 4.9.144 stable release
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[ Upstream commit 321cc359d899a8e988f3725d87c18a628e1cc624 ]
We need this new compatibility string as we experienced different behavior
for this 10/100Mbits/s macb interface on this particular SoC.
Backward compatibility is preserved as we keep the alternative strings.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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According to AK5558 MCLK frequence must not exceed 36.864 MHz.
Limit maximum supported rate as function of max MCLK frequency,
sample bits and number of slots.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 236796cad225daa39d5b77d763a1d964dd4de4c9)
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The existing implementation calculates mclk rate as function
of audio sample rate multiplied to multiplier taken from Table 5.
However this is not accurate for Manual Setting Mode - tables 3 & 4 from
AK4458 RM defines rate (LRCK/FS) and frame width (MCLK/16fs..1152fs) ranges
as parameters to calculate mclk frequency. Aside of this - adjust
bclk:mclk ratio from machine driver as function of "compatible" id.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 527b8b7032dcb75c14bb2790330ab96743d83b16)
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support more codecs, codec is specified by compatible string
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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i.MX8QM/i.MX8QXP has pad type/definition change on B0, update
binding doc accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
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Add two new message command I2S_TX_POINTER and I2S_RX_POINTER,
which are used to get the hw pointer in m4 side. For in low
power audio mode, m4 won't send notification every period, the
notification only be sent when hw pointer reach end of buffer,
so we need these command to get the position of hw pointer,
user can use it to calculate the timestamp.
Restructure send message and recv message together for i2s_rpmsg,
that every send message has a recv message. so the
i2s_send_message can store the recv message indepedently. one
reason is that the receive message is async withe send message.
The low power audio is disabled in default, user need to enabled
it by add "fsl,enable-lpa" in dts.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
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Add a new property 'video-mode' binding for panel rm67191
which is used to specify a video data transfer mode.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
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Add dts binding doc for i.MX8MM TMU.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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Use a specific compatible string for 850D in order to limit DSD MCLK
frequency for platforms newer than 850D.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
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Add devicetree binding doc for i.MX8MM pinctrl driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
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Add devicetree binding doc for i.MX8MQ pinctrl driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
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i.MX8qxp uses two LDB(one primary, one auxiliary) to support dual
channel mode. This patch adds DT property descriptions for those
properties needed by this case.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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specify the spdif in imx8mm for the ipg clock is higher that
it can support 192kHz
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
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Add the device-tree bindings for the display bridge
Samsung MIPI DSIM on i.MX platforms.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
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Add the device-tree bindings for the display node eLCDIF
on i.MX platforms.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
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Add documentation for micfil IP.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
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Add new cell for sw_done/sw_done_selector, because PDM need enable
software done feature in sdma script.
The new fourth cell defined as below:
Bit31: sw_done
Bit15~bit0: selector
For example: 0x80000000 means sw_done enabled for done0 sector which
is for PDM on i.mx8mm.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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enable rpmsg on imx8mm
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
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Add the pcie support for imx8mm and verify
it on imx8mm evk board when internal pll is
used as ref clock.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
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Add support to select the clock source to the CAN Protocol Engine (PE).
It's SoC Implementation dependent. Refer to RM for detailed definition
of each SoC.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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In order to avoid the name problem going forward with
integration with Qcom, Qcom has their own dsp and hifi
is competitor, so the hifi name should not be used in
our code.
So use the name of dsp instead of hifi to fix this
problem.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
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ov5640 sensor
Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
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NXP i.MX7ULP EVK boards all sensors connect with M4 core, A core
has to conmunicate with sensors by virtual io bus like rpmsg bus.
The driver implement the virtual sensor input driver to configure
sensors active/idle/delay actions and report the sensors' event to
user space.
Supply below sysfs for user to enable/disable detector and counter,
set poll delay:
/sys/class/misc/step_counter/enable
/sys/class/misc/step_detector/enable
/sys/class/misc/step_counter/poll_delay
Reviewed-by: Elven Wang <elven.wang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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- To save power consumption, PHY related CLKs can be
gated off after the configurations are done.
- The impedance ratio should be configured refer to
differnet REXT values.
0x6c <--> REXT valuse is 85Ohms
Default values 0x80 <--> REXT value is 100Ohms.
- IMX8QM_HSIO_PHY_X1_APB_CLK is mandatory required when
access SATA PHY registers. Change the power domain to SATA.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
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Signed-off-by: Antoine Bouyer <antoine.bouyer@nxp.com>
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Add gpio interrupt chip support that only support wakeup feature
by M4 core.
Reviewed-by: Robin Gong<yibin.gong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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The DSI-HDMI converter, ADV7535, driver uses four i2c memory maps: MAIN,
DSI-CEC, EDID and PACKET.
While the MAIN address is hard-coded in the ROM chip, the other three
can be programmed into the MAIN memory map.
Currently, the three memory maps addresses, that can be programmed, are
hard-coded into the code.
In order to avoid conflicts with other i2c clients on the bus, update
the driver to use configurable addresses specified in DTS file.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
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i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
Note IMX7ULP has two clock domains: M4 and A7. This binding doc
is only for A7 clock domain.
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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