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2025-10-22dt-bindings: clock: Add "#interconnect-cells" property in IPQ9574 exampleLuo Jie
The Networking Subsystem (NSS) clock controller acts as both a clock provider and an interconnect provider. The #interconnect-cells property is needed in the Device Tree Source (DTS) to ensure that client drivers such as the PPE driver can correctly acquire ICC clocks from the NSS ICC provider. Add the #interconnect-cells property to the IPQ9574 Device Tree binding example to complete it. Fixes: 28300ecedce4 ("dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions") Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-2-081f4956be02@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-10-22dt-bindings: touchscreen: consolidate simple touch controller to ↵Frank Li
trivial-touch.yaml Move azoteq,iqs5xx.yaml, himax,hx83112b.yaml, hynitron,cstxxx.yaml, ilitek_ts_i2c.yaml, semtech,sx8654.yaml, ar1021.txt to trivial-touch.yaml to consolidate simple touch yaml binding to one file. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20251021201924.2881098-2-Frank.Li@nxp.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2025-10-22dt-bindings: touchscreen: trivial-touch: add reset-gpios and wakeup-sourceFrank Li
Add optional reset-gpios and wakeup-source properties. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20251021201924.2881098-1-Frank.Li@nxp.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2025-10-22spi: dt-bindings: spi-rockchip: Add RK3506 compatibleHeiko Stuebner
The SPI controller found in the RK3506 SoC is still compatible to the original one introduced with the RK3066, so add the RK3506 compatible to the list of its variants. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20251022004200.204276-1-heiko@sntech.de Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-22dt-bindings: pinctrl: Convert bitmain,bm1880-pinctrl to DT schemaRob Herring (Arm)
Convert the bitmain,bm1880-pinctrl binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-22dt-bindings: pinctrl: Convert brcm,ns2-pinmux to DT schemaRob Herring (Arm)
Convert the brcm,ns2-pinmux binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-22dt-bindings: pinctrl: Convert actions,s900-pinctrl to DT schemaRob Herring (Arm)
Convert the actions,s900-pinctrl binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-22dt-bindings: pinctrl: Convert actions,s700-pinctrl to DT schemaRob Herring (Arm)
Convert the actions,s700-pinctrl binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-22dt-bindings: power: rockchip: Add support for RV1126BFinley Xiao
Add power domain IDs for RV1126B SoC. Add a new compatible because register fields have changed. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-10-22dt-bindings: power: Add support for MT8196 power controllersAngeloGioacchino Del Regno
Add support for the power controllers found in the MediaTek MT8196 Chromebook SoC. This chip has three power controllers, two of which located in the SCP subsystems (where one can be directly controlled and the other can be controlled only through the HW Voter IP), and one located in the Multimedia HFRP subsystem, controllable only through the HW Voter IP. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-10-22dt-bindings: serial: sh-sci: Fix r8a78000 interruptsGeert Uytterhoeven
The SCIF instances on R-Car Gen5 have a single interrupt, just like on other R-Car SoCs. Fixes: 6ac1d60473727931 ("dt-bindings: serial: sh-sci: Document r8a78000 bindings") Cc: stable <stable@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/09bc9881b31bdb948ce8b69a2b5acf633f5505a4.1759920441.git.geert+renesas@glider.be Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-22dt-bindings: serial: samsung: add samsung,exynos8890-uart compatibleIvaylo Ivanov
Add dedicated samsung,exynos8890-uart compatible to the dt-schema for representing uart of the exynos8890. Like exynos8895, it has a required DT property samsung,uart-fifosize, so reuse support for it. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250914132201.2622955-1-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-22dt-bindings: serial: samsung: Add compatible for ARTPEC-9 SoCRavi Patel
Add Axis ARTPEC-9 uart compatible to the bindings documentation. It is similar to the older samsung,exynos8895-uart design. Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20250918032703.8885-1-ravi.patel@samsung.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-22dt-bindings: mmc: rockchip-dw-mshc: Add compatible string for RK3506Heiko Stuebner
The dw-mshc controller in the RK3506 is compatible to the one first found in the RK3288 SoC, so add the RK3506 to the variant list. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-10-22dt-bindings: usb: Add Apple dwc3Sven Peter
Apple Silicon uses Synopsys DesignWare dwc3 based USB controllers for their Type-C ports. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neal Gompa <neal@gompa.dev> Signed-off-by: Sven Peter <sven@kernel.org> Link: https://patch.msgid.link/20251015-b4-aplpe-dwc3-v2-1-cbd65a2d511a@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-22dt-bindings: display: bridge: renesas,dsi-csi2-tx: Allow panel@ subnodeMarek Vasut
This controller can have both bridges and panels connected to it. In order to describe panels properly in DT, pull in dsi-controller.yaml and disallow only unevaluatedProperties, because the panel node is optional. Include example binding with panel. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://lore.kernel.org/r/20250904210147.186728-4-marek.vasut+renesas@mailbox.org
2025-10-22dt-bindings: soc: samsung: exynos-sysreg: add gs101 hsi0 and misc compatiblesPeter Griffin
Add dedicated compatibles for gs101 hsi0 and misc sysreg controllers to the documentation. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251013-automatic-clocks-v1-1-72851ee00300@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-22dt-bindings: soc: samsung: exynos-sysreg: add power-domainsAndré Draszik
On gs101 only, sysreg can be part of a power domain, so we need to allow the relevant property 'power-domains' for the relevant compatibles google,gs101-*-sysreg. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251010-power-domains-dt-bindings-soc-samsung-exynos-sysreg-v2-1-552f5787a3f3@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-21dt-bindings: net: dsa: yt921x: Add Motorcomm YT921x switch supportDavid Yang
The Motorcomm YT921x series is a family of Ethernet switches with up to 8 internal GbE PHYs and up to 2 GMACs. Signed-off-by: David Yang <mmyangfl@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251017060859.326450-2-mmyangfl@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-21ASoC: spacemit: add i2s support to K1 SoCMark Brown
Merge series from Troy Mitchell <troy.mitchell@linux.spacemit.com>: On the K1 SoC, there is a full-duplex I2S controller. The I2S is programmable, with the sample width configurable to 8, 16, 18, or 32 bits. A dedicated FIFO is provided for transmit (TXFIFO) and another for receive (RXFIFO). In non-packed mode, both FIFOs are 32 entries deep and 32 bits wide, giving a total of 32 samples each. The register definitions can be found here[1] Link: https://developer.spacemit.com/documentation?token=Rn9Kw3iFHirAMgkIpTAcV2Arnkf#18.2-spi%2Fi2s [1] Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> --- Changes in v5: - Patch 1/2: - nothing - Patch 2/2: - dont't read sspsp value in spacemit_i2s_init() - set SSPSP_FSRT bit for DSP_A mode (was missing in previous version) - Link to v4: https://lore.kernel.org/all/20250921-k1-i2s-v4-0-4f819f50e468@linux.spacemit.com/ Changes in v4: - Patch 1/2: - nothing - Patch 2/2: - Only 8k, 16k and 48k rates are supported - Only 16-bit and 32-bit are supported - Use the runtime constraint API instead of modifying dai->driver - Link to v3: https://lore.kernel.org/r/20250911-k1-i2s-v3-0-57f173732f9c@linux.spacemit.com Changes in v3: - Patch 1/2: - simplify dma-names definition - Patch 2/2 - remove empty spacemit_i2s_remove() - move FSRT setup for DSP_A into switch-case in spacemit_i2s_set_fmt() - Link to v2: https://lore.kernel.org/r/20250828-k1-i2s-v2-0-09e7b40f002c@linux.spacemit.com Changes in v2: - Patch 1/2: - modify commit message - remove unused third cell from pdma dmas property - update SPDX license in spacemit,k1-i2s.yaml to (GPL-2.0-only OR BSD-2-Clause) - Patch 2/2: - modify commit message - reset_assert in dai_ops::remove - select CMA and DMA_CMA in Kconfig - use devm_reset_control_get_exclusive - Link to v1: https://lore.kernel.org/r/20250814-k1-i2s-v1-0-c31149b29041@linux.spacemit.com --- Troy Mitchell (2): ASoC: dt-bindings: Add bindings for SpacemiT K1 ASoC: spacemit: add i2s support for K1 SoC .../devicetree/bindings/sound/spacemit,k1-i2s.yaml | 87 ++++ sound/soc/Kconfig | 1 + sound/soc/Makefile | 1 + sound/soc/spacemit/Kconfig | 16 + sound/soc/spacemit/Makefile | 5 + sound/soc/spacemit/k1_i2s.c | 458 +++++++++++++++++++++ 6 files changed, 568 insertions(+) --- base-commit: 4f010aced22532eea2ef0d9a2f5db7c64a196fec change-id: 20250813-k1-i2s-115bf65eaac8 Best regards, -- Troy Mitchell <troy.mitchell@linux.spacemit.com>
2025-10-21ASoC: amd: ps: Propagate the PCI subsystem Vendor andMark Brown
Merge series from Simon Trimmer <simont@opensource.cirrus.com>: This series of two patches propagates the PCI subsystem Vendor and Device IDs so that they can be used by component drivers to differentiate firmware loads.
2025-10-21dt-bindings: mfd: Add binding for the PF1550 PMICSamuel Kayode
Add a DT binding document for pf1550 PMIC. This describes the core MFD device along with its children: regulators, charger and onkey. Signed-off-by: Samuel Kayode <samuel.kayode@savoirfairelinux.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://patch.msgid.link/20251001-pf1550-v12-1-a3302aa41687@savoirfairelinux.com Signed-off-by: Lee Jones <lee@kernel.org>
2025-10-21ASoC: dt-bindings: don't check node namesWolfram Sang
Node names are already and properly checked by the core schema. No need to do it again. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251020060951.30776-9-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-21dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoCConor Dooley
"mss-top-sysreg" contains clocks, pinctrl, resets, an interrupt controller and more. At this point, only the reset controller child is described as that's all that is described by the existing bindings. The clock controller already has a dedicated node, and will retain it as there are other clock regions, so like the mailbox, a compatible-based lookup of the syscon is sufficient to keep the clock driver working as before, so no child is needed. There's also an interrupt multiplexing service provided by this syscon, for which there is work in progress at [1]. Link: https://lore.kernel.org/linux-gpio/20240723-uncouple-enforcer-7c48e4a4fefe@wendy/ [1] Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-10-21dt-bindings: gpu: img,powervr-rogue: Rework the allOf sectionMarek Vasut
Rework the current allOf: section such that all handling of clocks/clock-names properties happens first, and all handling of power-domains/power-domain-names happens second. This allows the allOf section to limit various GPU models to matching clocks count in the first half, and apply the same for power-domains count in the second half, without conflating the two limits together. This makes addition of GPU models with different clocks and power-domains count easier. No functional change intended. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Matt Coster <matt.coster@imgtec.com> Link: https://lore.kernel.org/r/20251018130147.12831-2-marek.vasut+renesas@mailbox.org Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2025-10-21dt-bindings: gpu: img,powervr-rogue: Drop useless power domains itemsMarek Vasut
The power-domains items: list is not very informative, replace it with plain minItems/maxItems instead. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Matt Coster <matt.coster@imgtec.com> Link: https://lore.kernel.org/r/20251018130147.12831-1-marek.vasut+renesas@mailbox.org Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2025-10-21dt-bindings: power: qcom,rpmpd: document the Kaanapali RPMh Power DomainsJishnu Prakash
Document the RPMh Power Domains on the Kaanapali Platform. Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-10-21dt-bindings: mmc: Add support for BCM72116 and BCM74371 SD host controllerKamal Dasu
Updating compatibility to support BCM72116 and BCM74371 SD host controller similar to other settop SoCs. Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-10-21dt-bindings: mmc: sdhci-msm: Add sm8750 compatibleSarthak Garg
Document the compatible string for the SDHCI controller on the sm8750 platform. Signed-off-by: Sarthak Garg <sarthak.garg@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-10-21dt-bindings: mmc: sdhci-msm: Add Kaanapali compatibleManish Pandey
Document the compatible string for the SDHCI controller on the Kaanapali platform. Signed-off-by: Manish Pandey <manish.pandey@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-10-21dt-bindings: net: airoha: Add AN7583 supportLorenzo Bianconi
Introduce AN7583 ethernet controller support to Airoha EN7581 device-tree bindings. The main difference between EN7581 and AN7583 is the number of reset lines required by the controller (AN7583 does not require hsi-mac). Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251017-an7583-eth-support-v3-1-f28319666667@kernel.org Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-10-21dt-bindings: leds: Add default-brightness property to common.yamlJean-François Lessard
Add default-brightness property to leds/common.yaml to establish a single canonical definition for LED brightness initialization. The property is currently defined locally in leds/leds-pwm.yaml and is needed by auxdisplay/titanmec,tm16xx.yaml. Properties should be defined in only one location to avoid type inconsistencies across bindings. Signed-off-by: Jean-François Lessard <jefflessard3@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Lee Jones <lee@kernel.org>
2025-10-21dt-bindings: leds: arc,arc2c0608: Convert to DT SchemaHarrison Carter
Convert the ArcticSand arc2c0608 LED driver to the dt-schema. Signed-off-by: Harrison Carter <hcarter@thegoodpenguin.co.uk> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Lee Jones <lee@kernel.org>
2025-10-21Merge tag 'drm-misc-next-2025-10-02' of ↵Simona Vetter
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for v6.19: UAPI Changes: Cross-subsystem Changes: - fbcon cleanups. - Make drivers depend on FB_TILEBLITTING instead of selecting it, and hide FB_MODE_HELPERS. Core Changes: - More preparations for rust. - Throttle dirty worker with vblank - Use drm_for_each_bridge_in_chain_scoped in drm's bridge code and assorted fixes. - Ensure drm_client_modeset tests are enabled in UML. - Rename ttm_bo_put to ttm_bo_fini, as a further step in removing the TTM bo refcount. - Add POST_LT_ADJ_REQ training sequence. - Show list of removed but still allocated bridges. - Add a simulated vblank interrupt for hardware without it, and add some helpers to use them in vkms and hypervdrm. Driver Changes: - Assorted small fixes, cleanups and updates to host1x, tegra, panthor, amdxdna, gud, vc4, ssd130x, ivpu, panfrost, panthor, sysfb, bridge/sn65dsi86, solomon, ast, tidss. - Convert drivers from using .round_rate() to .determine_rate() - Add support for KD116N3730A07/A12, chromebook mt8189, JT101TM023, LQ079L1SX01, raspberrypi 5" panels. - Improve reclocking on tegra186+ with nouveau. - Improve runtime pm in amdxdna. - Add support for HTX_PAI in imx. - Use a helper to calculate dumb buffer sizes in most drivers. Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://lore.kernel.org/r/b412fb91-8545-466a-8102-d89c0f2758a7@linux.intel.com
2025-10-21dt-bindings: embedded-controller: add Traverse Ten64 board controllerMathew McBride
Add device tree binding for the board (micro)controller on Ten64 family boards[1]. The schema is simple and is (presently) only consumed by U-Boot, but it is possible nvmem, watchdog and other features could be described in the future, as well as extension to future Traverse boards. [1] https://ten64doc.traverse.com.au/hardware/microcontroller/ Signed-off-by: Mathew McBride <matt@traverse.com.au> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-21dt-bindings: PCI: mediatek: Add support for Airoha AN7583Christian Marangi
Introduce Airoha AN7583 SoC compatible in mediatek PCIe controller binding. Similar to GEN3, the Airoha AN7583 GEN2 PCIe controller require the PBUS csr property to permit the correct functionality of the PCIe controller. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251020111121.31779-3-ansuelsmth@gmail.com
2025-10-21dt-bindings: PCI: mediatek: Convert to YAML schemaChristian Marangi
Convert the PCI mediatek Documentation to YAML schema to enable validation of the supported GEN1/2 Mediatek PCIe controller. While converting, lots of cleanup were done from the .txt with better specifying what is supported by the various PCIe controller variant and drop of redundant info that are part of the standard PCIe Host Bridge schema. To reduce schema complexity the .txt is split in 2 YAML, one for mt7623/mt2701 and the other for every other compatible. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251020111121.31779-2-ansuelsmth@gmail.com
2025-10-20dt-bindings: iio: imu: smi330: Add bindingJianping Shen
Add devicetree binding for Bosch imu smi330. The smi330 is a combined three axis angular rate and three axis acceleration sensor module. Signed-off-by: Jianping Shen <Jianping.Shen@de.bosch.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-10-20dt-bindings: iio: adc: add max14001Marilene Andrade Garcia
Add device-tree documentation for MAX14001/MAX14002 ADCs. The MAX14001/MAX14002 are isolated, single-channel analog-to-digital converters with programmable voltage comparators and inrush current control optimized for configurable binary input applications. They share the same features, but in the MAX14001 the inrush trigger threshold, current magnitude, and current duration are all programmable, whereas in the MAX14002 these parameters are fixed. Co-developed-by: Kim Seer Paller <kimseer.paller@analog.com> Signed-off-by: Kim Seer Paller <kimseer.paller@analog.com> Signed-off-by: Marilene Andrade Garcia <marilene.agarcia@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Marcelo Schmitt <marcelo.schmitt1@gmail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-10-20dt-bindings: altera: removal of generic PE1 dtsLothar Rubusch
Remove the binding for the generic Mercury+ AA1 on PE1 carrier board. The removed Mercury+ AA1 on PE1 carrier board is just a particular setup case, which is actually replaced by the set of generic Mercury+ AA1 combinations patch. In other words a combination of a Mercury+ AA1 on a PE1 base board, with boot mode SD card is already covered by the generic AA1 combinations. There is no further reason to keep this particular case now in a redundantly. Thus the redundant DT setup is removed. Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-10-20dt-bindings: altera: add Mercury AA1 variantsLothar Rubusch
Update binding with combined .dts for the Mercury+ PE1, PE3 and ST1 carrier boards with the Mercury+ AA1 SoM. Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-10-20dt-bindings: altera: add binding for Mercury+ SA2Lothar Rubusch
Update the device-tree binding for the Enclustra Mercury+ SA2 SoM. Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-10-20dt-bindings: altera: add Enclustra Mercury SA1Lothar Rubusch
Update the DT binding for the Enclustra Mercury+ SA1 SoM Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-10-20scsi: ufs: dt-bindings: exynos: Add power-domainsAndré Draszik
The UFS controller can be part of a power domain, so we need to allow the relevant property 'power-domains'. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://patch.msgid.link/20251007-power-domains-scsi-ufs-dt-bindings-exynos-v1-1-1acfa81a887a@linaro.org Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2025-10-20dt-bindings: dma: snps,dw-axi-dmac: Add iommu propertyKhairul Anuar Romli
Agilex5 integrates an ARM SMMU v3 (System Memory Management Unit) with dedicated Translation Buffer Units (TBUs) assigned to various peripherals, including the Synopsys DesignWare AXI DMA controller. Each TBU handles address translation for its associated device by mapping stream IDs to memory access permissions and virtual-to-physical address mappings via the SMMU core. The DesignWare AXI DMAC instances on Agilex5 are connected to their respective TBUs. These TBUs forward DMA transactions from the controller through the SMMU, enabling IOMMU-based features such as: - Address translation for DMA operations - Isolation and protection of memory regions accessed by the DMA controller - Support for secure and virtualized environments through enforced access control To support this configuration, the `iommus` property must be added to the binding schema for `snps,dw-axi-dmac`. This allows the device tree to associate each DMA controller with the correct SMMU stream ID, enabling the Linux IOMMU framework to configure translation contexts at runtime. This change documents the IOMMU support for the DMA controller on Agilex5 and allows proper integration with the SMMUv3 hardware. Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-10-20dt-bindings: mtd: cdns,hp-nfc: Add iommu propertyKhairul Anuar Romli
Agilex5 integrates an ARM SMMU (System Memory Management Unit) with Translation Buffer Units (TBUs) assigned to various peripherals, including the NAND controller. The Cadence HP NAND controller ("cdns,hp-nfc") on Agilex5 is behind a TBU connected to the system's SMMUv3. To support this, the controller requires an `iommus` property in the device tree to properly configure address translation through the IOMMU framework. Adding the `iommus` property to the binding schema allows the OS to associate the NAND controller with its corresponding SMMU stream ID. This enables: - DMA address translation between the controller and system memory - Memory protection for NAND operations - Proper functioning of the IOMMU framework in secure or virtualized environments This change documents the IOMMU integration for the NAND controller on platforms like Agilex5 where such hardware is present. Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-10-20dt-bindings: arm: rockchip: Add 100ASK DShanPi A1Hsun Lai
This documents 100ASK DShanPi A1 which is a SBC based on RK3576 SoC. Link: https://wiki.dshanpi.org/en/docs/DshanPi-A1/intro/ Signed-off-by: Hsun Lai <i@chainsx.cn> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/0601AB836AE5F348+20251014021623.286121-2-i@chainsx.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-10-20dt-bindings: arm: rockchip: Add LinkEase EasePi R1Liangbin Lian
LinkEase EasePi R1 is a high-performance mini router based on RK3568. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Liangbin Lian <jjm2473@gmail.com> Link: https://patch.msgid.link/20251014051226.64255-3-jjm2473@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-10-20dt-bindings: vendor-prefixes: Document LinkEaseLiangbin Lian
LinkEase is a company focusing on the research and development of network equipment and related software and hardware from Shenzhen. Add vendor prefix for it. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Liangbin Lian <jjm2473@gmail.com> Link: https://patch.msgid.link/20251014051226.64255-2-jjm2473@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-10-20dt-bindings: soc: imx-iomuxc-gpr: Document the CSI muxFabio Estevam
On i.MX6Q/6DL the following subnodes exist to describe the CSI port muxing: - ipu1_csi0_mux - ipu1_csi1_mux - ipu2_csi0_mux - ipu2_csi1_mux As they were not documented, dt-schema emits warnings like: 'ipu1_csi0_mux', 'ipu1_csi1_mux' do not match any of the regexes: '^pinctrl-[0-9]+$' Add a top-level patternProperties entry for these CSI mux subnodes and restrict it to i.MX6Q. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.0.4) at 2026-01-07 17:09:47 +0000