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The upsteamed commit is 0c516b4ff85c0be4cee5b30ae59c9565c7f91a00
ASoC: cs42xx8: Add codec driver support for CS42448/CS42888
This patch adds support for the Cirrus Logic CS42448/CS42888 Audio CODEC that
has six/four 24-bit AD and eight 24-bit DA converters.
[ CS42448/CS42888 supports both I2C and SPI control ports. As initial patch,
this patch only adds the support for I2C. ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Acked-by: Brian Austin <brian.austin@cirrus.com>
Acked-by: Paul Handrigan <Paul.Handrigan@cirrus.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
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cherry-picked commit is 43d24e76b69826ce32292f47060ad78cdd0197fa
Header of this commit is "ASoC: fsl_esai: Add ESAI CPU DAI driver", use upstream
driver to replace current one.
Merged feature is:
1. Move setting of PRRC and PCRC to the end of hw_params, and disable it in
shutdown function.
2. Merged the xrun handler with this commit.
3. Use dma init with NO_RESIDUE|NO_DT|COMPAT.
4. Add spba clock for ESAI
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
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There are three clock for ESAI, esai_extal, esai_ipg, esai_mem.
Make the clock for ESAI more clear.
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
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Change the output-rate, output-width to p2p-rate, p2p-width.
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
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HNP and SRP
This patch adds a file chipidea.txt for how to demo chipidea usb OTG HNP and SRP
functions via sysfs input files, any other possible information should be
documented for chipidea usb driver in future can be added into this file.
Signed-off-by: Li Jun <b47624@freescale.com>
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OTG HNP and SRP
This patch adds sysfs interface description for chipidea USB OTG HNP and SRP.
Signed-off-by: Li Jun <b47624@freescale.com>
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The current imx-wm8962 machine driver is designed for SSI as CPU DAI only
while as its name we should make the driver more generic to any other CPU
DAI on i.MX serires -- ESAI, SAI for example.
So this patch makes the driver more general so as to support those non-SSI
cases.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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The new Solo X has more requirements for SDMA events. So it creates a event mux
to remap most of event numbers in GPR (General Purpose Register). If we want to
use SDMA support for those module who do not get the even number as default, we
need to configure GPR first.
Thus this patch adds this support of GPR event remapping configuration to the
SDMA driver.
Acked-by: Robin Gong <b38343@freescale.com>
Acked-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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The SAI mainly has the following clocks:
bus clock
control and configure registers and to generate synchronous
interrupts and DMA requests.
mclk1, mclk2, mclk3
to generate the bit clock when the receiver or transmitter is
configured for an internally generated bit clock.
So this patch adds these clocks and their clock controls to the driver.
[ To concern the old DTB cases, I've added a bit of extra code to make
the driver compatible with them. And by marking clock NULL if failed
to get, the clk_prepare() or clk_get_rate() would easily return 0
so no further path should be broken. -- by Nicolin ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Acked-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 17d1eb6628e70488c44c46003dcfe583696bb7b7)
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Make use of the new enable_gpio field and allow it to be set from DT as
well. Now that all legacy users of platform data have been converted to
initialize this field to an invalid value, it is safe to use the field
from the driver.
Signed-off-by: Thierry Reding <treding@nvidia.com>
(cherry picked from commit 8265b2e4e62632b01f998095d1bbda4d281629fe)
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add snvs power key driver since ic team has fix some issues of SNVS on i.mx6sx
Signed-off-by: Robin Gong <b38343@freescale.com>
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Signed-off-by: Denis Carikli <denis@eukrea.com>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
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The next coming i.MX6 Solo X SoC also contains SAI module while we use
imp_pcm_init() for i.MX platform.
So this patch adds one compatible route for imx6sx and updates the DT
doc accordingly.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 30c35252aadb460e009ca8a3fdc8891903bdfc66)
[ Added essential parameters to imx_pcm_init() calling due to build error,
resulted from the define change of the function on the upstream. ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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This adds the Document for Freescale SAI driver under
Documentation/devicetree/bindings/sound/.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit b6344859b911990152e5ee411e62b82eb968004f)
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This patch adds SAI script support to imx-sdma.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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The current imx-sgtl5000 driver always attaches the cpu-dai to ssi while
in fact it could be attached to other cpu-dais like SAI. Thus this patch
use a general code to support another cpu-dai. And meanwhile update the
devicetree for i.MX6 Series.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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Add fixed phy address support.
i.MX6sx has two MACs, and MAC1 mdio bus connects to two phys which
means MAC2 share MDIO bus with MAC1. So for any one of the two MACn,
which can scan two phy address. For current implementment, it selects
the little address for the default address and binding with the phy.
For the situation, user can add the fixed phy address to DTS.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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We have already renamed the file name, change doc name at this
patch.
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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This patch makes it possible to set the chipidea udc into full-speed only mode.
It is set by the oftree property "maximum-speed = full-speed".
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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this helper will be used for controllers which
want to work at a lower speed even though they
support higher USB transfer rates.
One such case is Texas Instruments' AM437x
SoC where it uses a USB3 controller without
a USB3 PHY, rendering the controller USB2-only.
Signed-off-by: Felipe Balbi <balbi@ti.com>
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MIPI CSI2 depends on this clock to work.
This patch also updates the binding document.
Signed-off-by: Robby Cai <R63905@freescale.com>
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This patch adds mxc display driver support for the mxsfb
driver so that it may interactive with encoder drivers.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch almost reworks the LDB driver to make the
implementation simpler and clearer. The new version
should support all the LDB modules embedded in imx53,
imx6qdl and imx6sx. The lvds-channel subsidiary DT
node is introduced to represent each LVDS channel.
People may specify a channel's CRTC, working mode(dual
mode or split mode), data width, data mapping, display
timing and if it is a primary channel in the node.
Change logs:
* Use CTRC concept so that the driver may support both
IPU and LCDIF as the display engines.
* Add mxc dispdrv enable() callback.
* Cache LDB ctrl register value at probe()/setup()/
enable() stages and finally write to the register at
enable() stage.
* Simplify logics for setting ctrl/bus muxing/clocks.
* Use regmap to write crtl and bus muxing registers.
* Remove LDB description in DT binding doc fsl_ipuv3_fb.txt.
Instead, add a new one in fsl,ldb.txt.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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support pfuze200 chip which remove SW1C and SW4 based on pfuze100.
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit f2518480c7b744296a5587990a54e3a284d932b8)
Conflicts:
drivers/regulator/pfuze100-regulator.c
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According to imx6q RM, there are three clock providers for ASRC:
Module clock Clock root Gate
asrck_clock_d spdif1_clk_root N/A
ipg_clk ahb_clk_root asrc_clk_enable
mem_clk ahb_clk_root asrc_clk_enable
while the current clock tree describes a confusing clock named 'asrc'
that combines this three clocks by rooting its rate from spdif1_clk_root
but set its gate from ipg/mem_clk.
Thus this patch first fixes the name asrc to the correct one -- spdif1
and adds the missing clocks to ASRC.
[ Since we don't have the gate for asrck_clock_d, we can pass spdif0_clk
to ASRC in the devicetree directly. ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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Some flashes can only be properly accessed when the ECC mode is
specified, so a way to describe such mode is required.
Together, the ECC strength and step size define the correction capability,
so that we say we will correct "{strength} bit errors per {size} bytes".
The interpretation of these parameters is implementation-defined, but they
often have ramifications on the formation, interpretation, and placement of
correction metadata on the flash. Not all implementations must support all
possible combinations. Implementations are encouraged to further define the
value(s) they support.
Acked-by: Boris BREZILLON <b.brezillon.dev@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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This patch adds the binding file for Freescale QuadSPI driver.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Starting from IMX6, the flexcan stop mode control bits is SoC specific,
move it out of IP driver and parse it from devicetree.
It's good from maintain perspective and can avoid adding too many SoC
specifi bits in driver but with no IP changes when the IMX SoC series
keep growing.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Add core support to allow clock implementations to select the best
parent clock when rounding a rate, e.g. the one which can provide the
closest clock rate to that requested. This is by way of adding a new
clock op, determine_rate(), which is like round_rate() but has an extra
parameter to allow the clock implementation to optionally select a
different parent clock. The core then takes care of reparenting the
clock when setting the rate.
The parent change takes place with the help of some new private data
members. struct clk::new_parent specifies a clock's new parent (NULL
indicates no change), and struct clk::new_child specifies a clock's new
child (whose new_parent member points back to it). The purpose of these
are to allow correct walking of the future tree for notifications prior
to actually reparenting any clocks, specifically to skip child clocks
who are being reparented to another clock (they will be notified via the
new parent), and to include any new child clock. These pointers are set
by clk_calc_subtree(), and the new_child pointer gets cleared when a
child is actually reparented to avoid duplicate POST_RATE_CHANGE
notifications.
Each place where round_rate() is called, determine_rate() is checked
first and called in preference. This restructures a few of the call
sites to simplify the logic into if/else blocks.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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The patch adds the binding file for Freescale vf610 ADC driver.
CC: Shawn Guo <shawn.guo@linaro.org>
CC: Jonathan Cameron <jic23@kernel.org>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: Peter Meerwald <pmeerw@pmeerw.net>
CC: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC.
And this lvds2, along with lvds1, can be used to provide external clock source
to the internal pll, such as pll4_audio and pll5_video.
So This patch mainly adds the lvds2 to the clock tree and fix its relationship
with pll4 accordingly.
[ To reduce the risk from code changing. This patch only takes care of pll4
related part. We might later need to add the relationship with pll5 too. ]
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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This patch documents the Hannstar CABC driver's device tree bindings.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch update fec devicetree binding doc that add Optional
properties "fsl,num_tx_queues" and "fsl,num_rx_queues".
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core
driver.
Signed-off-by: Anson Huang <b20788@freescale.com>
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It adds initial MSL support for i.mx6sx, including below features:
1. add cpu type check;
2. add system timer support;
3. add clock tree support;
4. add machine layer init support;
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Acked-by: Jason Liu
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Update for hsic controller
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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The current mtd_type_show() misses the MTD_MLCNANDFLASH case.
This patch adds the case for it, and also updates the ABI.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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Based on community patch-set, re-setup pcie driver on
imx6 platforms.
* re-fine the pcie clks.
* add the pcie support in dts files.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Add support for the PCIe port present on the i.MX6 family of controllers.
These use the Synopsis Designware core tied to their own PHY.
Signed-off-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
(cherry picked from commit bb38919ec56e0758c3ae56dfc091dcde1391353e)
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switch to community upstreamed pcie driver.
Revert "ENGR00275213-1 arm: pcie: enable pcie on imx6 platforms"
This reverts commit d33370c77e57aed5a9b6733c9898418541fed54a.
Conflicts:
Documentation/devicetree/bindings/clock/imx6q-clock.txt
arch/arm/mach-imx/clk-imx6q.c
Signed-off-by: Richard Zhu <r65037@freescale.com>
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It is used to indicate whether we use SoC's usb charger
detection or not. Besides, we add anatop phandle since
we need to use anatop register to do most of charger detect operations.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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In default way, we use the ecc_strength/ecc_step size calculated by ourselves
and use all the OOB area.
This patch adds a new property : "fsl,use-minimum-ecc"
If we enable it, we will firstly try to use the datasheet's minimum required
ECC provided by the MTD layer (the ecc_strength_ds/ecc_step_ds fields
in the nand_chip{}). So we may have free space in the OOB area by using the
minimum ECC, and we may support JFFS2 with some SLC NANDs, such as Micron's
SLC NAND.
If we fail to use the minimum ECC, we will use the legacy method to calculate
the ecc_strength and ecc_step size.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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If wakeup is enabled, enter stop mode, else enter disabled mode.
Self wake can only work on stop mode.
For imx6q, the stop request has to be mannually assert on
IOMUX GPR13[28:29] register, we use syscon to control that bit.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Add gpios for tranceiver control.
Before we have a common tranceiver binding, we use this way first.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Add anatop phandle which is used to access anatop registers to
control PHY's power and other USB operations.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Add "fsl,imx6q-usbphy" for imx6dq and imx6dl, add
"fsl,imx6sl-usbphy" for imx6sl.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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We add a new sys node for ecc step size. So update the ABI document about it.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
[Brian: edited description, modified 'ecc_strength']
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Now that the last user of NAND_BBT_SCANALLPAGES has been removed, let's
kill this peculiar BBT feature flag.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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NAND_BBT_SCANEMPTY is a strange, badly-supported option with omap as its
single remaining user.
NAND_BBT_SCANEMPTY was likely used by accident in omap2[1]. And anyway,
omap2 doesn't scan the chip for bad blocks (courtesy of
NAND_SKIP_BBTSCAN), and so its use of this option is irrelevant.
This patch drops the NAND_BBT_SCANEMPTY option.
[1] http://lists.infradead.org/pipermail/linux-mtd/2012-July/042902.html
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Ivan Djelic <ivan.djelic@parrot.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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1. add epit1, epit2 and tzasc2 clock gate to clk tree so that
clk framework can manage these clock gates;
2. adjust ipu2_di1 clock gate registry code to follow hardware
register CG index sequence.
Signed-off-by: Anson Huang <b20788@freescale.com>
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