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SDb WP pin is not connected by default on MX6Q CPU2 board, so we removed it
in DTS file. BTW, SDb slot is designed for WiFi slot, it is ok to disable WP
for old CPU board also.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit 2efa09eb28d7404933725bc25b528641a9dc10f9)
(cherry picked from commit dd6e28f2932284494c89bb4897ad84c01db969d8)
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disable gpmi nand module in imx6qdl default dts since it conflicts with
uart3
Signed-off-by: Allen Xu <b45815@freescale.com>
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NAND scans the bad blocks during kernel boots up, which invokes the
gpmi_ecc_read_oob function to check the badblock mark for each block. In
this function the oob data was raw read from NAND chip without ECC, so
it hardly to guarantee the consistency of the data considering the
possible bitflips. It found that in some MLC NAND the oob data changed
and consequently the BBT changed in different power cycles. This issue
may cause the UBIFS mount failed.
To fix this issue, add "nand_on_flash_bbt" option in dts to store the BBT
in NAND flash. On the first time kernel boot up, all bad blocks and
probably some fake bad block would be recognized and be recorded in
on-nand bad block table. From the second time boot, kernel will read BBT
from NAND Flash rather than calling gpmi_ecc_read_oob function to check
bad block.
No bad block would be missed when create BBT since the probability that
16bit bad block mark filps from 0x00 to 0xFF is extremely low.
Signed-off-by: Allen Xu <b45815@freescale.com>
(cherry picked from commit d957353768a1b6d39b340b9d10b22fc42b0aa8e2)
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Add enet RGMII ENET_REF_CLK pin set for sabreauto board.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Enable OTG and host 1 USB function.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Li Jun <jun.li@freescale.com>
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Add FEC magic-packet feature support.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add property "revision-a10" to device tree to set the default command
set to A10.
Signed-off-by: Zidan Wang <b50113@freescale.com>
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- enable pcie on imx6qdl sabreauto boards.
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
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As the radio machine drive use the codec_of_node, so add si476x-codec
node for this usage.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 89a4342b5d6ee21173566fab6ae017c660a23620)
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From schematic, below GPIO keys' active state is low, so we need
to set correct active state in dts.
i.MX6Q/DL-SABRESD board: power, vol+ and vol-.
i.MX6Q/DL-SABREAUTO board: home, back, prog, vol+ and vol-.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit f1319b3268db3e0e80d85ba9f4ae3b569b916dd4)
Signed-off-by: Robin Gong <b38343@freescale.com>
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Add TV decoder (ADV7180 on baseboard) support
Signed-off-by: Robby Cai <r63905@freescale.com>
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Add v4l2 output support for imx6qdl sabreauto board
Signed-off-by: Robby Cai <r63905@freescale.com>
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Add PWM setting for brightness control
Signed-off-by: Robby Cai <r63905@freescale.com>
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disp_id 0 is already used for LDB.
The patch fixed the conflict and supported both in one dts file.
Signed-off-by: Robby Cai <r63905@freescale.com>
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Enable LDB driver for imx6q/dl sabreauto board.
Signed-off-by: Robby Cai <r63905@freescale.com>
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NOTE since SD Card in main board takes a long route hence with
Drive Speed High 80 OHMS causing error on high speed cards.
Per suggestion DSE 40 OHMS is used.
And the SD1 on sabreauto baseboard is conflict with gpmi nand.
The conflict pins are DAT4~DAT7. Since the SD3 on cpu board
already supports 8 bit bus width, we do not want add an extra
dts file for it, so we disable 8 bit and use 4 bit width for
this issue.
[haibo chen:
cherry-pick commit e38226f4cbf222ce9377963e20fe5f1d7103a2af
cherry-pick commit 3807ed7ac39ec402f19bb27d2d60ceb3ce5448b2
from imx_3.10.y]
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
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Enable the sdio wakeup capability for SDIO cards.
Note: we do not enable it for sabresd usdhc4 since it has a solid
eMMC card on it.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit 9ea7e84fe686a5c959aebbbf4a1b81dcb1c3e3fd)
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All i.MX6 SabreAuto/SabreSD/EVK has the ability to keep card power
during suspend. So add this capability for them.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit 3f18df4746eb33e934c55de23d6496bb4adad33b)
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SD3.0 cards require power cycle the card during suspend/resume,
or the card re-enumeration after resume will fail to be identified
as UHS card since the card is already working on 1.8v mode and refuse
to ack the S18R request, thus, it will then work on normal high speed
mode instead.
We have to use external vmmc regulator to power cycle the card during
suspend/resume to reset card signal voltage to 3.3v frist for the later
1.8v voltage switch.
However, due to the sabreauto board limitation, we can not use external
regulator to powere off card by default since the card power is shared
with card detect pullup. Disabling the vmmc regulator will also shutdown
the cd pullup which causes incorrect illusion of card exist.
(e.g. plug out the card, mmc core wll think the card is exist since cd pin
is low but it never can find the card)
HW rework removing R695 and enable PAD internal pullup is needed to
fix this isssue.
User can manually open the mask of vmmc in dts to enable using external
regulator if your board has done the rework as said above.
Or by default we still do not power off card during suspend.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit 2fd1bf9320bce1c22f2406c74277b7422653511e)
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Add sysclk and spba clock, and assigned-clocks
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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enable gpio-key on imx6qdl-sabreauto board.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Add isl29023 sensor device tree support on i.MX6Q/DL/SX platform.
Signed-off-by: Luwei Zhou <b45643@freescale.com>
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Add missing devicetree nodes and binding for the support.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Enable asrc support and enable asrc p2p for sound-cs42888.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Enable sound-cs42888 in sabreauto board. Enable clock route for esai
from external 24.576MHz OSC to internal ESAI clock via analog clock2
PADs on the SoC and pll4 so that ESAI can get an entirely synchronous
clock source against CS42888.
anaclk2 0 1 24576000
lvds2_in 0 1 24576000
pll4_sel 0 1 24576000
pll4_audio 0 1 24576000
pll4_post_div 0 1 24576000
pll4_audio_div 0 1 24576000
esai_sel 0 1 24576000
esai_pred 0 1 24576000
esai_podf 0 1 24576000
esai 0 1 24576000
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Add pfuze100 support on imx6qdl-sabreaauto board.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Add mag3110 sensor device tree support on i.MX6Q/DL/SX platform.
Signed-off-by: Luwei Zhou <b45643@freescale.com>
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Add mma8451 sensor device tree support on i.MX6Q/DL/SX platform.
Signed-off-by: Luwei Zhou <b45643@freescale.com>
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The flexcan1 is disabled by default since it's conflict with fec.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit 0f6cfd8708633ee2f924aa509b30bb17b185f84e)
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3.14.y
Add EETI egalax touch screen for i.MX6q-sabreauto board and
i.MX6dl-sabreauto board in the new branch 3.14.y.
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
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Add imx6qdl-sabreauto board uart3 DTE pad set. To avoid a flood of
dts files, there comment out DTE pinctrl set. If user want to test
DTE mode, it needs to rebuild the DTB file.
(cherry picked from commit dc6028b08c6bd718d57866a1714f3977ba7820d3)
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add device tree support on i.MX6Q/DL-ARD platform.
Signed-off-by: Luwei Zhou <b45643@freescale.com>
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Enable dcic driver for imx6q/dl SabreSD and SabreAI
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Code merger from imx_3.10_y branch
-Add hdmi core driver, hdmi video and hdmi audio item to dts file
-Add hdcp and cec item
Signed-off-by: Sandor Yu <R01008@freescale.com>
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On imx6qdl-sabreauto board, there are three IO expanders implemented by
max7310, which are all controlled by I2C3. And GPIO5_4 is steering the
I2C3_SDA availability, while GPIO1_15 is used to reset max7310.
[shawn.guo: cherry-pick commit b938a6cb0d4c from imx_3.10.y]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Conflicts:
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
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This patch adds spdif support for imx6qdl-sabreauto by inserting the cpu dai
node with pinctrl group and its ASoC dai link node.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
[shawn.guo: cherry-pick commit 1169cf1f4d60 from upstream]
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Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that
boards that share the same pinctrl setting do not have to define it time
and time again in <board>.dts. However, along with the devices and use
cases being added continuously, the pinctrl setting nodes under iomuxc
becomes more than expected. This bloats device tree blob for particular
board unnecessarily since only a small subset of those pinctrl setting
nodes will be used by the board. It impacts not only the DTB file size
but also the run-time device tree lookup efficiency.
The patch moves all the pinctrl data into individual boards as needed.
With the changes, the pinctrl setting nodes becomes local to particular
board, and it makes no sense to continue numbering the setting for
given peripheral. Thus, all the pinctrl phandler name gets updated to
have only peripheral name in there.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
[shawn.guo: cherry-pick commit 817c27a128e1 from upstream]
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This is needed for supporting ultra high speed cards like SD3.0 cards.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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The imx6q and imx6dl are two pin-to-pin compatible SoCs. The same board
design can work with either chip plugged into the socket, e.g. sabresd
and sabreauto boards.
We currently define pin groups in imx6q.dtsi and imx6dl.dtsi
respectively because the pad macro names are different between two
chips. This brings a maintenance burden on having the same label point
to the same pin group defined in two places.
The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs
pad macro names. Then the pin groups becomes completely common between
imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the
long term maintenance of imx6q/dt pin settings becomes easier.
Unfortunately, the change brings some dramatic diff stat, but it's all
about DTS file, and the ultimate net diff stat is good.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Enable the WEIM NOR for imx6q{dl}-sabreauto boards.
For the pin conflict with SPI NOR, its status is set to "disabled".
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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In the imx6q-sabreauto and imx6dl-sabreauto boards,
the pin MX6Q{DL}_PAD_EIM_D19 is used as a GPIO for SPI NOR, but
it is used as a data pin for the WEIM NOR.
In order to fix the conflict, this patch removes the pin from the hog,
and adds a new board-level pinctrl: pinctrl_ecspi1_sabreauto.
The SPI NOR selects this pinctrl_ecspi1_sabreauto when it is enabled.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Since the SPI/NOR has pin conflict with the WEIM NOR,
we disable the spi/nor by default.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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enable the gpmi-nand for imx6q-sabreauto and imx6qdl-sabreauto boards.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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The sabreauto and sabresd boards are common for imx6q and imx6dl.
Create imx6qdl-sabreauto.dtsi and imx6qdl-sabresd.dtsi for those
common parts.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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