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This enables the buffers which bring the WE# signal to SODIMM-93/99
and tri-states the CPU pins directly connected to SODIMM-93/99.
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All pins not assigned to other functionality are muxed to be
gpio. This allows for later sysfs access to these pins.
Some USB OTG control signals are among the list as the driver for
these is not yet ready.
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UART A was lacking DCD/DSR/DTR muxing,
UART C pinmuxing was set for DCE.
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MIC_GND is controlled with a FET. With a pullup set in the dtb MIC_GND
is active by default.
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On the evaluation board is a pull down on this line, thus
low active makes more sense.
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Enable the external memory bus, aka weim.
Define a sram at CS0 and one at CS1, each in non multiplexed mode.
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Fix the mapping of PWM<A> to SOC pwmX mapping and
set the second SOC pin to input on PWM<A>, PWM<D>.
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imx6qdl-apalis.dtsi: enable stmpe-adc in device tree
defconfig: add stmpe-adc to minimal defconfig
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Add groups required by colibri-imx6
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Add device tree integration and add the device to the dtb.
i2c device, interrupt and reset GPIO can be specified in the dts as follows:
Note that additionally you may have to set the pinmuxing for the pins to
be GPIO.
&i2c1 {
status = "okay";
pcap@10 {
/* TouchRevolution Fusion 7 and 10 multi-touch controller */
compatible = "touchrevolution,fusion-f0710a";
reg = <0x10>;
gpios = <&gpio6 10 0 /* MXM-11, Pen down interrupt */
&gpio6 9 0 /* MXM-13, Reset interrupt */
>;
};
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CAAM depends on the clock used by WEIM interface. This patch supplied by
Haung Shijie corrects the issue by adding the clock to the device tree
entry for CAAM.
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
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As the sabreauto CPU board schematics mentions, the MIPI connector
isn't mechanically compatible with Freescale MIPI display and camera
board, then we have no way to support MIPI features currently on
this platform. So, let's disable MIPI CSI.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 453d409281228429270b9f294728e5cad1c63ee0)
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As the sabreauto CPU board schematics mentions, the MIPI connector
isn't mechanically compatible with Freescale MIPI display and camera
board, then we have only the parallel CSI video input that is supported
by the v4l2_cap_0 node. So, let's remove the orphan one - v4l2_cap_1.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 1396bc28eac7e968e278a9ce36cdc7a44b0417bd)
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MIPI CSI2 depends on this clock to work.
This patch also updates the binding document.
Signed-off-by: Robby Cai <R63905@freescale.com>
(cherry picked from commit 67e7963f6f7ddb6c001bb34c6af71f2330fd0e3f)
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wakeup
LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.
This patch adds the dummy regulator to the dts files.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Add hwrng support for i.MX6SL.
1. Add RNG driver. This driver originated as fsl-rngc.c. It
has been modified to support device tree. The name has been
changed since it supports both b and c variants of RNG.
2. Added clock and compatible info to the device tree data.
3. Added the entry in the options in the Kconfig for hwrng.
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
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This patch mainly adds the clock route from external 24.576MHz OSC to internal
ESAI clock via analog clock2 PADs on the SoC and pll4 so that ESAI can get an
entirely synchronous clock source against CS42888.
[ 1, We found if using pll4 to generate a 24.576MHz from inernal 24.0MHz OSC,
we would get noise during the audio playback via ESAI->CS42888 even though
this generated clock's rate is equal to the external one statistically. It
might be resulted from the tiny difference between two clock source, which
might be crucial to the sensitive CODEC we use -- CS42888. So we here apply
the old 3.0.35 way to feed ESAI the same clock source as CS42888.
2, Ideally, we should use bypass mode for pll4 since we only need to get
the raw rate (24.576MHz) while currently bypass mode in clk-pllv3.c isn't
entirely supported: The clock rate would be fixed to 24.0MHz if setting to
bypass, which would cause child clock get an incorrect rate and the driver
who uses the child clock fail to derive a needed clock rate, and it might
be dangerous to involve the clk-pllv3.c driver to this fix. Thus we here
apply 3.0.35 way provisionally. ]
Expected result:
anaclk2 0 1 24576000
lvds2_in 0 1 24576000
pll4_sel 0 1 24576000
pll4_audio 0 1 786432000
pll4_post_div 0 1 786432000
pll4_audio_div 0 1 786432000
esai_sel 0 1 786432000
esai_pred 0 1 98304000
esai_podf 0 1 24576000
esai 0 1 24576000
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 49584be724d4d9c7a753d2b981b3932d8d871eb4)
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This patch removes the device tree node lvds_cabc_ctrl, since
it is replaced by hannstar_cabc_lvds0 and hannstar_cabc_lvds1.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 6a3d2c5e858afeef695bcd9fe2ecc0933d3d29da)
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This patch adds a device tree node for the Hannstar CABC function.
We currently disable the CABC feature since it makes a panel's
backlight unstable when display content varies considerably from
time to time.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 0c98df5d1b04ea043e5279628aebf406c250f5e3)
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This patch adds a device tree node for the Hannstar CABC function.
The LVDS0 and LVDS1 interfaces of the i.MX6dql Sabreauto platform
shares a control pin for the CABC function, but LVDS1's control
wire is invalid for the unpopulated resistor R265 on the main board.
We currently disable the CABC feature since it makes a panel's
backlight unstable when display content varies considerably from
time to time.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 6af4f4ac7c361a60fe05400497f644db3adcfc94)
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