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When the M4 core is enabled on i.MX6, the QSPI2 clk can't be gated,
otherwise, the M4 will hang. This patch add a check to make sure when
M4 is enabled, just skip the QSPI2 clk gating operations.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit e2f17323916eae636e63353d742c986227b72702)
(cherry picked from commit 60def702db2c083cc6c0486100a829d71dc74845)
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QSPI2/GPMI_IO share the same clock source but with the
different gate, need explicitely gate the QSPI2 & GPMI_IO
during the clock init phase according to the SOC design.
The topo of the clock for the GPMI_IO and NAND as below:
mux --> pre divider --> post divider --gate-- >GPMI_IO
|-gate-- >QSPI2
(Note: i.MX6SX:GPMI_NAND and GSPI2 is PINMUX conflicts.)
The SOC design spec required that if change the parent clock
of the GPMI_IO or QSPI2, need gate the GPMI_IO and QSPI2 first
otherwise, there will have some glitch which cause the divider
malfunciton. Thus, we need explicitely gate QSPI2 & GPMI_IO at
the clock initialization phase and then later on common clock
framework will gurantee that each time, the parent clock rate
changes after the child clock is disabled(gated).
Signed-off-by: Jason Liu <r64343@freescale.com>
(cherry picked from commit 7712fd2cfa2ba2d7577d2836cebd9ff7ac6d34a8)
(cherry picked from commit 110d63a5886e065e77a69f816216af044c096a44)
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SSI and SSI_IPG are controlled by the same clock gating bits, so register
them with imx_clk_gate2_shared.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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SAI and SAI_IPG are controlled by the same clock gating bits, so register
them with imx_clk_gate2_shared.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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imx_clk_gate2_flags() uses CGR value 2b'11, while imx_clk_gate()
use CGR value 2b'01. We need 2b'11 which means "clock is on during
all modes, except STOP mode".
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit 51841a54f6746ce06b16a3297014069a2b3b97c2)
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M4 can NOT switch its clk parent due to glitch MUX,
to handle this case, A9 will help switch M4's clk
parent, the flow is as below:
M4:
1. enter low power idle, send bus use count-- to A9;
2. enter wfi and only wait for MU interrupt;
3. receive A9's clk switch ready message, go into low
power idle;
4. receive interrupt to exit low power idle, send request
to A9 for increase busfreq and M4 freq, enter wfi
and only wait for MU interrupt;
5. receive A9 ready message, go out of low power idle.
A9:
1. when receive M4's message of entering low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to OSC, ungate M4 clk,
send ready command to wake up M4 into low power idle;
2. when receive M4's message of exiting low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to origin high clk,
ungate M4 clk, send ready command to wake up M4
to exit low power idle;
Signed-off-by: Anson Huang <b20788@freescale.com>
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Since CAN device is allocated to run on M4 and handled by M4 if M4 is enabled,
so we do not set CAN parent clock when M4 is enabled.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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By default, uboot set uart clk parent to OSC to make UART work when M4
is enabled. In the situation, uart maximum baud rate only reach at 1.5Mbps
that cannot match real case requirement.
The patch set the uart module clock source to pll3_80m in default. If
test low power case, it needs to add "uart_from_osc" in kernel command line.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit 2e4986437817a5e4ff251a0594abcf3614e52a20)
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imx6sx clk/pm of a9/m4 related changes in mcc2.0 updates
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
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"Patch ENGR00329450 ARM: imx: set CLK_SET_RATE_GATE for gate and divider clocks"
requires that the particular clock (derived from PLL) need to be disabled before
its rate is changed. While on imx6sx, CSI0 and CSI1 shares the same CSI clock,
which means the CSI clock cannot be disabled then changed the clock when another
CSI module is already working.
Currently the CSI clock is only derived from OSC 24Mhz instead of PLL.
Now use the clk_register_gate() without CLK_SET_RATE_GATE flag by compromise
to make two CSIs work properly.
Signed-off-by: Robby Cai <r63905@freescale.com>
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This patch mainly adds the clock route from external 24.576MHz OSC to internal
ESAI clock via analog clock2 PADs on the SoC and pll4 so that ESAI can get an
entirely synchronous clock source against CS42888.
Expected result:
anaclk2 0 1 24576000
lvds2_in 0 1 24576000
pll4_sel 0 1 24576000
pll4_audio 0 1 786432000
pll4_post_div 0 1 786432000
pll4_audio_div 0 1 786432000
esai_sel 0 1 786432000
esai_pred 0 1 98304000
esai_podf 0 1 24576000
esai_extal 0 1 24576000
The spdif clock use the parent pll4_audio_div, it is prepared in spdif probe
by the regmap. So the pll4_sel will be prepared, So we can't do operation of
setting esai_extal in init_late, because pll4_sel has flag CLK_SET_PARENT_GATE,
then we can't do clk_set_parent when it is prepared, here move it to
init_machine function.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC.
And this lvds2, along with lvds1, can be used to provide external clock source
to the internal pll, such as pll4_audio and pll5_video.
So This patch mainly adds the lvds2 to the clock tree and fix its relationship
with pll4 accordingly.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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As A9 and M4 share many resources on i.MX6SX, especially for
clk and power related resource, so we need to handle the hardware
conflict between these two cores, there are two cases that we
need to consider currently:
1. clk management: for every clk node, only when both A9 and
M4 do NOT need it, then we can disable it from hardware;
2. power management: only when both A9 and M4 agree to enter
low power mode, then system can enter it.
Here we use MU and hardware SEMA4 to achieve our goal, MU is
for communiation between A9 and M4, SEMA4 is to protect the
shared memory.
For clk management, we use shared memory to maintain the clk
status for both A9 and M4 side, and this shared memory is
protected by hardware SEMA4, A9 and M4 will maintain their
own clk tree info in their SW environment, and get other
CORE's clk tree info from shared memory to decide whether
to perform a hardware setting change when they plan to.
For power management, M4 is treated as a high speed device
in A9 side, M4 is booting up with 227MHz by default, only
when M4 freq drop to below than 24MHz, then A9 is able to
enter low bus mode and low power idle mode. Everytime A9
is trying to adjust bus freq, it will request M4 to stay
at wfi, and once bus freq scaling is done, A9 will send
message to wake up M4 to continue, this is because M4 can
NOT access DDR or other important bus during bus freq scaling.
Whenever M4 wants high bus freq, it can send message to A9 to
increase bus freq, All these communications are done by MU
module.
For further use case implementation, we can define new protocol
to achieve, everytime MU receives a message, it will trigger
a thread to handle this request, A9 can response according
to the message.
Signed-off-by: Anson Huang <b20788@freescale.com>
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change procedure.
Recent checks added to the clock code prints warning during ddr frequency change procedure.
Hence the clock rates printed by clk_summary after ddr freq change are incorrect.
This patch fixes the issue by:
1. Removing CLK_SET_RATE_GATE for ocram_clk since it has a busy bit to be checked when
the ocram_podf is changed.
2. Added the CLK_GET_RATE_NOCACHE flag for PLL clocks, so that the rate is calculated each time.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Those system bus related mux only can be switched by busfreq driver,
and in busfreq asm code, it already follow the flow that hardware design
require, so no need to do flow check for these clk mux:
i.MX6Q/DL: periph_clk2_sel and pre_periph_clk_sel;
i.MX6SL: periph_clk2_sel, pre_periph_clk_sel,
periph2_clk2_sel and pre_periph2_clk_sel
i.MX6SX: periph_clk2_sel, pre_periph_clk_sel,
periph2_clk2_sel and pre_periph2_clk_sel.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Change perclk parent to OSC instead of IPG, as IPG clock may
be changed by busfreq.
when kernel command line has "uart_from_osc" defined, uart clk will
select OSC as its parent, this is to make PLL3 be able to be off
for low power purpose, as we need all PLLs off in low power idle
mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
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for PLL clocks"
The commit aabf4911f9971d4a6f02fe74bfdd39e7d74b7154, which added a check
to prevent pll rate changes when PLL is enabled, causes incorrect reporting
of MMDC clock during low power IDLE.
So revert the patch as the code needs to be improved to handle all cases.
Revert "ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocks"
This reverts commit aabf4911f9971d4a6f02fe74bfdd39e7d74b7154.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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This is a smilar change for imx6sx clock tree as what we did for imx6q
with commit 0bec46131d88 (ENGR00318063-8: ARM: imx6q: hide buggy
ldb_di_sel from clk API).
As the valid procedure of switching ldb_di_sel on imx6sx is not
available yet, we hide this buggy mux by looking at the parent selection
done by bootloader and register it statically to clock framework, so
that switching this buggy mux becomes impossible.
Also, since the bit width of ldb_di_sels is 3, we add two "dummy"
entries for ldb_di_sels to avoid out-of-bounds error.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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As some modules need to access ocotp in MSL, so we need to
make sure it is enabled during MSL, after kernel boot up,
clk dirver will disable it in late init.
Signed-off-by: Anson Huang <b20788@freescale.com>
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We already know that pll2_bus is the best parent of QSPI clock. Let's
set it up in clock initialization as the default, so that we can save
those implicit parent switching and rate changing calls from clock
framework.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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initialized
Since flag CLK_SET_PARENT_GATE is introduced, clk_set_parent() and
clk_set_rate() could possibly fail when clock is prepared/enabled
beforehand. Let's move the prepare/enable of clocks after parent and
rate setup to avoid such possible failures.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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There are a bunch of clk_enable_prepare, clk_set_parent and clk_set_rate
calls in imx6 clock driver's initialization. They are called without
retunr check. If there is something going wrong with the calls, they
will just fail silently.
The patch creates a set of helper functions imx_clk_enable_prepare,
imx_clk_set_parent and imx_clk_set_rate, and use them instead from clock
initialization to check the return and print error message to tell
failures if any.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The i.MX6 Reference Manual requires PLLs to be powered down before
changing its rate. Let's add flag CLK_SET_RATE_GATE for PLLs and
audio/video dividers to enforce the check at clock core level. So any
clk_set_rate() call from clients on these clocks will fail if the clocks
are not disabled and unprepared.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The mux clocks found on imx6 SoCs are all glitchy ones except
pll1_sw_clk_sel, axi_sel, periph_clk_sel and periph2_clk_sel. When
switching parent clock of a glitchy mux without gating, a glitch could
be generated and propagated into the downstream divider, and hence locks
up the divider and results in no clock output.
To avoid the situation, the parent switching should happen only when
the clock is gated. Add CLK_SET_PARENT_GATE flag for i.MX mux clocks,
so that clock core will make that check during clk_set_parent() call.
Since glitchless clocks do not need this flag, we create
imx_clk_mux_glitchless() without this flag for them. The periph_clk_sel
and periph2_clk_sel are registered by imx_clk_busy_mux() which does not
set this flag anyway, so they need no change.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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imx_clk_mux_flags
All the users of function imx_clk_mux_flags() set CLK_SET_RATE_PARENT
to request rate change propagatiopn up to parent. In this case, it
should be good to clear flag CLK_SET_RATE_NO_REPARENT to let clk core
find the best parent clock for the requested rate.
Let's drop flag CLK_SET_RATE_NO_REPARENT for imx_clk_mux_flags(), so
that function imx_clk_mux_flags_reparent() can just be saved.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The current imx6sx clock driver combines two mux clocks ocram_alt_sel
and ocram_sel into one, while ocram_alt_sel is a glitchy mux and
ocram_sel is a glitchless one. Fix it to match the clock tree in
Reference Manual.
One thing clk API clients need to take care is that clk_set_parent()
can be called on glitchy ocram_alt_sel only when ocram_sel selects the
other path, i.e. periph. Otherwise, a glitch could be generated on
ocram_alt_sel and get propagated into the divider ocram_podf. In that
case, ocram_podf gets locked up and ocram clock has no output.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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From reference manual, periph2_pre's parent list option 3 is
pll4_audio_div, not pll2_198m. And periph2_clk2 's parent of
option 1 should be osc, not pll2.
Need to mask handshake of mmdc ch0.
Signed-off-by: Anson Huang <b20788@freescale.com>
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There are three clock for ESAI, esai_extal, esai_ipg, esai_mem.
Make the clock for ESAI more clear.
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
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On i.MX6SX, when CA9 and CM4 are working together, CA9 can
NOT disable those shared modules' clock, so keep those
clocks CM4 needs always enabled.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Shawn's patch -- ARM: imx: shared gate support for i.MX clk_gate2 clocko
has fixed the problem of clock conflicts due to sharing a same gate.
So from now on, we can no longer need to take care the shared gate clock
for each audio clock route. Thus this patch separates them by using the
new clock registering helper function. And meanwhile, we set a proper
rate for each route so as to support each module.
For S/PDIF, we use 98304000Hz so that the current driver would perfectly
get 32000Hz and 48000Hz sample rate playback support, even though we
can only get 43885Hz for 44100Hz sample rate in this way -- If user
want to playback 44100Hz group sample rates, they need to change the
parent rate.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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Set vadc clock parent to PLL3 USB OTG.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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enable mcc a9 linux demo on imx6sx.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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SAI derives its mclk from SSI_CLK, so this patch sets a default value for them.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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We set the maximum clock frequency for the WEIM module.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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On Solo X, SPDIF and AUDIO clocks shares one single gate to switch two
entirely different clock routes:
SPDIF <-- <---- SPDIF_PODF ----....
\ /
gate1
/ \
AUDIO <-- <---- AUDIO_PODF ----....
The two audio modules would easily cause conflict during clock operations
if running in the same time:
SPDIF <-- gate1 <---- SPDIF_PODF ----....
AUDIO <-- gate1 <---- AUDIO_PODF ----....
To keep them safe, we here have to merge them into one gate clock and limit
their rates and parent identical:
<---- SPDIF_PODF ----....
/
SPDIF, AUDIO <-- gate1
\
<---- AUDIO_PODF ----....
[ The only disadvantage of this modification is that we can not separately
set a different clock rates and clock sources to SPDIF and AUDIO clock. ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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This patch sets a default clock 24.576MHz for ESAI clock and swtich the
source of external AUDIO clock from pll4 to pll3 since 24.0Mhz would be
more likely recommanded than 24.576MHz to WM8962 audio codec.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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There's one clock for SAI memory access missing in the clock tree. Thus add it.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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correct csi parent clock
Signed-off-by: Robby Cai <R63905@freescale.com>
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-Designed team confirmed GC400T is designed to run 720M.
-Update the clock source for GC400T.
Signed-off-by: Loren HUANG <b02279@freescale.com>
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According to imx6sx RM, there are three clock providers for ASRC:
Module clock Clock root Gate
asrck_clock_d spdif0_clk_root N/A
ipg_clk ahb_clk_root asrc_clk_enable
mem_clk ahb_clk_root asrc_clk_enable
while the current clock tree describes a clock named 'ASRC' that only
describes the asrc_clk_enable function.
Thus this patch first adds the other missing clocks to ASRC.
[ Since we don't have the gate for asrck_clock_d, we can pass spdif0_clk
to ASRC in the devicetree directly. ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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- add mandatory pcie related clks in imx6sx clks tree
- add pcie dts in imx6sx dts
- add pcie kconfig option in imx6sx soc config
- add pcie regulate into dts
Signed-off-by: Richard Zhu <r65037@freescale.com>
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If usbphy is enabled, we need to enable usbphy dump clock, it is
the requirement from IC engineer, it is used to guarantee some
RTL operation correctness without software operation.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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We currently has asrc_* clocks in the imx6sx clock tree while actually,
according to the Reference Manual, all of them should be named after the
audio_clk that controls the external MCLK output from MCLK pad of AUDMUX.
Thus fix it along with its gate clock missing in the current clock tree.
Meanwhile, this patch also configures a default clock rate for it -- 24MHz.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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The clock for qspi may be different when different NOR flashes are connected
to the board.
So the IMX6SX_CLK_QSPI1_SEL/IMX6SX_CLK_QSPI2_SEL should have the re-parent
capability.
This patch adds a new helper to register the clock which needs the
re-parent capability.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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The default parent of can_sel clock is invalid, need manually set it.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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- correct LCDIF pixel clock's parent selection
- correct LCDIF PODF clock's parent
- Set LCDIF1_PRE_SEL clock parent to PLL5_VIDEO, and set LCDIF1_SEL clock's
parent to LCDIF1_PODF. They are set for pixel clock.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Robby Cai <R63905@freescale.com>
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After enet bootup, enet disable all clock to save power causes
system hang, so there had workaround to enable enet clock gate.
Now the issue is fixed, remove the workaround.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add i.mx6sx enet clk support:
- Add enet2 refrence clock.
- Add PTP clock.
- Set enet system AHB clock to 200Mh.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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It adds initial MSL support for i.mx6sx, including below features:
1. add cpu type check;
2. add system timer support;
3. add clock tree support;
4. add machine layer init support;
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Acked-by: Jason Liu
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