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Introduced new imx clk APIs like imx_clk_divider2 which has flag
CLK_SET_PARENT_ON for imx7d.
PLL/PFDs does not need this flag.
Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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The A7 core clock can't be gated and when changing the A7 core clock rate
dynamically, if the clks on the A7 core path with SET_RATE_GATE flag set,
it will fail. So the the SET_RATE_GATE need not be set.
Signed-off-by: Bai Ping <b51503@freescale.com>
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when kernel command line has "uart_from_osc" defined, set uart1
parent clock to OSC for low power case.
The patch also abstract the kernel parameter for IMX common to
reduce the redundant code. But for i.MX6SL patform, the origin
kernel parameter is uart_at_4M, now is changed to uart_from_osc.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add i.MX7D clk tree support.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
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This reverts commit 8cc908a0168afb677b5de6405579b681b6f595db.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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According to the hardware design, when changing the arm_podf divider,
make sure the pll1 has clk output. If the pll1 output is disabled before
changing the arm_podf, enbale and bypass the pll1 to make sure the
arm_podf can be successfully changed.
Signed-off-by: Bai Ping <b51503@freescale.com>
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As A9 and M4 share many resources on i.MX6SX, especially for
clk and power related resource, so we need to handle the hardware
conflict between these two cores, there are two cases that we
need to consider currently:
clk management: for every clk node, only when both A9 and
M4 do NOT need it, then we can disable it from hardware;
Here we use MU and hardware SEMA4 to achieve our goal, MU is
for communiation between A9 and M4, SEMA4 is to protect the
shared memory.
For clk management, we use shared memory to maintain the clk
status for both A9 and M4 side, and this shared memory is
protected by hardware SEMA4, A9 and M4 will maintain their
own clk tree info in their SW environment, and get other
CORE's clk tree info from shared memory to decide whether
to perform a hardware setting change when they plan to.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add busfreq node in the dtsi file and modified the source code
to support imx6sl to enter low busfreq mode.
As the clk tree of imx6sl on 3.14 branch different with imx6q,
imx6sx, etc. So the busfreq change flow need some additional
code. Especially, after change the bus frequency to 24MHz, the
clock parent-child relationship need one more step to update.
Before change to 24MHz low bus mode, the clock tree between the
OSC and MMDC as below:
OSC
\__pll2_bypass_src
\__pll2
\__pll2_bypass
\_pll2_bus
\_..... mmdc
After change to 24MHz low bus mode, we bypass the pll2 in asm code, so
the correct clock tree as below:
OSC
\_pll2_bypass_src
\_pll2_bypass
\_pll2_bus
\_ .... mmdc
So the parent of pll2_bypass clock need to be set to pll2_bypass_src after
entering 24MHz mode, and set to pll2 after exiting 24MHz to reflect the correct
parent-child relationship in kernel.
Changing dev_dbg to printk to ease the debug of busfreq driver, print the busfreq
change information as needed.
Signed-off-by: Bai Ping <b51503@freescale.com>
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change procedure.
Recent checks added to the clock code prints warning during ddr frequency change procedure.
Hence the clock rates printed by clk_summary after ddr freq change are incorrect.
This patch fixes the issue by:
1. Removing CLK_SET_RATE_GATE for ocram_clk since it has a busy bit to be checked when
the ocram_podf is changed.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
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Those system bus related mux only can be switched by busfreq driver,
and in busfreq asm code, it already follow the flow that hardware design
require, so no need to do flow check for these clk mux:
i.MX6Q/DL: periph_clk2_sel and pre_periph_clk_sel;
i.MX6SL: periph_clk2_sel, pre_periph_clk_sel,
periph2_clk2_sel and pre_periph2_clk_sel
i.MX6SX: periph_clk2_sel, pre_periph_clk_sel,
periph2_clk2_sel and pre_periph2_clk_sel.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Without flag CLK_SET_RATE_NO_REPARENT, during clk_set_rate call, clock
framework will spontaneously switch parent if there is another parent
clock which can provide a better rate. Such implicit clock reparent
sometimes results in unexpected clock tree topology change. Also, with
flag CLK_SET_PARENT_GATE in place, the clk_set_rate() can fail due to
this spontaneous clock switch. So let's stop clock framework from doing
this spontaneous reparent by adding flag CLK_SET_RATE_NO_REPARENT for
mux clocks.
While at it, adds the missing CLK_SET_PARENT_GATE flag for the fixup mux
clock also.
shawn.guo: cherry-pick commit f99c1687c820 from imx_3.10.y
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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This is a forward porting of commit 580f8c84ae81 (ENGR00318063-11: ARM:
imx6: add return check for clock calls) from imx_3.10.y to imx_3.14.y.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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A recent QSPI boot failure (5% possibility) on i.MX6SX reminds us that
the peripheral clocks are still missing the check, rate cannot be
changed when the clock is enabled due to the glitchy multiplexers.
Commit a63839445ad3 (ENGR00325423: ARM: imx: pllv3 can only be
configured when it's powered off) adds the check for PLL clocks but
misses the peripheral clocks. The patch uses the help from clock
framework to check the condition with flag CLK_SET_RATE_GATE.
We adds flag CLK_SET_RATE_GATE for i.MX gate and divider clocks on
which the client drivers usually make clk_set_rate() call, so that the
call will fail when clock is still on instead of standing the risk of
running into glitch issue.
shawn.guo: cherry-pick commit 6487168bc783 from imx_3.10.y
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The mux clocks found on imx6 SoCs are all glitchy ones except
pll1_sw_clk_sel, axi_sel, periph_clk_sel and periph2_clk_sel. When
switching parent clock of a glitchy mux without gating, a glitch could
be generated and propagated into the downstream divider, and hence locks
up the divider and results in no clock output.
To avoid the situation, the parent switching should happen only when
the clock is gated. Add CLK_SET_PARENT_GATE flag for i.MX mux clocks,
so that clock core will make that check during clk_set_parent() call.
Since glitchless clocks do not need this flag, we create
imx_clk_mux_glitchless() without this flag for them. The periph_clk_sel
and periph2_clk_sel are registered by imx_clk_busy_mux() which does not
set this flag anyway, so they need no change.
shawn.guo: cherry-pick commit 10bae51219b3 from imx_3.10.y
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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There are a couple of gate clocks are mutually exclusive on i.MX6, i.e.
LVDSCLK1_IBEN and LVDSCLK1_OBEN. They cannot be enabled simultaneously.
This patches adds an exclusive gate clock type specifically for such
case. The clock driver will need to call imx_clk_gate_exclusive() to
register a gate clock with parameter exclusive_mask indicating the mask
of gate bits which are mutually exclusive to this gate clock.
Right now, it only handles the exclusive gate clocks which are defined
in a single hardware register, which is the case we're running into
today. But it can be extended to handle exclusive gate clocks defined
in different registers later if needed.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
(cherry-picked from commit fa5253d0d8ea0f753bf2e6e066eca0b9bfe981e9)
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The clocks for Quadspi controller may be different when different
NOR flashes are connected to the board.
But the CLK_SET_RATE_NO_REPARENT flag in the current imx_clk_mux_flags
makes the clock do not have the re-parent capability.
This patch removes the CLK_SET_RATE_NO_REPARENT for imx_clk_mux_flags.
It makes the Quadspi happy.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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It's quite common on i.MX that one gate bit controls the gating of
multiple clocks, i.e. this is a shared gate. The patch adds the
function imx_clk_gate2_shared() for such case. The clocks controlled
by the same gate bits should call this function with a pointer to a
single share count variable, so that the gate bits will only be
operated on the first enabling and the last disabling of these shared
gate clocks.
Thanks to Gerhard Sittig <gsi@denx.de> for this idea.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
[shawn.guo: cherry-pick commit f9f28cdf2167 from upstream]
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Pull clock framework changes from Michael Turquette:
"The common clk framework changes for 3.12 are dominated by clock
driver patches, both new drivers and fixes to existing. A high
percentage of these are for Samsung platforms like Exynos. Core
framework fixes and some new features like automagical clock
re-parenting round out the patches"
* tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits)
clk: only call get_parent if there is one
clk: samsung: exynos5250: Simplify registration of PLL rate tables
clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
clk: samsung: exynos4: Register PLL rate tables for Exynos4210
clk: samsung: exynos4: Reorder registration of mout_vpllsrc
clk: samsung: pll: Add support for rate configuration of PLL46xx
clk: samsung: pll: Use new registration method for PLL46xx
clk: samsung: pll: Add support for rate configuration of PLL45xx
clk: samsung: pll: Use new registration method for PLL45xx
clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
clk: samsung: exynos4: Remove checks for DT node
clk: samsung: exynos4: Remove unused static clkdev aliases
clk: samsung: Modify _get_rate() helper to use __clk_lookup()
clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
clocksource: samsung_pwm_timer: Get clock from device tree
ARM: dts: exynos4: Specify PWM clocks in PWM node
pwm: samsung: Update DT bindings documentation to cover clocks
clk: Move symbol export to proper location
clk: fix new_parent dereference before null check
clk: wm831x: Initialise wm831x pointer on init
...
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Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
being reparented during clk_set_rate.
To avoid breaking existing platforms, all callers of clk_register_mux()
are adjusted to pass the new flag. Platform maintainers are encouraged
to remove the flag if they wish to allow mux reparenting on set_rate.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Andrew Chew <achew@nvidia.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: linux-tegra@vger.kernel.org
Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com> [tegra]
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi]
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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All the clocks controlled by the register 'CCM Serial Clock
Multiplexer Register 1' should be fixup clocks. This patch
changes those clocks from basic multiplexer or divider clocks
to fixup clocks.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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One register may have several fields to control some clocks. It
is possible that the read/write values of some fields may map to
different real functional values, so writing to the other fields
in the same register may break a working clock tree. A real case
is the aclk_podf field in the register 'CCM Serial Clock Multiplexer
Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook
for multiplexer clock which is called before writing a value to
clock registers to support this kind of multiplexer clocks.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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One register may have several fields to control some clocks. It
is possible that the read/write values of some fields may map to
different real functional values, so writing to the other fields
in the same register may break a working clock tree. A real case
is the aclk_podf field in the register 'CCM Serial Clock Multiplexer
Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook
for divider clock which is called before writing a value to clock
registers to support this kind of divider clocks.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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MLB PLL should be handled internally in MLB driver,
so remove it from pllv3.
Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Currently clock providers defined in the DT are not registered
on i.MX5 platforms since of_clk_init() is not called.
This is not a problem for the SOC's own clocks, which are registered
in code, but prevents the DT being used to define clocks for external
hardware.
Fix this by calling of_clk_init() and actually using the DT to obtain
the 4 SOC fixed clocks.
These are already defined in the DT but were previously just used to
manually obtain the rate.
Fall back to the old scheme for non DT platforms.
Since the same method may be useful for other i.MX platforms
implement the imx_obtain_fixed_clock() function in common code.
Actually changing other i.MX platforms to use this should be done
later by someone with access to the appropriate hardware.
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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The default is for dividers to set CLK_SET_PARENT_RATE and for muxes to
not set that flag. In the LDB clock tree, we need the opposite, so add
functions to create divider and mux clocks with configurable flags.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Now that the additional enable bits in the enet PLL are handled
as gates, the gate_mask is identical for all plls. Remove the
gate_mask from the code and use the BM_PLL_ENABLE bit for
enabling/disabling the PLL.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
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This also removes mach/clock.h along the way
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This gate consists of two bits:
0b00: clk disabled
0b01: clk enabled in run mode and disabled in sleep mode
0b11: clk enabled
Currently only disabled and enabled are supported. As it's unlikely
that we find something like this in another SoC create a i.MX specific
clk helper for this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This PLL is found on i.MX6 SoCs
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This PLL is found on i.MX51 and i.MX53
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The pllv1 is found on i.MX1, i.M25, i.MX27, i.MX31 and i.MX35.
Currently only reading the rate is supported.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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- Add necessary #ifdefs for CONFIG_COMMON_CLOCK
- Add a global spinlock to protect the CCM registers
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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