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The vendor tree does imx7 PGC management through regulator notifiers
while upstream implemented the same features using power domains. These
two drivers have entirely different interfaces with higher-level IP
blocks.
Resolve this conflict by moving the old code to drivers/soc and
supporting both power-domain and regulator interfaces. This effectively
merges the two drivers and is similar to how imx6sx implements both
power domains and a regulator notifier for pcie specifically.
Supporting both interfaces allows consumes to switch one-by-one, for
example by having PCI work with a power-domains reference while usb hsic
still uses the regulator enable/disable interface.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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The power domain code shares the same node and will not probe if irqchip
probes first and marks the node with OF_POPULATED.
Clearing the OF_POPULATED flag is also done in imx_gpc_init for imx6 and
imx_gpcv2_irqchip_init implemented by upstream.
In imx_4.9.y this was solved in a different way by adding a second pgc
node, see commit fab513930e78 ("MLK-14280: gpc: gpc driver not probed").
Solving the problem by clearing OF_POPULATED allows using the upstream
PGC driver without hacks.
Having two irqchip implementations with same name seems to work fine
with the mach-imx variant taking precedence.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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Enable memory power down for i.MX7D TO1.1 to save power, TO1.0
has issue of entering DSM by mistake, so it is disabled as a
solution, now that this issue is fixed on TO1.1, enable it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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For low power idle with ARM power gated, per hardware requirement,
there must be no interrupt coming during the power down
process of ARM core, so RBC counter is enabled to hold interrupts
and GIC must be disabled at the moment;
The hardware design team recommends ~240us is required during ARM
core power down, so we update the RBC counter value to 8(~240us);
Update GPC SCU and CPU power up/down timing according to design
team's recommendation.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Design team recommend to put SCU/C0/C1 in same power up slot
to avoid reset timing issue of debug mode, adjust the power
up slot and timing per their requirement.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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When only single core online for i.MX7D, the secondary core wfi
flag should be set to make sure low power idle can be entered when
last core enters wfi. Otherwise, DDR/CCM/ANATOP will NOT enter
low power mode as the secondary core wfi flag is always clear;
Make sure the last power up slot do the ack for single core case.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Since upstream removed cpu hotplug notifiers skip this part.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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1.8v of imx7d pcie phy, should be turned on after
the 1p0d(1.0v) of pcie phy is turned on.
And turned off before the 1p0d(1.0v) of pcie phy
is turned off
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
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In this notifier, we can power on/off the two LDO's which are needed
for USB HSIC.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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When A7 platform is in low power mode while M4 is NOT,
M4 should be able to send message to wake up A7, so
MU must be always as wake up source.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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1. Per design requirement, EXSC for PCIe will need clock to recover RDC
setting on resume when M/F mix is off, so we need to enable PCIe
LPCG before entering DSM.
2. As M4 clock is disabled in low power mode, after exit from DSM, A7
needs to restore TCM for M4, but without M4 clock, this operation
never success, so we enable A7 wakeup sources for M4 as well during
DSM, after exit DSM, M4's original wakeup sources will be restored.
Signed-off-by: Anson Huang <Anson.Huang@freescale.com>
(cherry picked from commit 847db79957d25545c762670eb1bc003f34cb2592)
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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change the slots to persistent to be congruent with
M4 image. Also change so that slots do read/modify/write
so that M4 settings are not overwritten.
Signed-off-by: Teo Hall <teo.hall@freescale.com>
(cherry picked from commit eae33480b615c1586248a761ef3c6bcd9e0c59af)
Conflicts:
arch/arm/mach-imx/gpcv2.c
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The GPC setting should be modified using the read-modify-update flow.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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SCU PGC register is different from others, it contains
other timing settings, so we can NOT just program 0/1
to disable/enable SCU power gating, but need to only
program bit 0, correct it for all modules' PGC settings.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Redo necessary gpcv2 initialization after resume from
LPSR mode, as its state is lost in lpsr mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
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- For PCIe module on i.mx7d, some GPC operations would
be mandatory required when PCIe PHY is powered on/off.
So we need update gpc driver for the new requirements.
We implement it by regulator notify framwork in gpcv2
driver.
NOTE:
make sure gpc driver is ready before PCIe driver is probed.
Otherwise, cause system hang during PCIe driver probe,
because the notify NOT installed ready and the gpc will
NOT power on PCIe.
- config the imx7d pcie
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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We should use hwirq instead of logic number at gpc driver, otherwise,
it may override other global memory due to write out of boundary
for array, eg: below oops may kernel at imx7d sdb board during suspend/
resume test:
INFO: rcu_preempt detected stalls on CPUs/tasks:
1: (2 GPs behind) idle=b25/140000000000000/0 softirq=1951/1957 fqs=0
(detected by 0, t=2102 jiffies, g=847, c=846, q=4)
Task dump for CPU 1:
swapper/1 R running 6088 0 1 0x00000000
[<8089f4e4>] (__schedule) from [<8089f908>] (schedule+0x4c/0xa4)
[<8089f908>] (schedule) from [<80011514>] (arch_cpu_idle_dead+0x18/0x1c)
[<80011514>] (arch_cpu_idle_dead) from [<8006e3d8>] (cpu_startup_entry+0x2e0/0x450)
[<8006e3d8>] (cpu_startup_entry) from [<80017200>] (secondary_start_kernel+0x13c/0x15c)
[<80017200>] (secondary_start_kernel) from [<800095ac>] (__enable_mmu+0x0/0x14)
rcu_preempt kthread starved for 2102 jiffies!
NMI watchdog: BUG: soft lockup - CPU#0 stuck for 22s! [rtcwakeup.out:735]
Modules linked in: evbug
CPU: 0 PID: 735 Comm: rtcwakeup.out Tainted: G W 4.1.4-00701-g32bb3ba-dirty #370
Hardware name: Freescale i.MX7 Dual (Device Tree)
task: a8920a00 ti: a99bc000 task.ti: a99bc000
PC is at _raw_spin_lock+0x4c/0x60
LR is at get_parent_ip+0x14/0x30
pc : [<808a2e74>] lr : [<8005c080>] psr: 80000013
sp : a99bdcd8 ip : a99bdca8 fp : a99bdcec
r10: 80d4455c r9 : 00008070 r8 : 00000010
r7 : 00000000 r6 : 00000000 r5 : 00000001 r4 : 80e09934
r3 : 00000001 r2 : 00000000 r1 : 00000000 r0 : 00000000
Flags: Nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control: 10c5387d Table: a9f0006a DAC: 00000015
CPU: 0 PID: 735 Comm: rtcwakeup.out Tainted: G W 4.1.4-00701-g32bb3ba-dirty #370
Hardware name: Freescale i.MX7 Dual (Device Tree)
[<80019258>] (unwind_backtrace) from [<80014948>] (show_stack+0x20/0x24)
[<80014948>] (show_stack) from [<8089b490>] (dump_stack+0x8c/0xcc)
[<8089b490>] (dump_stack) from [<80011714>] (show_regs+0x1c/0x20)
[<80011714>] (show_regs) from [<800af83c>] (watchdog_timer_fn+0x290/0x2fc)
[<800af83c>] (watchdog_timer_fn) from [<8008c0a8>] (__run_hrtimer+0x90/0x294)
[<8008c0a8>] (__run_hrtimer) from [<8008cd94>] (hrtimer_interrupt+0x11c/0x2ac)
[<8008cd94>] (hrtimer_interrupt) from [<80618a4c>] (arch_timer_handler_phys+0x40/0x48)
[<80618a4c>] (arch_timer_handler_phys) from [<8007ca24>] (handle_percpu_devid_irq+0xac/0x1d0)
[<8007ca24>] (handle_percpu_devid_irq) from [<80078334>] (generic_handle_irq+0x3c/0x4c)
[<80078334>] (generic_handle_irq) from [<80078660>] (__handle_domain_irq+0x8c/0xfc)
[<80078660>] (__handle_domain_irq) from [<800094e4>] (gic_handle_irq+0x34/0x6c)
[<800094e4>] (gic_handle_irq) from [<80015500>] (__irq_svc+0x40/0x74)
Exception stack(0xa99bdc90 to 0xa99bdcd8)
dc80: 00000000 00000000 00000000 00000001
dca0: 80e09934 00000001 00000000 00000000 00000010 00008070 80d4455c a99bdcec
dcc0: a99bdca8 a99bdcd8 8005c080 808a2e74 80000013 ffffffff
[<80015500>] (__irq_svc) from [<808a2e74>] (_raw_spin_lock+0x4c/0x60)
[<808a2e74>] (_raw_spin_lock) from [<8002ac14>] (imx_enable_cpu+0x34/0xc8)
[<8002ac14>] (imx_enable_cpu) from [<8002b548>] (imx_cpu_kill+0x60/0x94)
[<8002b548>] (imx_cpu_kill) from [<80017090>] (__cpu_die+0x60/0x94)
[<80017090>] (__cpu_die) from [<808959bc>] (_cpu_down+0x1e4/0x2fc)
[<808959bc>] (_cpu_down) from [<80036f7c>] (disable_nonboot_cpus+0xd0/0x264)
[<80036f7c>] (disable_nonboot_cpus) from [<80073984>] (suspend_devices_and_enter+0x344/0x910)
[<80073984>] (suspend_devices_and_enter) from [<8007433c>] (pm_suspend+0x3ec/0x6e4)
[<8007433c>] (pm_suspend) from [<80072754>] (state_store+0x7c/0xcc)
[<80072754>] (state_store) from [<803455e4>] (kobj_attr_store+0x1c/0x28)
[<803455e4>] (kobj_attr_store) from [<8019f670>] (sysfs_kf_write+0x54/0x58)
[<8019f670>] (sysfs_kf_write) from [<8019ea40>] (kernfs_fop_write+0xc8/0x1ac)
[<8019ea40>] (kernfs_fop_write) from [<8013285c>] (__vfs_write+0x34/0xe8)
[<8013285c>] (__vfs_write) from [<801330cc>] (vfs_write+0xa0/0x174)
[<801330cc>] (vfs_write) from [<80133970>] (SyS_write+0x54/0xb0)
[<80133970>] (SyS_write) from [<800108c0>] (ret_fast_syscall+0x0/0x3c)
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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For SW power up/down mipi phy in GPC, below flow should
be executed:
1. map mipi phy to A7 domain;
2. enable mipi phy PGC bit if it is a disable operation;
3. do software power up/down request in GPC;
4. wait for the software request bit clear.
Previous flow is incorrect, as it miss #4 step, correct it.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 707ed61de83e7cc1c7d7b15cc8a1c00bea0bc8d1)
Conflicts:
arch/arm/mach-imx/gpcv2.c
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Add mipi phy regulator notify callback to power on or power off this
phy along with the regulator enable/disable called. This will be used
by mipi dsi/csi later.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
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Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>
(cherry picked from commit cfb19ed8cf5ae2bf1a3277f257ad20eb14892de5)
[Leonard: cherry picked so maybe it boots now?]
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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Add i.MX7D suspend/resume support, including standby
and mem mode support, mega/fast mix off and DDR
retention support.
Signed-off-by: Anson Huang <b20788@freescale.com>
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