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The double MU count operations should be only done when changing the
MMDC frequency from 400MHz to a low frequency(100MHz or 24MHz).
Otherwise, the MU count may overflow and lead to system hang/panic issue.
This is basically a porting of 4d09bf110b878a6f720ee9d19c8b64ceace95fbe
to imx6dq lppdr2.
Also a member "freq" has been added to the mmdc_settings_info structure
to store the current ddr frequency on iram settings to be able to execute
the double MU count, only on 400MHz mode and bypass the operation
otherwise within the update freq routine.
Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
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Flush and disable L1 before disabling L2, to let data to be coherent.
Flushing L1 pushes everyhting to L2. L2 is sync later, but it can still
have dirty lines.
Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
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The timing settings for 100MHz are almost the same as the ones for
400MHz except for the MMDCx_MISC[RALAT] parameter which needs to be
set to 2 cycles.
For the 100MHz case the restoration of the mmdc setting should be performed
in 2 steps: restore the mmdc setting and then overwrite the RALAT setting
for 2 cycles.
A decision code within the "mmdc_clk_lower_equal_100MHz" macro is added
to go to the "equal to 100MHz" or to the "lower to 100MHz" case
Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
Signed-off-by: Alejandro Lozano <alejandro.lozano@nxp.com>
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Setting the Read Additional Latency (RALAT) to 2 cycles,
MMDCx_MDMISC[RALAT] = 2, is needed for 24MHz operation point.
Currently this is set within the "set_timings_below_100MHz_operation"
macro, which is use for the 24MHz case.
In order to provide a generic way for setting RALAT=2 the code
is wrapped in this new macro: "set_mmdc_misc_ralat_2_cycles", so
other set points (besides the below 100MHz case) can reuse this code.
As an example, for 100Mhz operation the RALAT should be set to 2 cycles,
however, the rest of the MMDCFG parameter are not the same as in the
"below_100MHz" case. So, this macro can be reused for its RALAT part.
Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
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Two macros are renamed:
1) set_timings_above_100MHz_operation as restore_mmdc_settings_info
2) mmdc_clk_lower_100MHz as mmdc_clk_lower_equal_100MHz
For (1) the operation is generic to several cases and not just related
(at least on a semantic way) with the operations "above" 100MHz
Renamed as restore_mmdc_settings_info the macro can be reused for the
other cases like equal to 100MHz and possibly other intermediate
operation points.
For (2), the macro is renamed as mmdc_clk_lower_equal_100MHz to reflect
that this macro handles both the "lower than 100 MHz" case and the
"equal to 100MHz" case.
Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
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Fix switch_to_100Mhz miss to store updated podf dividers
for system clocks running at 100Mhz (audio mode)
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
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Simplify system root clock sources, only use pll2_pfd2 and osc
for system clocks, when busfreq request high bus mode or audio bus
mode only update dividers to achieve operating frequencies from
same source (pll2_pfd2).
Bus freq mode (400M) (100M) (24Mhz)
mmdc_ch0_clk_root @396MHz @99MHz @24Mhz
axi_clk_root @198MHz @49.5MHz @24Mhz
ahb_clk_root @132MHz @49.5Mhz @24Mhz
ipg_clk_root @66MHz @24.75Mhz @12Mhz
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
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Fix Audio frequency operation mode (100Mhz), wrong branch
condition was causing to switch to high speed timings settings
if (freq mode <= 100Mhz) use low speed timings settings
On Audio freq mode request
1. Set timings to operate on low speed
2. Switch mmdc clock root to 100Mhz
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
(cherry-picked from commit 79756d9defae46b67cd37807b859b52e63b18496)
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On low frequency operation (freq <= 100Mhz) set self-refresh exit
to next valid command delay to 23 clock cycles (MMDC_MCFG0[tXS] = 0x16)
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
(cherry-picked from commit b480c0a99fe722017e1ad04c1de16739c1467e0a)
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Add support for saving initial boot mmdc timing settings,
restore timming settings when switching from low to high
lpddr2 ddr frequency.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
(Cherry picked from commit 6787b0fea9eb1ba5cc21e2faf232c3e7d80ac028)
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Add 100Mhz (HIGH_AUDIO_CLK) bus frequency support for imx6q lpddr2 targets
On HIGH_AUDIO_CLK busfreq request source dram mmdc clock root from
pll2_pfd2_div_2 to generate 100Mhz operation frequency.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
(cherry-picked from commit 5bc118112b36b72ed6b1e75a3760c371b486abec)
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Add imx6q lpddr2 busfreq support for single channel memory
types, perform ddr frequency scaling taking into account if
ddr uses single or dual channel mode by checking
MMDC0_MDMISC[LPDDR2_2CH] state.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add busfreq support for imx6q lpddr2 pop target platform
DDR scaling support for low bus frequency and high bus
frequency mode (24Mhz/400Mhz)
Update Copyrigth year info
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 91cff834d4f5d065fe8e7e60c1c1799f00990654)
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