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2017-11-27MLK-14409-01 ARM: imx: Add speed grading fuse check for 900MHz on i.mx6ullBai Ping
According to the latest datasheet(Rev.1,02/2017), when the internal LDO is enabled, the ARM core can run at 900MHz. We need to check the speed grading fuse to determine the max ARM core frequency. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit cc0edd14c5fc3b5590302572687b08f80563c683) (cherry picked from commit c0821bb630b5a993a7cb8405f228f8bbd9e0bef7)
2017-10-02ARM: imx: clk: enable OCOTP clock by defaultStefan Agner
For some reason USDHC and USB access crashes the kernel if the OCOTP clock is not enabled. It seems not to be software related since there is no direct access from the USDHC/Chipidea USB driver to the OCOTP IP. It might be that the hardware checks the fuses to determine if the particular SoC is supposed to let user access a certain peripheral... Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2017-10-02imx: Fix 'Expose SoC unique ID' for newer i.MX6Max Krummenacher
i.MX6 SL/UL/ULL use a different node in the device tree for with ocotp. So change to the relevant compatible string for these SoCs. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
2017-09-27Merge remote-tracking branch 'fslc/4.1-2.0.x-imx' into toradex_4.1-2.0.x-imxMax Krummenacher
2017-07-27busfreq-imx: only use existing global variablesMax Krummenacher
The struct arm_reg and soc_reg are declared in by a extern statement in include/linux/busfreq-imx.h. However they are only declared when imx6-cpufreq.c is compiled and linked. Qualify the use of arm_reg and soc_reg with the relevant config option and change KConfig to switch that option on for the SoCs which use it. This fixes the following build issue when building for i.MX 7 with option ARM_IMX6Q_CPUFREQ not set: arch/arm/mach-imx/built-in.o: In function `imx6ull_lower_cpu_rate': platform-imx-dma.c:(.text+0x5514): undefined reference to `arm_reg' platform-imx-dma.c:(.text+0x551c): undefined reference to `arm_reg' platform-imx-dma.c:(.text+0x553c): undefined reference to `soc_reg' platform-imx-dma.c:(.text+0x5544): undefined reference to `soc_reg' platform-imx-dma.c:(.text+0x5598): undefined reference to `arm_reg' platform-imx-dma.c:(.text+0x55a0): undefined reference to `arm_reg' platform-imx-dma.c:(.text+0x55ac): undefined reference to `soc_reg' platform-imx-dma.c:(.text+0x55b4): undefined reference to `soc_reg' platform-imx-dma.c:(.text+0x55c8): undefined reference to `soc_reg' platform-imx-dma.c:(.text+0x55d0): undefined reference to `soc_reg' platform-imx-dma.c:(.text+0x55f0): undefined reference to `arm_reg' platform-imx-dma.c:(.text+0x55f8): undefined reference to `arm_reg' Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
2017-06-19imx: fix errors when CONFIG_SOC_IMX6SLL is not definedAlejandro Mery
I'm not exactly sure how to properly fix the cpuidle part as the whole file seems to assume all IMX* are enabled so this is mostly a "bug-report" instead of a proper patch arch/arm/mach-imx/built-in.o: In function `init_mmdc_lpddr2_settings': platform-imx-dma.c:(.text+0x9938): undefined reference to `imx6sll_lpddr2_freq_change' platform-imx-dma.c:(.text+0x993c): undefined reference to `imx6sll_lpddr2_freq_change' arch/arm/mach-imx/built-in.o: In function `imx6sl_init_late': platform-imx-dma.c:(.init.text+0xdef0): undefined reference to `imx6sll_cpuidle_init' Signed-off-by: Alejandro Mery <amery@hanoverdisplays.com>
2017-06-17Merge remote-tracking branch 'fslc/4.1-2.0.x-imx' into ↵Marcel Ziswiler
toradex_4.1-2.0.x-imx-next Conflicts: arch/arm/boot/dts/imx7d.dtsi arch/arm/mach-imx/busfreq-imx.c arch/arm/mach-imx/imx_rpmsg.c drivers/mmc/host/sdhci-esdhc-imx.c Parts moved to: arch/arm/boot/dts/imx7s.dtsi Note: This also includes NXP's latest rel_imx_4.1.15_2.1.0_ga.
2017-05-30ARM: imx: spare the first 16KiB of OCRAM_S for Cortex-M4Stefan Agner
The Cortex-M4 boot vector table is located in the OCRAM_S. When building a firmware with a complete vector table at 0x00000000 Linux overwrites the vector table with suspend information. Use the higher 16KiB for suspend related information so that we can use the lower 16KiB for the Cortex-M4 core. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2017-04-19MLK-13801-01 ARM: imx: add gpt_3m clock on imx6sllBai Ping
Add gpt_3m clock source on i.MX6SLL. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit a0c56a60ea0c0acae0bc8eea75c465eeb11826cd)
2017-04-03apalis-imx6: use stopmode for poweroffMax Krummenacher
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-04-03pm-imx6.c: fix power off by stop modeMax Krummenacher
With the 3.14.28 release of the kernel imx6_stop_mode_poweroff() does not enter stop mode. Thus the function does not switch of power but returns. This seems to be caused by the second processor which has been stopped. Set the WFI event mask for the stopped processor works around the issue. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry-picked from commit 2acff0eaece38533e85e08431e7ae9f3027c677a)
2017-04-03colibri-imx6: use stopmode for poweroffMax Krummenacher
After the system has been shutdown with PMIC_ON_REQ and VCC_BATT is supplied from a battery it will never restart either by RESET or power cycle. So use the PMIC_STBY_REQ after shutdown to switch off power rails. Conflicts: arch/arm/mach-imx/pm-imx6.c drivers/regulator/pfuze100-regulator.c (cherry-picked from commit c8b186404065c4502b485820ad4a51515924795c) (cherry-picked from commit ee4c5c4da3b32f65528a2d523ca4bce574dee3c5) Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-04-03ARM: imx: mu: let Cortex-M4 know about A7 stateStefan Agner
Introduce two new messages to let the Cortex-M4 know in what state the Linux system is in. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-04-03ARM: imx: clk: do not force clock frequency of M4Stefan Agner
Let the M4 handle the clock frequency by itself. We also don't need to take care to make sure clocks stay on, the per domain CCM clock gate control registers can be used to let the CCM know that the M4 runs on that PLL: CCM_ControlGate(CCM, ccmPllGateSysDiv2, ccmClockNeededRun); Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-04-03ARM: imx: busfreq: do not force high frequency during suspendStefan Agner
If the M4 core is running and in a low frequency mode, the A7 core should make sure that the AXI bus is left in a low frequency mode when entering suspend. So far the code unconditionally increased the high frequency variable which essentially forced the AXI bus to run in high frequency mode when entering suspend. With this change we leave the system in the state it was last in and also make sure that the last state change is actually applied before going to sleep. Typically high_bus_count ends up to be 0 because all devices requiring a high bus frequency release the bus during suspend, allowing the AXI bus to switch to 24MHz only. If the M4 is not running we don't want to artificially slow down the suspend process, hence let the bus run at full speed (it will get disabled anyway by hardware mechanism). Similar, when the M4 is running at high speed we likely need the bus capacity. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-04-03ARM: imx: busfreq: initialize M4 frequency depending boot stateStefan Agner
Set low frequency state in case M4 start with 24MHz. This makes sure that Linux is aware of the M4 state and makes sure the bus frequency is not accidentally increased during suspend (bus_freq_pm_notify). Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-04-03ARM: imx: busfreq: request bus frequency depending on M4 clockStefan Agner
Only request high bus frequency for Cortex-M4 if the Cortex-M4 is running in a high frequency mode. The Cortex-M4 clock is not directly connected with the bus frequency, however, we assume that when the M4 CPU is running at lower frequency a lower bus speed is sufficient too. The driver already has been doing this on i.MX 6SoloX, this change applies the same logic to i.MX 7. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-04-03imx: Expose SoC unique IDBhuvanchandra DV
Expose SoC unique ID read from OCOTP registers. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2017-02-22MLK-13362-2 ARM: imx: fix audio bus mode hang for imx6dq lpddr2Juan Gutierrez
The double MU count operations should be only done when changing the MMDC frequency from 400MHz to a low frequency(100MHz or 24MHz). Otherwise, the MU count may overflow and lead to system hang/panic issue. This is basically a porting of 4d09bf110b878a6f720ee9d19c8b64ceace95fbe to imx6dq lppdr2. Also a member "freq" has been added to the mmdc_settings_info structure to store the current ddr frequency on iram settings to be able to execute the double MU count, only on 400MHz mode and bypass the operation otherwise within the update freq routine. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-02-20MLK-13281-2 ARM: imx: missing brackets on phy checking for 6sxJuan Gutierrez
Adding the corresponding brackets were missing when introducing a new phy fixup function. This patch fix it. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-02-08MXSCM-240-4 arm: imx: add missing brackets to mmdc_clk checkJuan Gutierrez
Even though is not affecting the behaviour, the brackets are missing to limit this check for imx6q as was intended in first place Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-02-08MLK-13894 ARM: imx: Add low power run voltage change support on i.mx6ullBai Ping
Drop the VDD_SOC and VDD_ARM voltage to 0.9V when system runs at low power run mode. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 65517808712fcd4c5cb3b81a5d8714929957e49c)
2017-02-08MLK-13601-02 ARM: imx: Add fuse check support for imx6ullBai Ping
On i.MX6ULL, some part can run at 1GHz or 800MHz setpoint. we need to use the speed grading fuse to disable the unsupported setpoint. speed grading fuse define as below: 2'b00: Reserved; 2'b01: 528MHz; 2'b10: 792MHz; 2b'11: 996Mhz; Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-01-31MXSCM-243-2 arm: imx6q: mmdc handshake for lpddr2 2ch-mode on low-powerJuan Gutierrez
For i.mx6q systems the mmdc handshake on channel 0 is kept enabled (while channel 1 is bypassed). This is ok for lpddr2 systems operating on 1ch-mode, but not true for 2ch-mode. On this case the handshake needs to be set for both channels, otherwise a kernel panic or Oops error might be observed after resuming from suspend. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-01-31MXSCM-243-1 arm: imx: get the mmdc 2ch-mode api for lpddr2Juan Gutierrez
To configure the suspend settings for lpddr2 systems is necessary to know if mmdc is operating on 1ch-mode or 2ch-mode. Here, the imx_get_lpddr2_2ch_mode api is introduced to get this info when needed and decide accordingly. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-01-26MXSCM-240-3 arm: imx: set CLK_GET_RATE_NOCACHE flag for clock dividersJuan Gutierrez
Using the CLK_GET_RATE_NOCACHE flag on the clock dividers will allow the recalculation of the rate instead of just caching its value. For instance, this allows the mmdc clock to be properly updated, after being modified by the busfreq driver, within an iram routine by calling the clk_get_rate api. Using this flag allows to call only to the .recalc_rate functions instead of additionally call the .set_rate ones. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2017-01-26MXSCM-240-1 arm: imx: set mmdc clk rate on high audio freq on i.mx6q lpddr2Juan Gutierrez
As periph_pre_clk's parent is not changed when going to high audio frequency, the clk framework will not update its children's frequency. This cause the the mmdc_ch0_axi clk_rate does not reflect the right frequency when reading it from userspace like: cat /sys/kernel/debug/clk/mmdc_ch0_axi/clk_rate Since the mmdc_ch0_axi_podf is changed in the asm busfreq routine, then the mmdc rate needs to be updated to make sure clk tree is right, although it will not do any change to hardware. To do this the clk_get_rate api is used to update the mmdc_clk which needs to be dereferenced from the device tree. Since for other cases like ddr3, the update of the rate of the mmdc clk is not needed, the absense of this parameter (on the device tree) don't make throw an error, instead, NULL checks are used to check if the mmdc clk needs to be updated or not. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-01-20MXSCM-241-2 arm: imx: coherency issues after updating lpddr2 busfreqJuan Gutierrez
After a frequency transition, like 400MHz to 24Mhz, on i.mx6DQ SCM systems (which use lpddr2), the curr_ddr_rate variable retains its previous cached value causing the next frequency update transition to fail by following a wrong flow which results in a complete hang of the system. Issuing an L1 cache flush during the freq update routine (as in in MXSCM-241-1) and moving up the curr_ddr_rate variable before calling tge freq update alleviates the problem. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-01-20MXSCM-242-1 arm: imx6q: flush and disable L1 before L2 on lpddr2 for i.mx6qJuan Gutierrez
Flush and disable L1 before disabling L2, to let data to be coherent. Flushing L1 pushes everyhting to L2. L2 is sync later, but it can still have dirty lines. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2017-01-19MLK-13774 ARM: imx: fix lpddr2 busfreq support on i.mx6ullBai Ping
Fix busfreq support on i.MX6ULL LPDDR2 board. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 4306d7689b330d67ccf6586e365465f217d3df09)
2017-01-10ARM: imx7d: clk: add root clock for keypad portStefan Agner
The keypad port (KPP) module is clocked by the IPG root clock through clock gate CCM_CCGR170. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-01-10ARM: imx: define buffer count per VirtIO queueStefan Agner
Let RPMSG_NUM_BUFS to be the number of buffers per VirtIO queue, so that each queue (TX/RX) has 256 buffers. The change does not affect the number of buffers. But specifing per VirtIO queue aligns better with the way buffer sizes are specified on the FreeRTOS side (in platform_info.c). Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-01-10ARM: imx: remove 'unused' warningMax Krummenacher
Depending on configuration the imx_gpcv2_add_m4_wake_up_irq() stub might not be used anywhere. (e.g. when configuring for i.MX6Q only). Set unused attribute to the function so that this does not trigger a compile time warning. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-01-10clk-imx6q.c: set eth phy clock dependent on RMII/RGMIIMax Krummenacher
Evaluate the device tree to find out about the used phy mode rather than using a hardcoded value of 125MHz valid for RGMII only. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit 97f5120f2330550d500231b7bf27e7433fd31508)
2017-01-10mach-imx6q.c: handle RESET_MOCI when PCIe is disabledMax Krummenacher
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit 02110528b45ae331d89f7e7bb6a29b5494ec0be1) (cherry picked from commit 8d07763eb1d6a2a11e9b237ac94b8de43183b02e) Conflicts: arch/arm/mach-imx/mach-imx6q.c
2017-01-10mach-imx6q.c: fix typo in error msgMax Krummenacher
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit 943e92ef3b9822cd278eff806b001c14c7bebb83) (cherry picked from commit c1afc9bbac7068ec5646fff9490447eacce07c81)
2017-01-10ARM: imx: adjust vring location to be at 256MB boundaryStefan Agner
The VirtIO vring descriptors are currently at the end of the 1024MiB boundary of DDR memory 0xbfff8000. For the Colibri iMX7S and iMX7D this is outside of the addressable DDR memory. In practise VirtIO still worked because when accessing memory at out-of-bound addresses it usually just accesses memory from lower addresses (most significant address line is ignored). However, we should not rely on that behavior. Move the hardcoded vring to the end of the 256MiB boundary at 0x8fff0000. Note: This needs a Cortex-M4 firmware which uses the same hardcoded vring address. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-01-10ARM: imx7d: clk: add 240MHz sys main clock to init_onStefan Agner
Add the 240MHz sys main clock to the init on list to make sure it is kept enabled by Linux. This allows to enable/debug the M4 core after Linux started. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com> (cherry picked from commit bef7a90406b663a74aaaf06bdccc56285d9fe93c)
2017-01-10ARM: imx: fix clock for i.MX 7 when Cortex-M4 is runningStefan Agner
Commit b0149f1c7c ("MLK-11620 ARM: imx: single SOC config/compile support") ifdef'd clock functionality for SoloX only if Cortex-M4 is running. However, i.MX 7 also provides a Cortex-M4, hence the true branch in those if statements have been taken. Since the whole block was ifdef'd, the functions were rendered useless for i.MX 7. Fix this by just doing the same thing as if Cortex-M4 is not running. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com> (cherry picked from commit 7b20ca6cdb752ac4770c2c11e9500b7c1d8bc395)
2017-01-10ARM: dts: imx7d-colibri: use external Ethernet PHY clockMax Krummenacher
Add workaround for M4 NMI issue. Set the Ethernet PHY reference clock to be generated externaly from the i.MX 7 by default (Colibri i.MX 7 V1.1 sample batch) Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> (cherry picked from commit 7f9ad0ee55abbc89b433c4ff14e64eb35c831370)
2017-01-10mach-imx7d.c: use enet_out clk to decide on PHY clockMax Krummenacher
The i.MX 7 can provide a reference clock to the PHY or use a reference clock from an external circuit. If the device-tree node with compatible "fsl,imx7d-fec" has a clock named enet_out then provide the clock from the i.MX 7, if such a clock is missing use a clock provided from an external circuit. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> (cherry picked from commit 73c06d69321c45b69ffc864cbaaa7143da87d186)
2017-01-10ARM: imx: enet1: output reference clockMax Krummenacher
Enable output driver of Ethernet reference clock. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> (cherry picked from commit dab46121a94916a253d7283c8b85ea6dcfb6e628)
2016-12-21MLK-13484 ARM: imx: imx6ul: add PHY KSZ8081 new silicon revision fixup settingAndy Duan
The previous code only support i.MX6UL EVK RevA, RevB, RevC PHY KSZ8081 with fixed silicon revision. Different silicon revision may have different phy fixup init setting. i.MX6UL EVK RevC1 apdate new silicon revision PHY. After debug and tune, the revision still need the same phyfix setting. So, add Ethernet PHY KSZ8081 new silicon revision fixup setting. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> (cherry picked from commit: 15c759347681b65fa33986f0fc5687a374d9f3a1)
2016-12-19MLK-13616 ARM: imx: Add low power run voltage change support on i.MX6SLLBai Ping
On i.MX6SLL, if all PLLs is bypassed in low power run mode, we can decrease the VDD_ARM_IN and VDD_SOC_IN voltage to 0.925V to save power. a 25mV margin is added to cover IR drop and board tolerance. Add low power run voltage change support for i.MX6SLL. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 3b9da6e8b867ee59c81314d3e08af60053a5855d)
2016-12-08MXSCM-217 imx: keep weak 2p5 power up when ENET WOL wakeup is enabledJuan Gutierrez
When ENET wake up is enabled by wake-on-lan (WOL), the weak 2P5 ldo needs to keep power up even for LPDDR2 due to the ENET_PLL is feed by the weak 2p5 ldo during DSM. If the weak 2P5 ldo is power down the ENET module is power off hence it is not able to sense the WOL interrupt and trigger the system resume. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2016-11-21MLK-13497 clock: make an accurate pixel cock rate for epdc on i.mx6sllRobby Cai
change parent clock to pll3_pfd2 and calculate out a desired pixel clock rate. This patch fixed the following warning. "imx_epdc_v2_fb 20f4000.epdc: Unable to get an accurate EPDC pix clkdesired = 40000000, actual = 63529412" Signed-off-by: Robby Cai <robby.cai@nxp.com> (cherry picked from commit 76a336b931a74605caa94ca82c7b8343d604fee6)
2016-11-16MLK-13384 ARM: imx: remove ldo bypass check on imx6sllBai Ping
As on i.MX6SLL, there is no ARM LDO, the code for ARM LDO bypass check is unnecessary, remove these piece of code in i.MX6SLL low power idle. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit be3df9ec9b68574b5a319009fa6f37c105d6b771)
2016-11-16MLK-13362 ARM: imx: fix audio bus mode hang on imx6sx/ul/sllBai Ping
When MMDC runs at a low frequency, it is not recommended to perform "force measurement", the MMDC measure unit may return a wrong measurement value when running below 100MHz. Additionally, the double MU count operations should be only done when changing the MMDC frequency from 400MHz to a low frequency(100MHz or 24MHz). Otherwise, the MU count may overflow and lead to system hang issue. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 4d09bf110b878a6f720ee9d19c8b64ceace95fbe)
2016-11-16MLK-13344-05 ARM: imx: Add cpuidle support on imx6sllBai Ping
Add low power idle support on i.MX6SLL. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 26de2bb5e8ddef4f1562cc5e6001bfc0027106f0)
2016-11-16MLK-13344-04 ARM: imx: Add busfreq support on imx6sllBai Ping
Add bufreq driver support on i.MX6SLL. For i.MX6SLL, it only support LPDDR2 and LPDDR3. the DDR clock change flow is same on these two type of DDR. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 8479afb4e7c52c6de1bedefb00a7cea4320fc14d)
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