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PLL1 was enabled without incrementing the usecount, and was
thus not getting disabled under certain conditions.
This causes 2 issues:
1. Increases the power.
2. Causes crashes on MX6SL in audio mode as ARM is switched
to PLL1 assuming its in bypass when entering WAIT mode. But PLL1
is enabled and not in bypass state.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fix couple of race-conditions associated with low power IDLE code:
1. Ensure that bus freq mutex is used in the suspend/resume function
2. Ensure that the usecount of pll2 is incremented/decremented when
ARM is switched to run from PLL2_PFD_400. And PLL2 is enabled/disabled
when necessary.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Need to ensure that check for usecount in clk_set_parent
occurs within the protection of the clock mutex. Else
there is a chance that the usecount can be decremented
(and the clock disabled) after the check.
Also add back the code to maintain the correct usecount
for pll2_pfd_400.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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We can't modify the usecount of pfd 400M clock when ARM freq
is changed, as when the children of pfd 400M do clock enable/disable,
they will also modify this usecount, these two modification is
out of same lock protection. And this wrong usecount may lead to
pfd 400M or pll2 disabled accidently, and it will cause system hang!
Signed-off-by: Anson Huang <b20788@freescale.com>
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This patch sets PLL3_PFD_540M clock frequency to 540MHz
so that IPU and VPU clock can reach 270MHz.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit faf59e846f03b37c65996e58d045de8d64481283)
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Checking of the bus_freq variables and changing of the
bus/ddr frequency should be done under one mutex.
Else there is a race-condition that the variable changed
just after it was checked.
Also ensure that the bus freq is always increased before
the cpu freq is set to anything other than the lowest setpoint.
Else there is a possibility that the ARM is set to run from
PLL1 at higher frequency when bus/DDR are still at 24MHz.
This is dangerous since when system enters WAIT mode in
low bus freq state, PLL1 is set to bypass when ARM is being
sourced from it.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it
can run at 270MHz on MX6DL/S. This is required for improving
VPU performance.
Change AXI_CLK to be sourced from periph_clk just before the DDR
freq is going to be dropped to 24MHz/50MHz. Change it back
to PLL3_PFD1_540 when the DDR freq is back at 400MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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[MX6X] Fix BogoMIPS value is not correct
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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Increase VPU frequency to 352Mhz for TV box, use pll2_pfd_400M.To avoid impact
other code which assume ARM clock sourcing from pll2_pfd_400M, change cpu
setpoint of 396M to 352M. and disable bus freq adjust.
add CONFIG_MX6_VPU_352M to choose it, default is disabled.
Signed-off-by: Robin Gong <B38343@freescale.com>
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1. BUS freq's set low bus setpoint using delat work, which
didn't have mutex lock, so in some scenarios, set high bus
freq function can be called at the same time, we need to move
mutex lock into these two routine;
2. Using pm notify to make sure bus freq set to high setpoint
before supend and restore after resume.
3. Clear build warning.
Signed-off-by: Anson Huang <b20788@freescale.com>
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In order to support USB remote wake up, we should keep the PLL3 enable
and power bit all the time. We use BM_ANADIG_ANA_MISC2_CONTROL0 to control
the PLL3 power off PLL3's power when PLL3 is not used by other module.
PLL3 power design logic as below:
usb1_pll_480_ctrl_power_int=hw_anadig_usb1_pll_480_ctrl_power && ((disable_480_p
ll_n && ~hw_anadig_ana_misc2_control0 )||pwrctl_otg_wakeup || utmi_otg_suspendm)
There are two basic case:
- If USB is active and USB remote wakeup happen , Pll3 will be turn on.
- If USB is not active and no remote wakeup happen, the PLL3 will be controlled
by hw_anadig_ana_misc2_control0 bit.
Signed-off-by: make shi <b15407@freescale.com>
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System will report oops as below. To fix it we will move mx6_timer_rate to
clock.c, so that we can avoid use clk_get_sys which cause schedule after
spin_lock.
oops log:
BUG: scheduling while atomic: kinteractiveup/1403/0x00000002
Modules linked in:
(unwind_backtrace+0x0/0xfc) from [<804f05f0>] (__schedule+0x4b8/0x6b0)
(__schedule+0x4b8/0x6b0) from [<804f12ac>] (__mutex_lock_slowpath+0x138/0x208)
(__mutex_lock_slowpath+0x138/0x208) from [<804f13b4>] (mutex_lock+0x38/0x3c)
mutex_lock+0x38/0x3c) from [<803b9134>] (clk_get_sys+0x1c/0xec)
(clk_get_sys+0x1c/0xec) from [<8005f814>] (mx6_timer_rate+0x14/0x7c)
(mx6_timer_rate+0x14/0x7c) from [<80056a20>] (_clk_gpt_get_rate+0x18/0x2c)
(_clk_gpt_get_rate+0x18/0x2c) from [<8005e89c>] (clk_get_rate+0x34/0x40)
(clk_get_rate+0x34/0x40) from [<80055f3c>] (_clk_pll_enable+0xa8/0x1ec)
(_clk_pll_enable+0xa8/0x1ec) from [<80056088>] (_clk_pll1_enable+0x8/0x20)
(_clk_pll1_enable+0x8/0x20) from [<80056998>] (_clk_arm_set_rate+0x278/0x2e8)
(_clk_arm_set_rate+0x278/0x2e8) from [<8005e824>] (clk_set_rate+0x54/0x68)
(clk_set_rate+0x54/0x68) from [<80061660>] (set_cpu_freq+0xb8/0x160)
(set_cpu_freq+0xb8/0x160) from [<800618b4>] (mxc_set_target+0xf0/0x20c)
(mxc_set_target+0xf0/0x20c) from [<80372388>](__cpufreq_driver_target+0x54/0x60)
Signed-off-by: Robin Gong <b38343@freescale.com>
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1.add new cpu setpoint: replace 498Mhz with 672Mhz,and remove 198Mhz.
but now 498Mhz seems not stable enough, comment now, test enough to
add it. Rigel kept unchange now.
2.support adjusting VDDSOC/VDDPU when cpu frequency change.
Signed-off-by: Robin Gong <b38343@freescale.com>
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The original 528M setting is invalid and become 396M actually,
Change gpu3d core clock parent to 594_PFD to enable 528M setting.
Benchmark performance are improved with clock change on i.MX6DL:
Basemark2: 5.85 --> 7.66
Nenamark2: 23.7 --> 27.4
Quadrant 3d: 2186 --> 2270
Signed-off-by: Xianzhong <b07117@freescale.com>
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GPU 2D core suspend resume fail related with clock glitch
Switch GPU 2D core clock to PLL2
PLL3 has an errata TKT094231 To1.2 will fix it
Signed-off-by: Richard Liu <r66033@freescale.com>
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Add the new WAIT mode workaround added for MX6Q1.2 and MX6DLTO1.1.
A new bit is added to CCM_CGPR (bit 17). This bit needs to be
enabled for the WAIT mode fix to be active and needs to be disabled
before the system enters STOP mode with power gating enabled.
Fix WAIT mode bug when system is in low power IDLE mode:
In low power IDLE mode (AHB @ 24MHz), switch ARM to run from 24MHz
on MX6QTO1.1 and MX6DLTO1.0 chips when ARM core enters WAIT mode.
We still need to use the ARM:IPG_CLK ratio of 12:5. Since IPG_CLK
is at 12MHz, we need to run ARM below 28.8MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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HDMI output video mode is 1080p, LVDS output is XGA.
The IPU bandwidth is not enough to support the two display output
when IPU HSP clock setting to 200MHz,
increase the IPU HSP clock to 270MHz and dual display can work.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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VDOA needs OCRAM clock and DDR clock enabled when video playback,
and set bus clock high to finish work quickly.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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hdmi_clk is used to access hdmi register only, it is not a high
speed clk, no need to set high bus flag.
Signed-off-by: Anson Huang <b20788@freescale.com>
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ahash still has a scatterlist problem which cause this problem.
Thus we disable ahash feature in defconfig and wait for later patch to
fix it.
Also, we remove caam high freq flag to make bus freq run.
Signed-off-by: Terry Lv <r65388@freescale.com>
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This patch supports clko2 clock to be clko's parent clock.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 3827c82e439b6a8bbb6569a01327043251875964)
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Add debug message for wait mode to check it was enabled or not.
it will easy to get the wait mode status from this info
e.g, if wait mode is enabled, there are below info from console:
wait mode is enabled for i.MX6
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Previous flow when we change PLL1_SW_CLK from 400M
PFD to PLL1_MAIN_CLK is as below:
1. move PLL1_SW_CLK from 400M PFD to PLL1_MAIN_CLK;
2. change PLL1_MAIN_CLK's freq if necessary;
There is chance that the PLL1_MAIN_CLK freq is higher
than what we want, then after step1, system may hang as
we use low voltage to run high freq.
The correct flow should be as below:
1. make sure PLL1_MAIN_CLK is enabled;
2. make sure pLL1_MAIN_CLK freq is what we want;
3. move PLL1_SW_CLK from 400M PFD to PLL1_MAIN_CLK.
Signed-off-by: Anson Huang <b20788@freescale.com>
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As Arik TO1.0 GPT use ipg_perclk as clock source, we need to
lower it to 6M before init GPT, or the clock source freq will
be wrong if we lower the ipg_perclk after GPT time already init.
Signed-off-by: Anson Huang <b20788@freescale.com>
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As DDR freq change is by modifying CCM register directly,
we need to update the clock tree as well, or the clock
tree will be broken. Also, we need to make sure the clock
rate counting is right.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The max freq for IPU and AXI clocks is 264MHz. Hence source
IPU from mmdc_ch0 clock on MX6 to get maximum frequency.
And source AXI from periph_clk on for max freq.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Need to make sure gpt serial clock enabled on Arik TO1.0.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Ensure that the CPUFREQ driver sets the CPU to its maximum
frequency when it is suspended.
Also change the WAIT macro in clock.c to use GPT counter
for the delay instead of getnsdayoftime(). As the kernel
timekeeping driver is suspended before CPUFREQ and this
causes a dump during suspend.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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To avoid the ARM from accepting an interrupt in the dangerous
window, reduce the ARM core freq just before the sytem is
about to enter WAIT state.
Reduce the ARM freq so as to maintain 12:5 ARM_CLK to IPG
ratio. Use the ARM_PODF to drop the frequency.
In a multicore case the frequency is dropped only when all the
4 cores are going to be in WFI.
In case of single core environment, its easy to drop the ARM core
freq just before WFI since there is no need to identify the state of
the other cores.
Some other points to note:
1. If "mem_clk_on" is added to the command line, the memory clocks will
not be gated in WAIT mode. This will increase the system IDLE power.
This mode is valid only on MX6sl, MX6DQ TO1.2 and MX6DL TO1.1.
2. In case the IPG clk is too low (for ex 50MHz) and ARM is at 1GHz,
we cannot match the 12:5 ratio using ARM_PODF only. In this case,
donot clock gate the memories in WAIT mode (available on MX6SL,
MXDQ TO1.2 and MXDL TO1.1). For MXDQ TO1.1 and MX6DL TO1.0, disable
system wide WAIT entry in this case.
In STOP mode, always ensure that the memory clocks are gated, else
power impact will be significant.
WAIT mode is enabled by default with this commit.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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- Ethernet clock source name is differentiated by IP name.
FEC IP clock name is "FEC"; ENET IP clock name is "enet".
Signed-off-by: Fugang Duan <B38611@freescale.com>
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IPU_HSP clocks should NOT be sourced from MMDC clock since the
MMDC clock can be scaled.
Move the IPU_HSP clock to be sourced from PLL3_PFD_540M instead.
Also don't source AXI_CLK from periph_clk as this domain is
scaled between 528MHz, 400MHz and 24MHz. Move AXI_CLK
clock to be sourced from PLL3_PFD_540M too.
When the system needs to enter low power mode, AXI_CLK is switched
from PLL3_PFD_540M to periph_clk. And then switched back
when low power mode is exited.
The code will print a warning message if PLL3_PFD_540M is
relocked to a different frequency when IPU_HSP or axi_clk is
sourced from it.
Currently remove the support for 400Mhz DDR working point for
MX6Q since we can get IPU underruns during the DDR frequency
transitions.
The DDR freq change code needs to ensure that all bus clocks
donot exceed max frequency during the frequency transition.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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On mx6dl, set ipu2_clk's parent from pll2_pfd_400M.
On mx6q, ipu2_clk's parent from mmdc_ch0_axi_clk, and it is 264MHz by default.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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The DDR frequency needs to be at 50MHz for low power audio
playback. So added a new low power mode for audio.
Set the AHB to 25MHz, AXI to 50MHz and DDR to 50MHz in this
mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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In Rigel validatioin, the MLB sys_clock isn't using the right frequency
after boot.
In arik, the register CBCMR controls gpu2d clock, not mlb clock, mlb is
sourced from axi_clock.
But In rigel, the axi clock is lower than in mx6q, so mlb need to find a
new clock root. The gpu2d clock is then root of mlb clock in rigel.
Thus we need to add setting to support this change.
Signed-off-by: Terry Lv <r65388@freescale.com>
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change clock source explicitly by calling set_parent() function
Signed-off-by: Allen Xu <allen.xu@freescale.com>
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change CLKO source to pll4_audio_main_clk for low power
mode consideration
Signed-off-by: Gary Zhang <b13634@freescale.com>
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The idea is to get the soc silicon revision from DIGPROG register Of
ANATOP(USB_ANALOG_DIGPROG), which will make kernel code independent
with bootloader which need pass the system_rev by ATAG.
This patch also will print the chip name and revision when kernel boot
up since this information is important for customer to know.
on i.mx6q TO1.1, it will print as the following:
CPU identified as i.MX6Q, silicon rev 1.1
Signed-off-by: Jason Liu <r64343@freescale.com>
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Due to pll2_pfd_352M would be used for LVDS, change NAND clock source to
pll2_pfd_400M.
Signed-off-by: Allen Xu <allen.xu@freescale.com>
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According to ticket TKT071080, 0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1.
However, MX6DL uses mmdc_ch1 as LDB DI parent clock.
This patch corrects the LDB DI parent clock setting.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Fix the boot failure caused by:
8f0c21e06d4f7d0c7c078d6261ccd75f2a45c3ab
MX6- Add bus frequency scaling support
There is no SATA on MX6DL. Accessing SATA PHYs early in the boot
process causes the system to crash.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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This patch corrects LDB DI clock's parent clock to
be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0
according to ticket TKT071080(0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1).
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Add support for scaling the bus frequency (both DDR
and ahb_clk).
The DDR and AHB_CLK are dropped to 24MHz when all devices
that need high AHB frequency are disabled and the CORE
frequency is at the lowest setpoint.
The DDR is dropped to 400MHz for the video playback usecase.
In this mode the GPU, FEC, SATA etc are disabled.
To scale the bus frequency, its necessary that all cores
except the core that is executing the DDR frequency change
are in WFE. This is achieved by generating interrupts on
un-used interrupts (Int no 139, 144, 145 and 146).
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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In our code 3d sharder clock uses 3d core clock CCGR field as its
enable bit. That works for MX6Q. But MX6DL uses 3d sharder clock
as 2d core clock, while disable 2d core clock, it will disable 3d
core by mistake.
To fix it, remove the enable bit setting of 3d shader clock in
clock.c file.
Signed-off-by: Larry Li <b20787@freescale.com>
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When there is no NAND I/O operation, close all the reference
clock, include GPMI,BCH and APBH clock.
Signed-off-by: Allen Xu <allen.xu@freescale.com>
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Add vdoa support on i.MX6 SOC platform
Signed-off-by: Wayne Zou <b36644@freescale.com>
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* Fix build warnings
* clock.c: In function '_clk_pll1_enable':
warning: no return statement in function returning non-void
* clock.c: In function 'mx6_clocks_init':
warning: unused variable 'reg'
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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TO1.0 parts donot boot properly after the following commit:
88d3af87222b37e454acd6a8de3b0cf18180da32
MX6-Switch ARM_CLK to PLL2_400MHz when ARM freq
is below 400MHz.
Correct gpt_clk was not getting enabled. Fix by adding the
appropriate gpt_clk.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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PLL1 can be disabled whenever ARM_CLK is below 400MHz since
ARM_CLK can be sourced from PLL2_PFD_400MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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what're done:
* PCIE topology, RC should be on bus 0, EP should be on bus 1.
Root Cause: The CLASS_REV of RC CFG header, specified
by SPEC to be RO, should be set to PCI_CLASS_BRIDGE_PCIclass
* Added PCIE PWR EN and RESET
* iATU wrong configurations.
Root Cause: The outbounds excepted the CFG region0
should be removed. Otherwise, the memory ATU wouldn't
work correctly.
* CT DHCP hang
Root Cause: PLL8 is set to bypass mode when linux close fec,
and the PCIe ref clk would be broken by PLL8 bypass mode.
The parent clk of pcie ref clk is disabled by FEC, since
linux would try to disable the none-addressed NIC after DHCP.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Change _clk_clko_round_rate and ensure the clock should
be less than the input rate.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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