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In order to save power consumption, disable pcie phy
(enable IDDQ mode) in kernel initialization.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Forget submit some local change...
Signed-off-by: Robin Gong <b38343@freescale.com>
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Currently, use CONFIG_MX6_INTER_LDO_BYPASS to enable/disable LDO bypass, and
use the same macro in u-boot too. It's not very friendly ,it will be more
flexible if use dynamic configure by command line input by u-boot.
Two ways to enable LDO bypass:
1. use command line:
You can set "ldo_active=on" or "ldo_active=off" in command line to enable/
disable LDO bypass.
2. set enable_ldo_mode value in board file:
If you didn't set the param in command line, every board
will use its default value, for example, you can find below code in arch/arm/
mach-mx6/mx6q_sabresd_pmic_pfuze100.c:
static int pfuze100_init(struct mc_pfuze *pfuze)
{
....
/*use default mode(ldo bypass) if no param from cmdline*/
if (enable_ldo_mode == LDO_MODE_DEFAULT)
enable_ldo_mode = LDO_MODE_BYPASSED;
....
}
Note:
1.You should know clearly ldo bypass can be only enabled in the board
that mounted with external pmic to supply VDDARM_IN/VDDSOC_IN power rail, and
you should implement related external regulator firstly, such as:
in arch/arm/mach-mx6/board-mx6q_sabresd.c
static struct mxc_dvfs_platform_data sabresd_dvfscore_data = {
.reg_id = "VDDCORE",
.soc_id = "VDDSOC",
....
}
otherwise, you have to use internal ldo which is the default configuration.
2.one special case, if the chip is 1.2Ghz, it can't be set LDO bypass.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Before, we use "arm_freq" in command line to set 1.2G. Now we will read the
fuse bit and "arm_freq", get the mini value to be used as "arm_max_freq".And:
1. you can easily set CPU max freq on what frequency you want by cmdline.
2. if you didn't set arm_freq in cmdline, kernel will read the fuse bit
(0x021bc440) to set the right arm_max_freq.
At the same time, add 1Ghz setpoint if chip max freq is 1.2Ghz.
Signed-off-by: Robin Gong <b38343@freescale.com>
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MX6SL and MX6DL have only 128KB of IRAM. Fix the
code so the right size is passed to iram_init()
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Use the correct function to read the chip revision.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add the new WAIT mode workaround added for MX6Q1.2 and MX6DLTO1.1.
A new bit is added to CCM_CGPR (bit 17). This bit needs to be
enabled for the WAIT mode fix to be active and needs to be disabled
before the system enters STOP mode with power gating enabled.
Fix WAIT mode bug when system is in low power IDLE mode:
In low power IDLE mode (AHB @ 24MHz), switch ARM to run from 24MHz
on MX6QTO1.1 and MX6DLTO1.0 chips when ARM core enters WAIT mode.
We still need to use the ARM:IPG_CLK ratio of 12:5. Since IPG_CLK
is at 12MHz, we need to run ARM below 28.8MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add IMX_CHIP_REVISION_1_2 support for i.mx6q TO1.2
Signed-off-by: Jason Liu <r64343@freescale.com>
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set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7,
mx6q use AXI-id0 for IPU display channel, it should has
highest priority(bypass), and AXI-id1 for other IPU channel,
it has high priority.
Also, clear OCRAM_CTL bits to disable OCRAM read/write pipeline control.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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To avoid the ARM from accepting an interrupt in the dangerous
window, reduce the ARM core freq just before the sytem is
about to enter WAIT state.
Reduce the ARM freq so as to maintain 12:5 ARM_CLK to IPG
ratio. Use the ARM_PODF to drop the frequency.
In a multicore case the frequency is dropped only when all the
4 cores are going to be in WFI.
In case of single core environment, its easy to drop the ARM core
freq just before WFI since there is no need to identify the state of
the other cores.
Some other points to note:
1. If "mem_clk_on" is added to the command line, the memory clocks will
not be gated in WAIT mode. This will increase the system IDLE power.
This mode is valid only on MX6sl, MX6DQ TO1.2 and MX6DL TO1.1.
2. In case the IPG clk is too low (for ex 50MHz) and ARM is at 1GHz,
we cannot match the 12:5 ratio using ARM_PODF only. In this case,
donot clock gate the memories in WAIT mode (available on MX6SL,
MXDQ TO1.2 and MXDL TO1.1). For MXDQ TO1.1 and MX6DL TO1.0, disable
system wide WAIT entry in this case.
In STOP mode, always ensure that the memory clocks are gated, else
power impact will be significant.
WAIT mode is enabled by default with this commit.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add i.MX 6SoloLite SoC revision support
Signed-off-by: Jason Liu <r64343@freescale.com>
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IPU_HSP clocks should NOT be sourced from MMDC clock since the
MMDC clock can be scaled.
Move the IPU_HSP clock to be sourced from PLL3_PFD_540M instead.
Also don't source AXI_CLK from periph_clk as this domain is
scaled between 528MHz, 400MHz and 24MHz. Move AXI_CLK
clock to be sourced from PLL3_PFD_540M too.
When the system needs to enter low power mode, AXI_CLK is switched
from PLL3_PFD_540M to periph_clk. And then switched back
when low power mode is exited.
The code will print a warning message if PLL3_PFD_540M is
relocked to a different frequency when IPU_HSP or axi_clk is
sourced from it.
Currently remove the support for 400Mhz DDR working point for
MX6Q since we can get IPU underruns during the DDR frequency
transitions.
The DDR freq change code needs to ensure that all bus clocks
donot exceed max frequency during the frequency transition.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The idea is to get the soc silicon revision from DIGPROG register Of
ANATOP(USB_ANALOG_DIGPROG), which will make kernel code independent
with bootloader which need pass the system_rev by ATAG.
This patch also will print the chip name and revision when kernel boot
up since this information is important for customer to know.
on i.mx6q TO1.1, it will print as the following:
CPU identified as i.MX6Q, silicon rev 1.1
Signed-off-by: Jason Liu <r64343@freescale.com>
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Add support for scaling the bus frequency (both DDR
and ahb_clk).
The DDR and AHB_CLK are dropped to 24MHz when all devices
that need high AHB frequency are disabled and the CORE
frequency is at the lowest setpoint.
The DDR is dropped to 400MHz for the video playback usecase.
In this mode the GPU, FEC, SATA etc are disabled.
To scale the bus frequency, its necessary that all cores
except the core that is executing the DDR frequency change
are in WFE. This is achieved by generating interrupts on
un-used interrupts (Int no 139, 144, 145 and 146).
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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When system is going to enter WAIT mode, set PLL1 to 24MHz
so that ARM is running at 24MHz. This is a SW workaround for
the WAIT mode issue.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Added the new 1.2GHz working point.
Currently 'arm_freq=1200" should be added to commandline
for the core to run at 1.2GHz. Also ensure that the appropriate
HW board mods have been done to set VDDARM_IN at 1.425V.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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None of the workarounds implemented in SW provide a stable solution for
the WAIT mode issue.
For this release, WAIT mode is disabled by default.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fix the following build warning:
1.arch/arm/mach-mx6/cpu.c:36: warning: function declaration isn't a
prototype
2.arch/arm/mach-mx6/system.c:55: warning: function declaration isn't a
prototype
3.arch/arm/mach-mx6/board-mx6q_sabreauto.c:751: warning: unused variable
'iterations'
Signed-off-by: Anson Huang <b20788@freescale.com>
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NFS can work with WAIT mode only if the NFS use
TCPIP protoco, in order to test more features of
WAIT mode, we enable it by default and make sure
NFS is using TCPIP protocol.
Signed-off-by: Anson Huang <b20788@freescale.com>
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WAIT mode and DVFS still have some defects, we need
to disable it by default until we make them works.
Signed-off-by: Anson Huang <b20788@freescale.com>
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WAIT mode is enabled by default with this commit.
Adding "enable_wait_mode=off" to the command line will
prevent the system from entering WAIT mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Only CPU0 executes WFI followed by ISBs in uncached iRAM.
All other cores execute the regular cpu_do_idle()
This puts a restriction that all interrupts should only be routed to CPU0.
This bug should be fixed in TO1.1.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Read the silicon version stored in ROM at address ox48.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Change dvfs driver and cpufreq driver to use regulator API to set cpu voltage.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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Set the ARM LDO voltage to 1.225V to run the part at 1GHz.
Also updated the rest of the voltages based on the latest
available working points.
The boards will need to be modified for this change to work
correctly. Please ensure that the VDDARM_IN is set to 1.38V
(using the potentiometer on the ARM2 board or choosing the correct
resistors on the sabrelite boards).
Also added command line option (arm_freq=800) to set the max ARM freq.
Add:
arm_freq=1000 -> to set the max ARM freq to 1GHz
arm_freq=800 -> to set the max ARM freq to 800MHz.
Default max ARM freq is 1GHz. No other values are currently
supported. If your board is not modified, please add the command
line "arm_freq=800' to avoid failures.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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arch/arm/mach-mx6/cpu.c:39: warning:
'arm_base' defined but not used.
Signed-off-by: Anson Huang <b20788@freescale.com>
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When WAIT mode is not enabled, execute cpu_do_idle() code.
Currently WAIT mode requires the code to be run from IRAM with caches disabled.
No L2 cache access should be done for a specified period after the system exits
WAIT mode. This delay and running code from IRAM adversely affects the
SDHC performance.
Hardware team is looking into the extended delay that is required.
Till its root caused, default should be to execute cpu_do_idle() and
disable entry into WAIT mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Current warm reset is not working with MMDC_CH1 bypass
bit set, now we disable warm reset to workaround it for
the coming release. Then, wdog reset will be cold reset.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Disable SCU standby mode will prevent SOC enter
WAIT mode, so, by default, we would not enable
WAIT mode to make NFS work, to enable WAIT mode,
you should not use NFS, and pass "enable_wait_mode"
from uboot.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add DVFS-CORE support for MX6 quad/dual SOC.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Set the appropriate bit in CCM to allow ARM-CORE to enter WAIT
mode when system is idle.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add support for CPUFREQ for SMP system.
Added support for 1GHz, 800MHz, 400MHz and 160MHz.
Added support for scaling the voltage along with frequency.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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1. Copy mx6_secondary_startup to iRAM;
2. CPU0 reset CPUx, then waiting CPUx reset OK, and
clear CPUx's boot_entry;
3. CPUx reset OK, waiting CPU0 to clear its parameter;
4. All these steps done, CPUx go on boot;
Signed-off-by: Anson Huang <b20788@freescale.com>
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Enable suspend/resume feature for MX6q
echo standby > /sys/power/state -> wait mode;
echo mem > /sys/power/state -> stop mode;
Currentlu only support debug uart as wakeup source;
Signed-off-by: Anson Huang <b20788@freescale.com>
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Enable iram for vpu on mx6q.
Signed-off-by: Sammy He <r62914@freescale.com>
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MSL code for bring up MX6 sabreauto board with Single core.
Merged from testbuild:imx6_bringup branch.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Singed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: Richard Zhu <r65037@freescale.com>
Signed-off-by: Anish Trivedi <anish@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Jason Chen <b02280@freescale.com>
Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Sammy He <r62914@freescale.com>
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
Merged-by: Zeng Zhaoming <b32542@freescale.com>
Reviewed-by: Jason Liu <r64343@freescale.com>
Reviewed-by: Frank Li <Frank.Li@freescale.com>
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