| Age | Commit message (Expand) | Author |
|---|---|---|
| 2012-07-20 | ENGR00182324-4 - MX6SL MSL: Enable L2 cache as OCRAM functionality | Jason Liu |
| 2012-07-20 | ENGR00182324-2 - MX6SL MSL: Add Support for i.MX6SoloLite SoC revision | Jason Liu |
| 2012-07-20 | ENGR00179782: i.mx6: consolidate mx6q/dl_revision() support | Jason Liu |
| 2012-07-20 | ENGR00174652 i.mx6: explicitly set the LPM mode to run mode during early bootup | Jason Liu |
| 2012-07-20 | ENGR00173869-3: i.mx6: add the cpu_is_mx6dl() support | Jason Liu |
| 2012-07-20 | ENGR00170434: MX6 - Add support to read Silicon version | Ranjani Vaidyanathan |
| 2012-07-20 | ENGR00154931 [MX6]L2 cache init wrong after resume | Anson Huang |
| 2012-07-20 | ENGR00153601 [MX6]Adjust L2 cache parameter | Anson Huang |
| 2012-07-20 | ENGR00152668 [MX6]Enable arch_reset | Anson Huang |
| 2012-07-20 | ENGR00152845-3 MSL imx6: msl files changes. | Jason Chen |
| 2012-07-20 | ENGR00139229-1 MX6: Bring up i.MX6 sabreauto with Single core | Zeng Zhaoming |
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index : linux-toradex.git | |
| Linux kernel for Apalis and Colibri modules | Toradex |
| summaryrefslogtreecommitdiff |