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All of the interrupts from the ENET block are not routed to
the GPC block. Hence ENET interrupts are not able to wake
up the SOC when the system is in WAIT mode. And the ENET
interrupt gets serviced only when another interrupt causes
the SOC to exit WAIT mode. This impacts the ENET performance.
To fix the issue two options:
1. Route the ENET interrupt to a GPIO. Need to enable the
CONFIG_MX6_ENET_IRQ_TO_GPIO in the config.
This patch provides support for routing the ENET interrupt
to GPIO_1_6. Routing to this GPIO requires no HW board mods.
If the GPIO_1_6 is being used for some other peripheral,
this patch can be followed to route the ENET interrupt to
any other GPIO though a HW mode maybe required.
2. If the GPIO mechanism cannot be used and is not enabled
by the above mentioned config, the patch will disable entry
to WAIT mode until ENET clock is active. When the ENET clock
is disabled, WAIT mode will be automatically enetered.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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This reverts commit 067c8dcfa79a169d86809272569fe734c4222c79.
i.mx6dl/dq sabreauto/sabresd board will boot up failed
randomly with this patch-set, thus revert it. [Jason]
Signed-off-by: Jason Liu <r64343@freescale.com>
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All of the interrupts from the ENET block are not routed to
the GPC block. Hence ENET interrupts are not able to wake
up the SOC when the system is in WAIT mode. And the ENET
interrupt gets serviced only when another interrupt causes
the SOC to exit WAIT mode. This impacts the ENET performance.
To fix the issue two options:
1. Route the ENET interrupt to a GPIO. Need to enable the
CONFIG_MX6_ENET_IRQ_TO_GPIO in the config.
This patch provides support for routing the ENET interrupt
to GPIO_1_6. Routing to this GPIO requires no HW board mods.
If the GPIO_1_6 is being used for some other peripheral,
this patch can be followed to route the ENET interrupt to
any other GPIO though a HW mode maybe required.
2. If the GPIO mechanism cannot be used and is not enabled
by the above mentioned config, the patch will disable entry
to WAIT mode until ENET clock is active. When the ENET clock
is disabled, WAIT mode will be automatically enetered.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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After using POR reset, the content in SRC will be reset.
See RM: 63.5.1.2.3 IPP_RESET_B(POR)
Because POR reset will reset most of register in IC, so use
SNVS_LP General Purpose Register (LPGPR) to store the boot mode value.
Below copy from SNVS_BlockGuide.pdf:
The SNVS_LP General Purpose Register provides a 32 bit read write
register, which can be used by any application for retaining 32 bit
data during a power-down mode
This Patch will use [7,8] bits of this register.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Previous setting of PUPSCR is 0x202, which means there is only ~63us
for LDO ramp up, sometimes, system fail to resume by USB remote wake up,
increase this timing to fix USB remote wake up issue.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The REG_BYPASS_COUNTER(RBC) holds off interrupts when the PGC
block is sending signals to power gate the core. This is apart
from the RBC counter's basic functionality to act as counter to
power down the analog portions of the chip.
But the counter needs to be set/cleared only when no interrupts
are pending. And also for correct hold off the interrupts, enable the
counter as close to WFI as possible.
The RBC counts CKIL cycles (32KHz)
So follow the following steps to set the counter
in suspend/resume in mx6_suspend.S:
1. Mask all the GPC interrupts.
2. Write the counter value to the RBC
3. Enable the RBC
4. Unmask all the interrupts.
5. Busy wait for a few usecs to wait for RBC to start counting
in case an interrupt is pending.
4. Execute WFI
Reset the counter after resume in pm.c:
1. Mask all the GPC interrupts.
2. Disable the counter.
3. Set the RBC counter to 0.
4. Wait for 80usec for the write to get accepted.
5. Unmask all the interrupts.
With the above steps, we can minimize the PDNSCR and PUPSCR counters
in the GPC. The basic condition for the RBC counter:
RBC count >= 25 * IPG_CLK + PDNSCR_SW2ISO.
PDNSCR_SW2ISO = PDNSCR_ISO = 1 (counts in IPG_CLK)
PUPSCR_SW2ISO = PUPSCR_ISO = 2 (counts in 32K)
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fix all build warnings in files:
arch/arm/mach-mx6/board-mx6sl_common.h
arch/arm/mach-mx6/board-mx6sl_evk.c
arch/arm/mach-mx6/clock_mx6sl.c
arch/arm/mach-mx6/cpu_regulator-mx6.c
arch/arm/mach-mx6/pm.c
arch/arm/mach-mx6/system.c
arch/arm/plat-mxc/dvfs_core.c
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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1. Fix AHB clock not changed to 3MHz in IDLE mode
2. Fix system hangs in IDLE mode due to changes made for LOCKDEP
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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1. Fix mutex_lock nested issue in idle mode
2. Fix mutex_lock nested issue in suspend mode
3. Fix spin_lock nested issue in busfreq
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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Need to ensure that DDR IO pads are not floated when
a peripheral that needs DDR is active, for ex SDMA.
Also need to keep IPMUX clock enabled even when ARM
is in WFI, so set the CCGR bits accordingly.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Change STANDBY mode to support the following for MX6SL:
1. assert VSTBY
2. ARM is power gated.
3. XTAL is ON
4. LDO 2P5 is disabled, weak 2P5 is enabled.
5. LDO 1p1 is enabled.
Implement this for a higher power but lower latency on resume
from STANDBY mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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1. If weak 2P5 is not enabled in DSM, need to enable pull down
function to make sure its voltage is 0V;
2. WB_COUNT need to set to a higher value instead of the reset
value to make sure it function normally.
Signed-off-by: Anson Huang <b20788@freescale.com>
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When system enter suspend, we increase CPUFreq to the highest point
without update the global loops_per_jiffy, it will lead to udelay
inaccurate during the last phase of suspend/resume.
WB counter and RBC counter need at least two 32K cycles to finish,
here we add 80us for safe.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Set DDR to 50MHz in low power audio playback.
AHB/AXI are at 24MHz.
Also fix correct usecount for PLL1 main clock. If not
it causes issues when pll1_sw_clk's parent is changed.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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[MX6X] Fix BogoMIPS value is not correct
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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When ARM enters WFI in low power IDLE state, float the DDR
IO pins to drop the power on the VDDHIGH rail.
Need to run WFI code from IRAM since DDR needs to be
put into self-refresh before changing the IO pins.
Drop AHB to 8MHz and DDR to 1MHz when ARM is in WFI when
in IDLE state.
Set IPG_PERCLK to run at 3MHz, since we want to maintain a
1:2.5 ratio between PERCLK to AHB_CLK.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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DL TO1.1 has fixed the ipg glitch issue which will
cause DSM mode resume fail, so now we enable DSM mode
on DL.
Signed-off-by: Anson Huang <b20788@freescale.com>
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CPUs may be waked up by SMP broadcast, and for this scenario, CPUs
can enter idle again directly to avoid run a long way to re-enter
idle, adding this interrupt check can minish SMP impact on peripheral
devices' performance.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add the new WAIT mode workaround added for MX6Q1.2 and MX6DLTO1.1.
A new bit is added to CCM_CGPR (bit 17). This bit needs to be
enabled for the WAIT mode fix to be active and needs to be disabled
before the system enters STOP mode with power gating enabled.
Fix WAIT mode bug when system is in low power IDLE mode:
In low power IDLE mode (AHB @ 24MHz), switch ARM to run from 24MHz
on MX6QTO1.1 and MX6DLTO1.0 chips when ARM core enters WAIT mode.
We still need to use the ARM:IPG_CLK ratio of 12:5. Since IPG_CLK
is at 12MHz, we need to run ARM below 28.8MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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There's only DISPLAY power down request setting before system suspends,
but without the paired DISPLAY power up request setting after resume.
This will cause ePxP/EPDC/SPDC module nonfunctional because the modules
will be powered down once pdn_req is asserted but not powered up again.
With this patch, ePxP/EPDC/SPDC survived (need reinitialize each, however)
on resume.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Previous patch only check the condition that GPT broadcast
event is ready or not before doing clock event switch.
It's not enough, as the clock switch from local timer to GPT
broadcast must be happen after GPT broadcast clock event setup
and current cpu's clock device switch to local timer clock event.
Otherwise, we will have chance that cpu exit the wait mode and
switch back clock event without local timer event setup correctly.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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As Mx6 dq, dl and sl have different DDR IO address, so
we need to do the DDR IO low power setting according
to different CPU type.
Also, Mx6sl has some different config in DSM, need to
separate it from other platforms.
Change mx6q_suspend to mx6_suspend, as it is a common
thing for all mx6 platforms.
Add rtc driver for mxsl platform to support suspend/resume test.
Signed-off-by: Anson Huang <b20788@freescale.com>
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To avoid the ARM from accepting an interrupt in the dangerous
window, reduce the ARM core freq just before the sytem is
about to enter WAIT state.
Reduce the ARM freq so as to maintain 12:5 ARM_CLK to IPG
ratio. Use the ARM_PODF to drop the frequency.
In a multicore case the frequency is dropped only when all the
4 cores are going to be in WFI.
In case of single core environment, its easy to drop the ARM core
freq just before WFI since there is no need to identify the state of
the other cores.
Some other points to note:
1. If "mem_clk_on" is added to the command line, the memory clocks will
not be gated in WAIT mode. This will increase the system IDLE power.
This mode is valid only on MX6sl, MX6DQ TO1.2 and MX6DL TO1.1.
2. In case the IPG clk is too low (for ex 50MHz) and ARM is at 1GHz,
we cannot match the 12:5 ratio using ARM_PODF only. In this case,
donot clock gate the memories in WAIT mode (available on MX6SL,
MXDQ TO1.2 and MXDL TO1.1). For MXDQ TO1.1 and MX6DL TO1.0, disable
system wide WAIT entry in this case.
In STOP mode, always ensure that the memory clocks are gated, else
power impact will be significant.
WAIT mode is enabled by default with this commit.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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add reboot to special function like mfg download mode,
android fastboot, recovery mode.
It use ASRC register to enter mfgtool download mode and other function.
For android fastboot, recovery function it use ASRC_GPR10 bit 7-8 bit,
it will checked in uboot and clear after read.
Add this feature to improve recovery function, to avoid infinit looping
enter recovery mode if some thing goes wrong in fastboot mode.
Also add convient function for developer.
usage:
download mode: "reboot download"
fastboot : "reboot fastboot"
recovery mode: "reboot recovery"
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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As mx6q soc use one clock to provide for cpu and local timer,
the local timers will be stopped when enter wait mode.
This causes system hang when enter wait mode with local timer
enabled. So we should switch the clock event to GPT
broadcast clock event before entering wait mode, and disable
local timers. Todo this, following changes made:
* In arch_idle(), we check if the GPT broadcast clock
event is switched to one shot mode. If the kernel clocksource
is switched from jiffies one to GPT, then we can use GPT
as broadcast event. And switch from local timer to GPT broadcast
event before entering mx6q_wait. Otherwise, kernel will hange
if the SW jiffies clock source is used.
We call clockevents_notify to switch clock source.
* Remove the enable_wait_mode check in local timer setup.
* Always return 0 in GPT v2 timer's set_next_event routing.
All the GPTs are running in free run mode as what driver did.
So we should allow the GPT CNT register roll over to 0 when it
reaches 0xFFFFFFFF. And the next event written to compare register
can less than the current value in CNT.
If we refused to do roll over settings, the kernel will continues
to set_next_event to GPT when the next event is far away and
we return negative value. This is happend when one CPU is in idle
and no timewheel is being expired in short time.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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The idea is to get the soc silicon revision from DIGPROG register Of
ANATOP(USB_ANALOG_DIGPROG), which will make kernel code independent
with bootloader which need pass the system_rev by ATAG.
This patch also will print the chip name and revision when kernel boot
up since this information is important for customer to know.
on i.mx6q TO1.1, it will print as the following:
CPU identified as i.MX6Q, silicon rev 1.1
Signed-off-by: Jason Liu <r64343@freescale.com>
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When system is going to enter WAIT mode, set PLL1 to 24MHz
so that ARM is running at 24MHz. This is a SW workaround for
the WAIT mode issue.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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To keep i.MX6DL resume work stably, need to open LDO on based
on the current codes.Will continue to optimize power in suspend
state in future codes.
Signed-off-by: Anson Huang <b20788@freescale.com>
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add mxs_reset_block() for mx6q.
In order to keep the same code as the community, I reduce the
parameters to one.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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1. Need to follow right programming model for wb_per_at_lpm
,zeroed wb_count each time exit from DSM and set it before
entering DSM;
2. For TO1.1, need to set fet_odrive for better power gate.
Signed-off-by: Anson Huang <b20788@freescale.com>
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There is small window where an interrupt can occur when the SOC is
in the process of entering WAIT mode. The ARM core responds to this
interrupt and can access the internal memories when their clocks are
disabled.
To avoid crashes generated due to this, WFI code should be executed
from non-cacheable IRAM and enough delay should added after the
WFI so that accesses to memories are prevented.
This workaround assumes that all interrupts are routed to CPU0 only.
This workaround is applicable to iMX6DL/Solo also.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The root cause of suspend/resume fail has been found,
the i-cache should be invalidated before resume. So
the workaround can be removed.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Fix the following build warning:
1.arch/arm/mach-mx6/cpu.c:36: warning: function declaration isn't a
prototype
2.arch/arm/mach-mx6/system.c:55: warning: function declaration isn't a
prototype
3.arch/arm/mach-mx6/board-mx6q_sabreauto.c:751: warning: unused variable
'iterations'
Signed-off-by: Anson Huang <b20788@freescale.com>
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Only CPU0 executes WFI followed by ISBs in uncached iRAM.
All other cores execute the regular cpu_do_idle()
This puts a restriction that all interrupts should only be routed to CPU0.
This bug should be fixed in TO1.1.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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GPU power down/up follow a restrict process.
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
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add performance monitor device to mx6q arm2 board.
add perfmon clocks to clock tree.
add perfmon to default config as a module
Signed-off-by: Tony Lin <tony.lin@freescale.com>
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Need to decline SOC LDO domain voltage to make 800M ARM2 board work,
we can set the SOC power domain to be same as ARM core power domain.
Tested on both 1G rework board and 800M origin board.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Previous setting for ARM core is 1V during suspend, it
is working for 800MHz cpu freq, but not enough for
1G cpu freq, actually, we didn't need to change ARM core
LDO's setting during suspend, hardware will auto change it.
Signed-off-by: Anson Huang <b20788@freescale.com>
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When WAIT mode is not enabled, execute cpu_do_idle() code.
Currently WAIT mode requires the code to be run from IRAM with caches disabled.
No L2 cache access should be done for a specified period after the system exits
WAIT mode. This delay and running code from IRAM adversely affects the
SDHC performance.
Hardware team is looking into the extended delay that is required.
Till its root caused, default should be to execute cpu_do_idle() and
disable entry into WAIT mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add necessary implement to lower the SOC power
when dormant, on ddr3, ARM+SOC is ~3.8mA, and
on LPDDR2, it is ~2.3mA.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Set the appropriate bit in CCM to allow ARM-CORE to enter WAIT
mode when system is idle.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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add the arch code for GPMI.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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1. Enable dormant mode in suspend, which means arm
core will be powered off when enter wfi, the latest
command for stop mode and dormant mode are as below:
echo standby > /sys/power/state
-> stop mode with arm core power on
echo mem > /sys/power/state
-> stop mode with arm core power off
2. Remove all iram related code in suspend.
Signed-off-by: Anson Huang <b20788@freescale.com>
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1. Add irq_set_wake function to gic chip;
2. Fix uart no_console_suspend issue;
Signed-off-by: Anson Huang <b20788@freescale.com>
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Enable suspend/resume feature for MX6q
echo standby > /sys/power/state -> wait mode;
echo mem > /sys/power/state -> stop mode;
Currentlu only support debug uart as wakeup source;
Signed-off-by: Anson Huang <b20788@freescale.com>
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MSL code for bring up MX6 sabreauto board with Single core.
Merged from testbuild:imx6_bringup branch.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Singed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: Richard Zhu <r65037@freescale.com>
Signed-off-by: Anish Trivedi <anish@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Jason Chen <b02280@freescale.com>
Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Sammy He <r62914@freescale.com>
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
Merged-by: Zeng Zhaoming <b32542@freescale.com>
Reviewed-by: Jason Liu <r64343@freescale.com>
Reviewed-by: Frank Li <Frank.Li@freescale.com>
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