Age | Commit message (Collapse) | Author |
|
For i.MX6DLTO1.1 and i.MX6DQTO1.2, the disconnection-bit can only be set after
the resume finished, otherwise, the remote-wake-up may fail. Because if the
device not switch to High-Speed 45ohm termination resistors mode, when the
disconnection detection bit is set the disconnection detection circuit will
detect a high speed disconnection by mistake.
Signed-off-by: make shi <b15407@freescale.com>
|
|
The Mx6 phy sometimes work abnormally after system suspend/resume if the 1V1
is off. So we should keep the 1V1 active during the system suspend if any USB
host enabled.
- Add stop_mode_config to 1 with refcount
- Add mutex to protect the refcount and HW_ANADIG_ANA_MISC0 register
- If stop_mode_config is set as 1, the otg vbus wakeup system will be supported
Signed-off-by: make shi <b15407@freescale.com>
|
|
- for Rigel1.1/Arik1.2, bit 17 of HW_USBPHY_IP will be set, it will fix the
issue that no wakeup between SUSP/PHCD. And the usb_platform_rh_suspend/
usb_platform_rh_resume do not need do complex software workaround, only
need set/clear the workaround bit.
- for Megrez , bit 17 and bit 18 of HW_USBPHY_IP will be set, it will fix the
issue that no wakeup between SUSP/PHCD and disconnect after resume. No need
do any software workaround.
Signed-off-by: make shi <b15407@freescale.com>
|
|
- remove mx6_usb_h1_init() in board specific initialization files
- Add module_init(mx6_usb_h1_init) and module_exit(mx6_usb_h1_exit) in usb_h1.c
to support the usb_h1 modulization
- Export necessary function which is used in usb_h1.c
Signed-off-by: make shi <b15407@freescale.com>
|
|
- add a function to tell if sw walkaround is needed
for the IC bug
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
|
|
modify usb wakeup interrupt number for mx6sl
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
|
|
- in mx6sl RM, the irq of usb h1(usb otg2) is 72, but
in fact, it should be 74, we need change the irq special
for mx6sl
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
|
|
- change msleep(1) to udelay(500)
- msleep may be called in atomic context, which will cause
warning message
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
|
|
According to IC guys, it needs to enable/disable usb wakeup setting at
controller and phy side together.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|
|
MSL part
- after suspend bit is set, we need to set PWD bit and
clear it right now to let PHY know the state change
- after suspend bit is set, disconnect detection should be
clear
- after set resume bit, disconnect detection should be set
after 30 ms
- IC issue PDM refer to
TKT092876
TKT092872
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
|
|
The host driver needs to differentiate wakeup event.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|
|
This issue will happen only when suspend bit is set but phcd is not set
The root cause of this issue is the IC defect.
- If the suspend bit is set without phcd bit set, host controller
can't resume normally
- The workaround is after set suspend bit, we need set the following
bit in USB PHY at once:
HW_USBPHY_PWD_RXPWDRX
HW_USBPHY_PWD_RXPWDDIFF
HW_USBPHY_PWD_RXPWD1PT1
HW_USBPHY_PWD_RXPWDENV
HW_USBPHY_PWD_TXPWDv2I
HW_USBPHY_PWD_TXPWDIBIAS
HW_USBPHY_PWD_TXPWDFS
- Furthermore, after resume, we must clear these bits during the K state
- IC has no plan to fix this issue
- This issue only happen on MX6Q/MX28
MSL part
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
|
|
Enable OTG driver on mx6q board
Signed-off-by: make shi <b15407@freescale.com>
|
|
Add necessary implement to Enable USB host1 function
Signed-off-by: make shi <b15407@freescale.com>
|
|
wakeup_pdata is initialized after device register, thus the field can't be
initialized correctively. change to the correct sequence.
Signed-off-by: Tony Lin <tony.lin@freescale.com>
|
|
(Fixed the bug that PLL7 lock failed after usb enters low power mode)
After confirming with IC guys, the phy clock should be used
like below:
- OTG phy clock
EN_USB_CLKS: should be also enabled
PLL3 power: Enable/Disable on the fly
- Host1 phy clock
EN_USB_CLKS and PLL7 power should be also enabled at the initialization
PLL7 power will be totally controller by IC
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|
|
Changes at MSL
- Add usb code for mx6q
- Usb host functions (keyboard and u-disk) are verified
- USB host low power mode and wakeup are supported
- defconfig for otg port is for host port
- Using upstream platform device register method
- Delete some useless code, and fix the warning during building
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|