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* Aline weim-nor partition layout with u-boot expected
offtsets
"bootloader" /dev/mtd0
"bootenv" /dev/mtd1
"kernel" /dev/mtd2
"rootfs" /dev/mtd3
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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* Aline spi-nor partition layout
* set correct chip-select value
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Forget submit some local change...
Signed-off-by: Robin Gong <b38343@freescale.com>
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On Sabresd board design, the WDOG_B output to reset external pmic source from
GPIO_2 pad which can be configured as WDOG2_WDOG_B, so if in ldo bypass mode,
we should use WDOG2 reset signal to reset pmic, not WDOG1. Also, configure the
related pins.
Signed-off-by: Robin Gong <b38343@freescale.com>
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U-boot will not care about ldo bypass, move these code from u-boot to kernel.
Move the workaround for PFUZE1.0 to kernel too.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Currently, use CONFIG_MX6_INTER_LDO_BYPASS to enable/disable LDO bypass, and
use the same macro in u-boot too. It's not very friendly ,it will be more
flexible if use dynamic configure by command line input by u-boot.
Two ways to enable LDO bypass:
1. use command line:
You can set "ldo_active=on" or "ldo_active=off" in command line to enable/
disable LDO bypass.
2. set enable_ldo_mode value in board file:
If you didn't set the param in command line, every board
will use its default value, for example, you can find below code in arch/arm/
mach-mx6/mx6q_sabresd_pmic_pfuze100.c:
static int pfuze100_init(struct mc_pfuze *pfuze)
{
....
/*use default mode(ldo bypass) if no param from cmdline*/
if (enable_ldo_mode == LDO_MODE_DEFAULT)
enable_ldo_mode = LDO_MODE_BYPASSED;
....
}
Note:
1.You should know clearly ldo bypass can be only enabled in the board
that mounted with external pmic to supply VDDARM_IN/VDDSOC_IN power rail, and
you should implement related external regulator firstly, such as:
in arch/arm/mach-mx6/board-mx6q_sabresd.c
static struct mxc_dvfs_platform_data sabresd_dvfscore_data = {
.reg_id = "VDDCORE",
.soc_id = "VDDSOC",
....
}
otherwise, you have to use internal ldo which is the default configuration.
2.one special case, if the chip is 1.2Ghz, it can't be set LDO bypass.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Before, we use "arm_freq" in command line to set 1.2G. Now we will read the
fuse bit and "arm_freq", get the mini value to be used as "arm_max_freq".And:
1. you can easily set CPU max freq on what frequency you want by cmdline.
2. if you didn't set arm_freq in cmdline, kernel will read the fuse bit
(0x021bc440) to set the right arm_max_freq.
At the same time, add 1Ghz setpoint if chip max freq is 1.2Ghz.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Setting certain IOMUX settings on SD1 prevents the system from
entering suspend. These pins are already configured as GPIO, so
it does not help to reconfigure them during suspend.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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In MX6Q/DL, originally GPIO_0 is used as CKO pin function. when SNVS
module is enabled, CKO output stops suddenly.
Both CKO clock config register CCOSR and GPIO_0 IOMUX register value are
not changed. But because ALT7 of GPIO_0 pad is SNVS_VIO_5 function. I
doubt that when SNVS module is enabled, GPIO_0 pad is automatically
changed to SNVS instance by SoC.
Thus we add option for snvs enable/disable.
Signed-off-by: Terry Lv <r65388@freescale.com>
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We should use module_init as usb driver initialization entry point.
To avoid the following crash when sabreauto board bootup:
Unable to handle kernel NULL pointer dereference at virtual address 00000030
pgd = 80004000
[00000030] *pgd=00000000
Internal error: Oops: 5 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 Not tainted (3.0.35-02249-g6493632-dirty #3070)
PC is at gpio_set_value_cansleep+0x20/0x34
LR is at mx6_usb_h1_init+0x68/0x188
pc : [<80251638>] lr : [<80010bd4>] psr: 20000013
sp : e4049f60 ip : 000000ef fp : 00000000
r10: 00000000 r9 : 00000000 r8 : e4049f8c
r7 : 80521f04 r6 : e4049f80 r5 : 80521f10 r4 : 80af53cc
r3 : 00000000 r2 : 00000001 r1 : 00000001 r0 : 00000000
Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 1000404a DAC: 00000015
Process swapper (pid: 1, stack limit = 0xe40482f0)
Stack: (0xe4049f60 to 0xe404a000)
9f60: 80af53cc 80010bd4 00000001 02184200 0000004a 00000001 02184200 00000048
9f80: 00000001 0000004d 0000004a 00000001 0000004d 00000048 8002e020 80af4ac0
9fa0: 00000000 80010b6c 00000000 8003b4c4 00000000 80130000 00000000 80abf898
9fc0: 000001f0 8002e020 8002e564 80042040 00000013 00000000 00000000 00000000
9fe0: 00000000 800083cc 00000000 80008334 80042040 80042040 5104b14a f0e00000
[<80251638>] (gpio_set_value_cansleep+0x20/0x34) from [<80010bd4>]
(mx6_usb_h1_init+0x68/0x188)
[<80010bd4>] (mx6_usb_h1_init+0x68/0x188) from [<8003b4c4>]
(do_one_initcall+0x30/0x16c)
[<8003b4c4>] (do_one_initcall+0x30/0x16c) from [<800083cc>]
(kernel_init+0x98/0x144)
[<800083cc>] (kernel_init+0x98/0x144) from [<80042040>]
(kernel_thread_exit+0x0/0x8)
Code: e92d4010 e7933100 e1a02001 e1a00003 (e5931030)
---[ end trace 1b75b31a2719ed1c ]---
Kernel panic - not syncing: Attempted to kill init!
[<8004823c>] (unwind_backtrace+0x0/0xfc) from [<8051d790>]
(panic+0x74/0x19c)
[<8051d790>] (panic+0x74/0x19c) from [<80078ba8>] (do_exit+0x664/0x718)
[<80078ba8>] (do_exit+0x664/0x718) from [<80044fcc>] (die+0x250/0x2c8)
[<80044fcc>] (die+0x250/0x2c8) from [<8004ba74>]
(__do_kernel_fault+0x64/0x84)
[<8004ba74>] (__do_kernel_fault+0x64/0x84) from [<8004bc14>]
(do_page_fault+0x180/0x2e0)
[<8004bc14>] (do_page_fault+0x180/0x2e0) from [<8003b400>]
(do_DataAbort+0x34/0x98)
[<8003b400>] (do_DataAbort+0x34/0x98) from [<80040f10>]
(__dabt_svc+0x70/0xa0)
Some board for example sabreauto board usb power gpio is use a io
i2c expander gpio, gpio i2c driver load use subsys_initcall as driver
initialization entry point, so gpio is not accessible at early bootup.
Signed-off-by: make shi <b15407@freescale.com>
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Change 996M setpoint voltage according to datasheet,
lower VDDARM_CAP from 1.275V to 1.25V, and VDDSOC/PU_CAP
from 1.275V to 1.175V.
Signed-off-by: Anson Huang <b20788@freescale.com>
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- remove mx6_usb_dr_init() in board specific initialization files
- Add module_init(mx6_usb_dr_init) and module_exit(mx6_usb_dr_exit)
in usb_dr.c to support the usb_dr modulization
- Export necessary function which is used in usb_dr.c
Signed-off-by: make shi <b15407@freescale.com>
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MSL headfile part change
-Add and remove some function define in usb.h
Signed-off-by: make shi <b15407@freescale.com>
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- Add USB_FSL_ARC_OTG configuration to imx6_defconfig and imx6s_defconfig,
the default configuration is selected as "y"
- add related USB_FSL_ARC_OTG configuration to Makefile
- add related USB_FSL_ARC_OTG configuration to Kconfig
Signed-off-by: make shi <b15407@freescale.com>
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Previous setting of PUPSCR is 0x202, which means there is only ~63us
for LDO ramp up, sometimes, system fail to resume by USB remote wake up,
increase this timing to fix USB remote wake up issue.
Signed-off-by: Anson Huang <b20788@freescale.com>
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* Pass csi-tx slave address for adv7280 chipset
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Improve the board level suspend power by configuring
various IOMUX pads to low power state.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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IPG_PERCLK is the parent of I2C. I2C needs a minimum of
12.8MHz as its input clock to achieve 400KHz speed. Hence
change the IPG_PERCLK speed accordingly.
MX6DQ/MX6DL - Set IPG_PERCLK at 22MHz (sourced from IPG_CLK)
MX6SL - Set IPG_PERCLK to 24MHz(Sourced from 24MHz XTAL).
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Configure MUX settings for bluetooth operation over UART3.
Enable RTS,CTS and DMA only for uart3.
Affected files :
arch/arm/mach-mx6/board-mx6q_sabreauto.c
arch/arm/mach-mx6/board-mx6q_sabreauto.h
arch/arm/mach-mx6/board-mx6solo_sabreauto.h
arch/arm/plat-mxc/include/mach/iomux-mx6q.h
On behalf of Francisco Munoz <francisco.munoz@freescale.com>.
Some modification are needed also on hciattach tool.
Signed-off-by: Israel Perez <B37753@freescale.com>
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1. Revert ENGR00231910 Do not disable PU regulator,revert the PU
regulator patch;
2. VPU reset register address is different on MX6 and MX5. It can
fix ENGR00230203 [Android_MX6DL_SD] Gallery: System hang after resume
from suspend during video playback. 20%
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
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If system enter suspend/resume during VPU encoding on Rigel, there will be
"VPU blocking: timeout." error . But there is ok if enter suspend/resume
during VPU decoding and enter suspend/resume during encoding/decoding on
Arik, until now we didn't know the root cause, so revert it firstly.
Because the previous patch about PU regulator is composed with four commits
and hard to revert, now we adopt simplest way that do not disable PU regulator
in low level. The negative impact is there will several mA increasment in
suspend, we will fix it ASAP.
Signed-off-by: Robin Gong <b38343@freescale.com>
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SD card card detection and NFC controller CS2 share
the same pin on ARD platform. However CS2 is not
connected to the socket. This signal was removed
from the sabreauto board file.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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3 pairs of clock enable bits are required for CAAM clocking:
(1) wrapper IPG clock
(2) wrapper ACLK
(3) secure memory clock
IPG enable happened to be using an incorrect shift selection, which
had the net effect of leaving secure memory unclocked. Added the correct
shift selection in so that all 3 clock enable pairs are turned on.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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There is 6% tolerance for PFM momde in standby so we need set 0.975V(>0.9V+%6)
for VDDSOC and VDDARM which maybe impact system resume ability.
Another two change is:
1.set VDDARM and VDDSOC standby voltage by setting PFUZE register directly,it
is not very friendly.So use more common "state_mem" in constrain of regulator
to set standby voltage.
2.align sabreauto code with sabresd
Signed-off-by: Robin Gong <b38343@freescale.com>
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In mx6q arm2 board, the gpmi conflicts with SD module.
But the defconfig has enabled the gpmi by default.
So we have to add a kernel cmdline to enable the gpmi by hand in arm2 board.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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The USB FS eye test will fail in MX6 board if the 3V USB phy LDO is not enabled.
Setting enable bit (bit-0) of LDO 3p0 will make 3p0 LDO to use bandgap output as
reference voltage, LDO output will be accurate. And HW team suggest that it is
better to raise the voltage of USB 3p0 phy LDO 3.2V to pass the USB compliance
testing.
- Implement vdd3p0 regulator enable and disable function to support
enable and disable the LDO 3p0 regulator.
- Use regulator API to enable the USB 3p0 phy LDO and raise the LDO
to 3.2V during system boot up. And disable the LDO before system
enter suspend and enable the LDO again after system resume.
Signed-off-by: make shi <b15407@freescale.com>
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Only enable power gating for PXP and EPDC. The feature for ELCDIF still need to
be verified.
Signed-off-by: Robby Cai <R63905@freescale.com>
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* Add ad7280 I2C device support
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Oscar Luna <r01160@freescale.com>
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Add eCompass support on Sabreauto platform
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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Configuration file modified to support NAND flash, SPI-NOR,
WEIM NOR and SD card on the same image.
Bootloader arguments will be used to choose between them.
Arguments on uboot are:
spi-nor
weim-nor
By default NAND is configured if neither spi-nor or weim-nor are used
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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* Adv7180 use tvin io_init callback to configure csi0/ipu
mux settings mx6q_csi0_io_init.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Write to the MMDC registers when resetting the MMDC after the
DDR I/Os have been floated.
This fixes the bug introduced by the commit:
"2a2f65bd07ad0f947794c2e5f2f825121805d663
MX6SL-Reset MMDC read FIFO in low power IDLE"
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The REG_BYPASS_COUNTER(RBC) holds off interrupts when the PGC
block is sending signals to power gate the core. This is apart
from the RBC counter's basic functionality to act as counter to
power down the analog portions of the chip.
But the counter needs to be set/cleared only when no interrupts
are pending. And also for correct hold off the interrupts, enable the
counter as close to WFI as possible.
The RBC counts CKIL cycles (32KHz)
So follow the following steps to set the counter
in suspend/resume in mx6_suspend.S:
1. Mask all the GPC interrupts.
2. Write the counter value to the RBC
3. Enable the RBC
4. Unmask all the interrupts.
5. Busy wait for a few usecs to wait for RBC to start counting
in case an interrupt is pending.
4. Execute WFI
Reset the counter after resume in pm.c:
1. Mask all the GPC interrupts.
2. Disable the counter.
3. Set the RBC counter to 0.
4. Wait for 80usec for the write to get accepted.
5. Unmask all the interrupts.
With the above steps, we can minimize the PDNSCR and PUPSCR counters
in the GPC. The basic condition for the RBC counter:
RBC count >= 25 * IPG_CLK + PDNSCR_SW2ISO.
PDNSCR_SW2ISO = PDNSCR_ISO = 1 (counts in IPG_CLK)
PUPSCR_SW2ISO = PUPSCR_ISO = 2 (counts in 32K)
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fix all build warnings in files:
arch/arm/mach-mx6/board-mx6sl_common.h
arch/arm/mach-mx6/board-mx6sl_evk.c
arch/arm/mach-mx6/clock_mx6sl.c
arch/arm/mach-mx6/cpu_regulator-mx6.c
arch/arm/mach-mx6/pm.c
arch/arm/mach-mx6/system.c
arch/arm/plat-mxc/dvfs_core.c
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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MMDC can clock in bad data due to the glitches caused by
changing the setting of various DDR IO pads in low power
IDLE to save power. Solution is to reset the MMDC read FIFO
before the DDR exits self-refresh.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Update the VDDARM and VDDSOC voltages based on IMX6SLCEC_Rev0
datasheet.
As the voltages for ARM @ 198MHz and ARM @ 396MHz are the same
remove the 198MHz working point.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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1. Fix AHB clock not changed to 3MHz in IDLE mode
2. Fix system hangs in IDLE mode due to changes made for LOCKDEP
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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1. Fix mutex_lock nested issue in idle mode
2. Fix mutex_lock nested issue in suspend mode
3. Fix spin_lock nested issue in busfreq
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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Add csi v4l2 platform device only when 'csi' is assigned in cmdline.
Because there's pin conflicts between csi and epdc.
Signed-off-by: Robby Cai <R63905@freescale.com>
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For DQ and DL, we must make sure DDR can be accessed after resume,
our code did NOT get a valid base address for MMDC to exit from
DVFS mode, need to fix it.
According to ARM, we only need to save r0-r3 and r12 before calling
C function.
Signed-off-by: Anson Huang <b20788@freescale.com>
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issue:
Once entering low power idle mode, pll2_400 will be bypass which will change
the clk rate of sdhc root clk. so far, there's no mechanism to inform sdhc
for changing of root clk in current driver structure.
fix:
Revert "ENGR00226096 mx6sl: remove high set point for usdhc"
This reverts commit 97aee96a34ca63da0d1d602a19b3a444352e5803.
Acked-by: Robby CAI <r63905@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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Setup uart2 to enable bluetooth basic functionality on mx6sl evk board.
DMA mode was not enabled for uart2 operation.
Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
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Currently, the sequence and functionality we use to enter and exit
suspend causes us to hang upon resuming. It appears that this is being
caused by two things. The first is the powering off of the 2p5 rail
which powers the IO pullups and pulldowns. The DQS pins were
configured as pull downs. The second is switching the DQS pins from
differential to CMOS mode (and back). This second problem only
occurs on a few EVK boards.
It is believed that these changes are causing glitches on the mmdc DQS
pins which is putting garbage in the FIFO (or causing some other FIFO
problem). This patch adds two mmdc0 FIFO resets after exiting the
suspend. Two are thought to be needed per previous FIFO reset
experience by Mike Kjar.
Since the MMDC0 FIFO will be cleaned each time, we can now remove
the code that configured the DQS lines as pull downs as we no
longer care if they float.
Signed-off-by: Robert Lee <robert.lee@freescale.com>
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According to the latest specification data, these rails should
go no lower than 900mV in standby mode. This patch modifies
the existing mx6sl board files and sets the pmic standby voltage
for these rails to be 925mV (extra 25mV to account for pmic accuracy).
Signed-off-by: Robert Lee <robert.lee@freescale.com>
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Need to ensure that DDR IO pads are not floated when
a peripheral that needs DDR is active, for ex SDMA.
Also need to keep IPMUX clock enabled even when ARM
is in WFI, so set the CCGR bits accordingly.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Different linker may use r12, we should save/restore all
registers(r0-r12) before calling C function to prevent
these registers from corruption in C code.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Although 400M bus setpoint can save some SOC domain power,
but it will also bring some additional power consumption
to DDR3, and the DDR performace's drop could also lead to
more heat generated by COREs which will spent more time
waiting for DDR data ready, also, there is not many usecases
that need this setpoint, all in all, we should remove 400M
setpoint.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Change STANDBY mode to support the following for MX6SL:
1. assert VSTBY
2. ARM is power gated.
3. XTAL is ON
4. LDO 2P5 is disabled, weak 2P5 is enabled.
5. LDO 1p1 is enabled.
Implement this for a higher power but lower latency on resume
from STANDBY mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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* Fix imx_dma_data duplicate struct definition
* Rename struct as name conflicts with imx_dma_data
struct defined at arch/arm/plat-mxc/include/mach/dma.h
* Update copyrigth year.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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MX6SL and MX6DL have only 128KB of IRAM. Fix the
code so the right size is passed to iram_init()
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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