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In order to fix the performance issue on ENET when WAIT mode
is activated, route the ENET interrupts to a GPIO on all MX6DL boards.
This patch must be applied on top of:
MX6Q/DL-Fix Ethernet performance issue when WAIT mode is active
808863866d2c17aeb3e70a7fcd094bd96db4b601
bae4d40849f3acdd9663f5a0857c9415ed7e6d5d
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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All of the interrupts from the ENET block are not routed to
the GPC block. Hence ENET interrupts are not able to wake
up the SOC when the system is in WAIT mode. And the ENET
interrupt gets serviced only when another interrupt causes
the SOC to exit WAIT mode. This impacts the ENET performance.
To fix the issue two options:
1. Route the ENET interrupt to a GPIO. Need to enable the
CONFIG_MX6_ENET_IRQ_TO_GPIO in the config.
This patch provides support for routing the ENET interrupt
to GPIO_1_6. Routing to this GPIO requires no HW board mods.
If the GPIO_1_6 is being used for some other peripheral,
this patch can be followed to route the ENET interrupt to
any other GPIO though a HW mode maybe required.
2. If the GPIO mechanism cannot be used and is not enabled
by the above mentioned config, the patch will disable entry
to WAIT mode until ENET clock is active. When the ENET clock
is disabled, WAIT mode will be automatically enetered.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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For MLB uses iram for data transfer, and there's a missing of dependency
on iram in MLB's clock setting, MLB can't receive data in wait mode.
We need to add ocram clock dependency in MLB clock.
Signed-off-by: Terry Lv <r65388@freescale.com>
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This reverts commit 067c8dcfa79a169d86809272569fe734c4222c79.
i.mx6dl/dq sabreauto/sabresd board will boot up failed
randomly with this patch-set, thus revert it. [Jason]
Signed-off-by: Jason Liu <r64343@freescale.com>
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* Correct mipi-csi2 settings only one data line is used
* Add mx6q_mipi_csi1_io_init ipu-csi setting callback
use virtual channel 1 and attach it to CSI1 -> IPU0
* Set i2c slave address to 0x52
* Set ipu-csi clko_clk
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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After enable PICE in kernel config, building will meet
fatal error:linux/wakelock.h: No such file or directory
Signed-off-by: Zhang Xiaodong <B39117@freescale.com>
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These timings are calculated from the M29W256GL7AN6E.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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This reverts commit 58209e14383520d58b1bf74e0e9f98f7d05b80c6.
After apply these two patches, we can not pass the stress test.
So revert these two patches.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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All of the interrupts from the ENET block are not routed to
the GPC block. Hence ENET interrupts are not able to wake
up the SOC when the system is in WAIT mode. And the ENET
interrupt gets serviced only when another interrupt causes
the SOC to exit WAIT mode. This impacts the ENET performance.
To fix the issue two options:
1. Route the ENET interrupt to a GPIO. Need to enable the
CONFIG_MX6_ENET_IRQ_TO_GPIO in the config.
This patch provides support for routing the ENET interrupt
to GPIO_1_6. Routing to this GPIO requires no HW board mods.
If the GPIO_1_6 is being used for some other peripheral,
this patch can be followed to route the ENET interrupt to
any other GPIO though a HW mode maybe required.
2. If the GPIO mechanism cannot be used and is not enabled
by the above mentioned config, the patch will disable entry
to WAIT mode until ENET clock is active. When the ENET clock
is disabled, WAIT mode will be automatically enetered.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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If not, the clocks usage will be mismatch
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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The previous patch ENGR00251630 didn't notice mx6q_revision() will
return -EINVAL and will match 'mx6q_revision()<IMX_CHIP_REVISION_1_1'
,then mx6dl TO1.1 will also change suspend state to 'standby'.
Signed-off-by: Robin Gong <b38343@freescale.com>
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For MX6DL,align max cpufreq judge by SPEED_GRADING fuse bit with MX6DQ.
For MX6SL without the fuse bit, we need add condition check, if found
arm_max_freq set by default , change to1G. Else decided by 'arm_freq'
setting by cmdline.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Support LVDS1 and HDMI dual display on SabreSD Rev.C board on i.mx6
By default, LVDS uses LDB_SEP1 mode due to the hardware design.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Config clock,irq,mux pad,data entry, etc to setup uart5.
Signed-off-by: Jianzheng Zhou <jianzheng.zhou@freescale.com>
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- enable the auto detect for parallel ov5642 and ov5640 in sabresd board.
Signed-off-by: Sheng Nan <b38800@freescale.com>
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- enable the auto detect for parallel ov5642 and ov5640 in sabrelite board.
Signed-off-by: Sheng Nan <b38800@freescale.com>
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Keep the phy lower flag as true defaultly, the driver should mark
it as false when the driver begins to use PHY.
This fixes one bug that when build both host and gadget as loadable
modules, the phy lower flag is false if the related module is not
loaded, then, the wakeup interrupt will not be treated as happened
if host module is loaded, but gadget is not loaded, or vice verse.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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At gadget module remove function, it closes the clock, but
at platform code, it still visits register. In fact,
The PHY has already been low power mode when driver's remove
before platform code is called.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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/home/b29397/work/projects/linux-2.6-imx/arch/arm/mach-mx6/usb_dr.c:
In function 'mx6_usb_dr_init':
/home/b29397/work/projects/linux-2.6-imx/arch/arm/mach-mx6/usb_dr.c:
615: warning: unused variable 'imx6q_mxc_ehci_otg_data'
/home/b29397/work/projects/linux-2.6-imx/arch/arm/mach-mx6/usb_dr.c:
At top level:
/home/b29397/work/projects/linux-2.6-imx/arch/arm/mach-mx6/usb_dr.c:
77: warning: 'fsl_platform_otg_set_usb_phy_dis' defined but not used
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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The callback will be used at probe and remove
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Connecting two boards directly more than 2 hours, Ar8031 phy link
status generates glitch, which cause ethernet link down/up issue, but
ethernet still be active. There have three cases to validate the issue:
Item#1: If add performance stress test while runing IEEE1588, the link
down/up issue cannot be found.
Item#2: If insert switch between two net nodes and run IEEE1588 test,
the issue also cannot be found.
Item#3: If disable AR8031 SmartEEE feature, after two days overnight test,
no such issue found.
The issue is caused by phy Ar8031 SmartEEE feature, Item#1 and Item#2 can
prevent phy enter lpm mode, which match the Item#3 test result, so disable
SmartEEE feature to avoid the link issue generation.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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You can see "cpu regulator mode:ldo_bypass" log directly from console when boot.
not "cpu regulator init ldo=1" before.
Signed-off-by: Robin Gong <b38343@freescale.com>
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You can see "arm_max_freq=1GHz" log directly from console during boot.
not "arm_max_freq=1" before.
Signed-off-by: Robin Gong <b38343@freescale.com>
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System will resume back failed which caused by IPG clock glich issue. The issue
(TKT094231) has been fixed on MX6DQ TO1.2 and MX6DL TO1.1.It is hard to
reproduced on MX6DQ TO1.1/1.0 with 0xffffffff in GPC_PGC_CPU_PUPSCR
which implemented on GA release. But it is easy to reproduced with 0xf0f0 on
mainline now. As we focus on latest formal chip, the problem is cleaned up until
now. We will aign with the workaround on MX6DL which do not power off ARM in
suspend.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Increase the NOR flash read speed.
Added weimnor driver to use cached (and page mode) reads.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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In order to save power consumption, disable pcie phy
(enable IDDQ mode) in kernel initialization.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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In order to save power consumption, disable sata phy
(enable PDDQ mode) in kernel level, if the sata module
is not enabled in kernel configuration.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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deprieved from boundary msi support patch
add the following modifications
* use the RC's line address 0x01FF8000 instead of one
actual physical memory as the msi start address.
The physical memory address is not mandatory required by the
msi start address.
* set PCI_MSI_FLAGS_ENABLE in RC's msi capability
structure when the msi int is enabled.
* the data of msg is only 16bit, set the upper 8bit
cputype, and the msi int num to the lower 8bit.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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This patch removes the unnecessary global variable declaration for
enable_wait_mode.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch contains code change only to print out
link up failure log like below.
link up failed, DB_R0:0x001b8400, DB_R1:0x08200000!
Before the change, the present print code can never
be called even if the link up fails.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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1.LDO ramp up time may be modified by ROM code
according to fuse setting, cpu freq driver use
fixed delay time which assume the LDO ramp up time
is the reset value of ANATOP register, need to set
it to reset value in regulator init.
2.The regulator set voltage should take care of
the ramp up time, calculate the ramp up time based
of register setting and to the delay, make sure that
when the set voltage function return, the voltage is
stable enough.
3.CPUFreq no need to use delay, it is already taken
care by regulator voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
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This patch sets HDMI PHY register values in MXC HDMI driver
platform data so that MXC HDMI driver can configure the
0x09 CKSYMTXCTRL register(Clock Symbol and Transmitter
Control Register) and 0x0E VLEVCTRL register(Voltage Level
Control Register), then we may pass HDMI compliance test
for MX6 HDMI dongle board.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 788bcf52a2e4c37dc42e9605d31995f8dd80d674)
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The pcie ep device inserted into the downstream port of the
pcie switch doesn't get the legacy INT when pcie switch
is used.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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PCIe switch access mechanism:
- CfgRd0/CfgWr0 is used to access the CFG space of the EP device
or the upstream port of PCIe switch that is connected to RC directly.
- CfgRd1/CfgWr1 is used to access the CFG space of the downstream port
of PCIe switch and so on cases.
UR and kernel crash problem:
i.MX6 PCIe maps UR(Unsupported Request)err to AXI SLVERR err, which would
cause the arm data abort exception.
There is one "Received Master Abort" in iMX6 Root complex Secondary
status register when a requester receives a Completion
with Unsupported Request Completion Status.
In this case, the Linux kernel would be crashed.
Workaround: correct this imprecise external abort.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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* Fix adv7180 tvin powerdown function
gpio power pin already exported in io-mux setup function
no need to request/free gpio
* Update copyrigth year 2013.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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VDDH should only be ON after VPOS when power up and should be off
before VPOS when power down. Set the appropriate MAX17135 timing
parameters for the correct power up/down sequence
Signed-off-by: Peter Chan <B18700@freescale.com>
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mx6sl_evk board uses Silex SXSDMAN board for bluetooth, add uart4 driver
to support it.
Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
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MX6SL EVK board uses Silex SX-SDMAN board for bluetooth.
Add rfkill interface to control SX-SDMAN reset.
The reset signal is required before using bluetooth.
Signed-off-by: Lionel Xu <R63889@freescale.com>
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when IRAM is used by SSI, add IRAM clock dependency to
SSI clock
Signed-off-by: Gary Zhang <b13634@freescale.com>
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on Sabresd board, IPG_PERCLK will be fixed on 6Mhz once system enter low bus,
and never restore to 22Mhz which be set in boot. It means some device clock
which sourcing from IPG_PERCLK such as I2C will be slow down. The root cause is
that there is workaround for GPT timer of Arik TO1.0 in mx6_ddr_freq.S. GPT
clock source from IPG_PERCLK on TO1.0 and should be fixed on 6Mhz. But for
TO1.1 and TO1.2 ,the workaround should be removed.
Signed-off-by: Robin Gong <B38343@freescale.com>
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Need to ensure that bus frequency setpoint is changed only if
the system is not already at the requested setpoint.
Changing the bus freq to high setpoint when its already at
high setpoint causes the AHB/IPG dividers to be set incorrectly.
Then when the system enters WAIT mode, the 12:5 ratio of
ARM_CLK:IPG_CLK is no longer maintained.
This causes random crashes.
Fix is to return immediately if the bus is already at the
requested setpoint
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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After using POR reset, the content in SRC will be reset.
See RM: 63.5.1.2.3 IPP_RESET_B(POR)
Because POR reset will reset most of register in IC, so use
SNVS_LP General Purpose Register (LPGPR) to store the boot mode value.
Below copy from SNVS_BlockGuide.pdf:
The SNVS_LP General Purpose Register provides a 32 bit read write
register, which can be used by any application for retaining 32 bit
data during a power-down mode
This Patch will use [7,8] bits of this register.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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In current linux BSP USB H1 driver default load before otg driver load,
which cause USBx not match the ehci controller number. like bellow:
root@freescale /sys/devices/platform/fsl-ehci.0$ ls
driver modalias pools power subsystem uevent usb2
root@freescale /sys/devices/platform/fsl-ehci.1$ ls
driver modalias pools power subsystem uevent usb1
Signed-off-by: make shi <b15407@freescale.com>
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MTD partition for SPI-NOR was not aligned to 8K.
Replace its offset from MTDPART_OFS_APPEND to MTDPART_OFS_NXTBLK.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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USB does not work when plug in a usb device during system suspend. Under this
case, USB driver will be in low power mode, but WIE bit not be set if usb wake
up is not enabled.So there are only ID change interrupt no USB wakeup interrupt
after system resume.In current bsp, after system resume ID change status not be
clear,and ID change interrupt will continue happen, which cause the system busy.
No checking WIR bit if ID change interrupt happen when USB in low power mode to
fix this issue.
Signed-off-by: make shi <b15407@freescale.com>
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Another patch changed caam_ipg_clk's CG to CG4 and this commit will
revert this change.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add HDMIdongle board for imx6Q/DL under board/freescale.
Signed-off-by: Zhang Xiaodong <B39117@freescale.com>
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Fix chip select for SPI-NOR and
remove flags for no writeable partition for weim nor and
SPI-NOR
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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Per hardware design, we can't set LDO bypass mode on Sabreauto board,otherwise,
system will can't reset,if cpu freq run in 400Mhz.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Didn't take more care about non-pfuze board, and there is two place in BSP will
call "mx6_cpu_regulator_init". It means regulator_get will be called twice on
every vddcore/vddsoc regulator. Then one value need set twice ,because from
regulator core view, there is two regulators share the same regulator. The non-
validate one will return error and print "COULD NOT SET GP VOLTAGE!!!!." on
Sabreauto board. The same as Sabrelite and ARM2 board.
Meanwhile, Sabreauto need be configured LDO bypass default.
Signed-off-by: Robin Gong <b38343@freescale.com>
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