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path: root/arch/arm/mach-tegra/Kconfig
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2017-03-31arm: tegra: soc: Use sys_soc to expose SoC UIDBhuvanchandra DV
Use the standard sys_soc interface to expose the SoC UID information. e.g. ~# cat /sys/bus/soc/devices/soc0/machine NVIDIA Tegra ~# cat /sys/bus/soc/devices/soc0/family NVIDIA Tegra30 ~# cat /sys/bus/soc/devices/soc0/revision A03 ~# cat /sys/bus/soc/devices/soc0/soc_id 98317451306464792 Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2013-03-03Conflicts:Marcel Ziswiler
arch/arm/mach-tegra/common.c drivers/ata/ahci-tegra.c
2013-01-24tegra: apalis_t30: initial Toradex Apalis T30 L4T supportMarcel Ziswiler
Tested on early prototype Apalis T30 V1.0a module. Known issues: - ADC not integrated yet. - HDA not integrated yet. - CEC not integrated yet. - IrDA not integrated yet. - Keys not integrated yet therefore no way to wake from suspend. - 8-bit MMC1 slot card detection interrupt not working despite detection GPIO successfully being tested with GPIOConfig. Note: even 8-bit cards work fine if already plugged-in during boot. - PCIe limited to internal Gigabit Ethernet chip for now due to our proprietary way of resetting other ports which requires further integration into NVIDIA's driver.
2012-12-17ARM: tegra3: pm315/beaver: enable Realtek ALC5640 audio codec supportBryan Wu
- select RT5640 ASoC support in Cardhu machine Kconfig - enable RT5640 ASoC driver in tegra3_defconfig - select RT5639 ASoC codec when selecting RT5640, othwise kernel linking will fail Bug 1190823 Change-Id: I1046c30667d4ca8276080f1b3174eccd0b25328c Signed-off-by: Bryan Wu <pengw@nvidia.com> Reviewed-on: http://git-master/r/168884 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2012-11-27tegra: usb: kernel configurationMarcel Ziswiler
Get rid of duplicate USB EHCI ULPI VIEWPORT stuff in Kconfig.
2012-11-12Merge branch 'l4t/l4t-r16-r2' into colibriMarcel Ziswiler
Conflicts: arch/arm/mach-tegra/tegra3_usb_phy.c arch/arm/mach-tegra/usb_phy.c drivers/usb/gadget/tegra_udc.c drivers/usb/otg/Makefile drivers/video/tegra/fb.c sound/soc/tegra/tegra_pcm.c
2012-10-03tegra: colibri_t30: initial Toradex Colibri T30 L4T R16 supportMarcel Ziswiler
Tested on early prototype Colibri T30 V1.0a eMMC module. Known issues: - spurious boot hang after following kernel message [ 5.595219] Timed out waiting for lock bit on pll pll_a - no audio (SGTL5000) support integrated yet - NAND detection/support disabled for now due to boot hang - USB OTG support disabled for now due to boot hang - trying to spawn L4T R16 X driver seems to hang Note: requires uImage with adjusted entry point/load address as follows mkimage -A arm -C none -O linux -T kernel -a 0x82008000 -e 0x82008000 -n 'Linux-3.1.10-colibri_t30' -d zImage uImage
2012-09-10Merge branch 'l4t/l4t-r16' into colibriMarcel Ziswiler
Merge with latest NVIDIA L4T R16. Only real conflict concerning inverted VBUS gpio support.
2012-08-29ARM: tegra: tai: Add tai machine numSeema Khowala
http://www.arm.linux.org.uk/developer/machines/list.php?id=4311 Bug 1002637 Change-Id: Id52214c1780294e4e4a6607b954c05e9be950fdd Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/127978 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29arm: tegra: Set Core to 0.95V in LP1Karthik Ramakrishnan
When the device prepares for LP1, the Core voltage is set to the highest value(1.2V for Enterprise and Kai, and 1.3V for AP37 and Cardhu). This is to set for some of the driver suspend along the sequence need a higher emc frequency and thus a higher Core voltage. Since the sequence of drivers suspend depends on the sequence of their registration in the table, which in turn is platform-dependent, there is no right place in the LP1 entry path where the Core voltage can be set to a lower voltage. Hence, the Core voltage remains high in LP1 resulting in higher power. Thus, the only safe location where the Core voltage can be lowered is once all the drivers are suspended and the DRAM is set in self-refresh, at the final point just before the system is suspended in the IRAM code. This location at the assembly code ensures that no other module will be running and thus that nothing will require a higher core voltage. The Core is set to the lowest possible value since nothing requires it. It is then restored to the highest voltage as soon as the LP1 resume code is started so that all drivers are resumed safely. At the execution point in IRAM during LP1 suspend path, even the I2C clocks are gated. They must be reset first and then the I2C transaction is performed. An I2C transaction involves 4 bytes of data, to send the slave address, the Core voltage register address and 2 bytes of data which has the value to set the voltage(the second byte is not required for this transaction). Once these registers are set, the I2C transaction is performed by setting the I2C transaction register to 0xA02. After sending the I2C transaction, we wait for about 250us to check the status of the transaction and if not updated, wait for more time to check again. If after 2ms and the transaction fails to register, the transaction is aborted and the device is allowed to enter at high voltage. Since the failure rate of I2C transaction is very low at this point in execution where there will be no conflicts in the bus, it is okay to have Core high for some of the LP1 cycles. However, it is unacceptable for the I2C transaction to fail on the way from LP1 resume since the device cannot come up with a lower Core voltage. In this case, the transaction is retried again and again till it is successful. There is no way but to keep trying as the device would fail to resume with Core at 0.95V. Each platform(or each PMU) has different values for the I2C transaction ie. slave address, Core voltage register and the value to set the voltage. For the device in IRAM, it cannot access anything in SDRAM memory, these values needs to be pushed to IRAM memory before the device starts execution in IRAM. This is done during initialization of suspend code when it picks values from the board files and copies it to IRAM part of code, before the whole memory is copied to IRAM. This new feature is controlled by a KConfig variable TEGRA_LP1_950 which should be enabled once the board file of the device is updated with the right values. The device hangs when it does not have the right values for the I2C transaction. With this change in Core, LP1 power is reduced by 12mW in Enterprise, 20mW in AP37 and about 24mW in Kai. Bug 1035684 Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> (cherry picked from commit ab476f287376fd0ae51a9f298659f5eba19f0296) Reviewed-on: http://git-master/r/124779 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-28video: tegra: cardhu: Default bpp from hardwareChristopher Freeman
This patch adds: 1. A kernel config option that hints to DC driver to use the current value of the color depth register as the default for initializing the FB driver. 2. Checks to see if DC is enabled before reading off the color depth register in tegra_dc_probe. Change-Id: I852cc1328fcf42f33052f46b86d753e691744329 Signed-off-by: Christopher Freeman <cfreeman@nvidia.com> Reviewed-on: http://git-master/r/127297 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-08-28ARM: tegra: enable errata 727915 for Tegra3Kirill Artamonov
By-way maintenance doesn't reliably work with enabled lp2_in_idle on Tegra3 platform which uses R3P1_50 revision of pl310. Enable errata 727915 for Tegra3 to avoid system hang. Change-Id: Ia296c1d5b35b8f28353c15d1e4622686bc7d3beb Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-on: http://git-master/r/127225 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-08-20ARM: tegra: e1853: Add build support for E1853Ashwin Joshi
E1853 is T30 based automotive platform. Modify Makefile to support build of E1853 board. Also, added config option to Kconfig file. Bug 966833 Bug 1018258 Change-Id: I18dc015b79256fde1c77947198b426a0060a9017 Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com> Reviewed-on: http://git-master/r/118932 Reviewed-by: Sandeep Trasi <strasi@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User (cherry picked from commit bed57d893803f2ccef8f40bd30bdf1e8a44f184b) Reviewed-on: http://git-master/r/119652 GVS: Gerrit_Virtual_Submit Tested-by: Haribabu Narayanan <hnarayanan@nvidia.com> Reviewed-by: Bob Johnston <bjohnston@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-23arm: tegra: cardhu: IrDA support on UARTBRamalingam C
Adds the IrDA support functions to the platform_data of UARTB on Verbier boards(E1198 and E1186). And also adds a config variable CONFIG_TEGRA_IRDA to control the IrDA support on Tegra. Bug 999895 Change-Id: Iab77c419004292190421d55fd02e249ff98c728e Signed-off-by: Ramalingam C <ramalingamc@nvidia.com> Reviewed-on: http://git-master/r/114930 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-23ARM: Tegra3: clocks: Configurable cbus dividerMohit Kataria
Added config option to set cbus divider. Bug 978870 Change-Id: I49c57064ce695dd703ad97a50b8c0d373f5a05d0 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/114197 (cherry picked from commit 3f2b0e2b973a106d62e1f4bfb75bb40bd1a96b9b) Reviewed-on: http://git-master/r/109962 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-17ARM: Tegra3: clocks: optional se.cbusMohit Kataria
Made se.cbus optional so that se clock can be derived from other clocks and not just from the clocks which drive cbus. Added config option for the same. Bug 978870 Change-Id: I7b5bf405efb58bbb53143f52d2bfe0ebcf6b8322 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/110827 (cherry picked from commit 35e9017b79a3a4b4e0b4098cd2e63ad24018d3de) Reviewed-on: http://git-master/r/106397 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-16ARM: tegra: iovmm: Make IOMMU/IOVMM selectable in KconfigHiroshi DOYU
This patch enables to replace iovmm*.ko family with tegra-{smmu,gart}.ko if needed in kernel config. To use IOMMU as backend engine, Enable TEGRA_IOMMU_{GART,SMMU} under IOMMU in config, and automatically disable IOVMM. IOVMM is equivalent to IOMMU_API. TEGRA_IOVMM_GART is equivalent to TEGRA_IOMMU_GART. TEGRA_IOVMM_SMMU is equivalent to TEGRA_IOMMU_SMMU. Change-Id: I73408e927eb3f21e1db4e73700aaf415f4949166 Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/115011 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-05ARM: tegra: usb: Add config option to increase cpu freqRakesh Bodla
Adding an option to increase the cpu frequency to improve usb gadget transfer rate performance. Bug 923594 Reviewed-on: http://git-master/r/80050 (cherry picked from commit d67b47bbb8322d65f745dcb2226af3f3d582d69a) Conflicts: arch/arm/mach-tegra/Kconfig Change-Id: I4b23fc9948aec37ec58891205ec7dd02f0597af2 Reviewed-on: http://git-master/r/113437 Reviewed-by: Rakesh Bodla <rbodla@nvidia.com> Tested-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2012-07-02ARM: config: Added tegra skin throttling optionJoshua Primero
Added Kconfig option to enable skin thermal throttling. bug 1007726 Change-Id: I8f92172ffd44802f1662c327c02c8a61c523c408 Signed-off-by: Joshua Primero <jprimero@nvidia.com> Reviewed-on: http://git-master/r/105989 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-06-08Initial Toradex Colibri T20 L4T R15 support.Marcel Ziswiler
2012-06-03arm: tegra: p1852: Add i2s/tdm mode selectionNitin Pai
Added code to select i2s vs tdm mode. Added tdm-pcm-audio device defination. Changed the pcm driver to use tdm-pcm-audio device. Added fields to pass the pcm driver name to ASoC. Added P1852_TDM config to KConfig and Linux defconfig Bug 948478 Change-Id: I82fa03ab947cc615089e0a3107fb53901a1c00cd Signed-off-by: Bob Johnston <bjohnston@nvidia.com> Reviewed-on: http://git-master/r/105383 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-01arm: tegra: Enable config NVMAP_CACHE_MAINT_BY_SET_WAYS.Krishna Reddy
Change-Id: Ia6dccfbd0464bc088dfcb05cc16e7f2ad35a9783 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/104291 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-24arm: tegra: Enable arm errata 764369Krishna Reddy
Enable arm errata 764369 for TEGRA_2x and 3x. Bug 981223 Bug 885467 Change-Id: Ie013dc1ed4f1417a72dda72ea2d079a6534c3933 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/104181 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-23arm: tegra: cardhu: add TEGRA_CARDHU_DUAL_DSI_PANEL config optionPreetham Chandru
add TEGRA_CARDHU_DUAL_DSI_PANEL config option to enable or disable dual dsi panel in cardhu Bug 935764 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Change-Id: I9a93386c046f5845a3dcf55c575de6b8e67f188d Reviewed-on: http://git-master/r/96706 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21ARM: tegra: define/enable ARCH_HAS_SUSPEND_PAGETABLEChris Johnson
For Tegra, the CPU suspend code path installs its own 1:1 pagetable setup once at init time. This pagetable is used by all CPUs doing suspend/resume. We want to use the common ARM code for CPU suspend/resume, but don't want the MMU reenable code to patch the current pagetable as it's shared (and could cause problems if the pagetable loads/stores were were interleaved). The installed pagetable already covers the cpu_resume_turn_mmu_on VA, so we're able to just use the existing pagetable. This sets up the CONFIG option to skip this part of the MMU reenable. Bug 929856 Change-Id: Ibbac258122df6def7f7a2d511778a6f11d474938 Signed-off-by: Chris Johnson <cwj@nvidia.com> Reviewed-on: http://git-master/r/92350 Reviewed-by: Sang-Hun Lee <sanlee@nvidia.com> Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Ahung Cheng <ahcheng@nvidia.com> Tested-by: Ahung Cheng <ahcheng@nvidia.com> Reviewed-on: http://git-master/r/103205 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21arm: tegra: thermal: removed TEGRA_THERMAL_SYSFSJoshua Primero
Removed the CONFIG_TEGRA_THERMAL_SYSFS option. Any throttling activities must go through the Linux thermal sysfs framework now via CONFIG_THERMAL. Change-Id: Ibe680d82d3225994e6bebcfe75a0f058e567e35c Signed-off-by: Joshua Primero <jprimero@nvidia.com> Reviewed-on: http://git-master/r/103182 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-04ARM: tegra: Enable ARM errata 716044 for Tegra2.Krishna Reddy
Change-Id: Id71da6f6371f337f913d981f6d121c3fb2561a41 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/95915 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-04-16arm:tegra[3]: power up wifi chip at bootMursalin Akon
power up WiFi chip, if Kconfig option TEGRA_PREPOWER_WIFI is turned on. Bug 956238 Change-Id: I26ef92fee30f8d18a47c3968b9b01b97e52a9382 Signed-off-by: Mursalin Akon <makon@nvidia.com> Reviewed-on: http://git-master/r/90671 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-04-12ARM: tegra: common: Remove T30 A01 SMMU workaroundJuha Tukkinen
Remove CONFIG_TEGRA_SMMU_BASE_AT_E0000000 workaround as T30 A01 is no longer supported. Change-Id: I0ba6c838984e3c3ec401057925727c9596a8075f Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-on: http://git-master/r/95644 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-04-03ARM: tegra3: Make MC early ack feature configurable.Manoj Chourasia
Add a config option to configure early acknowlegement from memory controller. Early acknowledgement is feature of memory controller where MC acknowledged immediately to any write requests from CPU. To maintain mermory coherency all the read requests are blocked till all the early-acked writes have reached to a point of coherency. bug 943638 Change-Id: I97f30261c4711fc338b007502b6eef7217ddb6cb Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/91477 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-28ARM: tegra3: ARM_SAVE_DEBUG_CONTEXT should be selected based on PM_SLEEPManoj Chourasia
ARM_SAVE_DEBUG_CONTEXT was getting selected by tegra3 independent of PM_SLEEP config. ARM_SAVE_DEBUG_CONTEXT itself is dependent on PM_SLEEP. That was generating following warning while doing savedefconfig with PM_SLEEP disabled. scripts/kconfig/conf --savedefconfig=defconfig Kconfig warning: (ARCH_TEGRA_2x_SOC && ARCH_TEGRA_3x_SOC) selects \ ARM_SAVE_DEBUG_CONTEXT which has unmet direct dependencies\ (PM_SLEEP && CPU_V7) This patch fixes the issue. bug 931053 Change-Id: I57016476b7ca39f9ac36a9c59d0102c89c85c6c9 Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/91461 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-23ARM: tegra: Remove legacy i2s/spdif driverLaxman Dewangan
Removing legacy i2s/spdif driver from tree. These files are added to support customer projects prior to moving over to alsa driver for audio. There is no intention of using them and hence removing it. Change-Id: I864dbc50e2e76ac16f40542460f63c8c8a0eff71 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/91758 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-23ARM: tegra: enterprise: enable TI AIC326x codecNikesh Oswal
Change-Id: I941e1140b139240d04906759098249508dbd9535 Signed-off-by: Nikesh Oswal <noswal@nvidia.com> Reviewed-on: http://git-master/r/90056 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-03-12ARM: tegra: Put all Tegra Kconfig entries under if ARCH_TEGRAScott Williams
Change-Id: I49041ada720045908a433b44f301036fc4913462 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/88955 Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-03-08ARM: tegra: Enable CPA.Krishna Reddy
Change-Id: I24725e7d98226e56af7ca06c91c05277a7eb1fdd Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/88443 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-06ARM: tegra: clock: Put Cardhu clocks to known stateJong Kim
Add TEGRA_PREINIT_CLOCKS option to put host1x, disp1, and audio clocks into known state, so that L4T Cardhu works on u-boot. BUG 931602 Change-Id: I7c5aaff340a072fe6587822eccc89df72b2b1d79 Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/86725 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-06arm: tegra: update thermal sensor configurationsHao Tang
Bug 941960 Removed CONFIG_TEGRA_INTERNAL_TSENSOR_EDP_SUPPORT. Add internal tsensor on kai. Change-Id: Iaefa43112fbbaa42d43a428ecb86ad821e683f85 Signed-off-by: Hao Tang <htang@nvidia.com> Reviewed-on: http://git-master/r/84350 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-03-01ARM: tegra: Enable ARM_SAVE_DEBUG_CONTEXTScott Williams
Change-Id: Icbeed86d3fdc04d4ae7e3c129a707ceba6f61fba Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/86159 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-01arm: tegra: cardhu: add support for max98095Ravindra Lokhande
add support for maxim 98095 audio codec Change-Id: I112130341363e18986158cd94a981a60a80fb0d0 Reviewed-on: http://git-master/r/75956 Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com> Reviewed-on: http://git-master/r/85485 Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-02-24ARM: tegra: cardhu: enable TI aic326x codecNikesh Oswal
Change-Id: I05f436146def9a2a7f55ff3fa1af6b560d3b289c Signed-off-by: Nikesh Oswal <noswal@nvidia.com> Reviewed-on: http://git-master/r/84541 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-23ARM: tegra: power: Power off multiple CPUs on-lineAlex Frid
Currently on Tegra3 cpu complex is powered off in idle (enters CPU0 LP2 state) only if all secondary CPUs are off-line. This commit adds an option for CPU0 to enter LP2 while secondary CPUs are still on-line but have been power gated and entered LP2 state by themselves. The critical race: secondary CPU is waking up from LP2, while CPU0 is turning common CPU rail off, is addressed as follows. 1. When entering LP2 state on CPU0: a) disable GIC distributor b) check that CPU1-3 are all power-gated (i.e., either off-lined or have entered LP2) c) if (b) passes - set all interrupts affinity to CPU0, then re-enable distributor and continue with CPU complex powering off d) if (b) fails - re-enable distributor and enter clock-gated (LP3) state on CPU0 This procedure prevents waking secondary CPUs by GIC SPIs. 2. We still need to make sure that no CPU1-3 PPIs from legacy IRQ/FIQ or private timers would happen. This is achieved by disabling timers and legacy interrupts if CPU1-3 enters LP2 state with external timers selected as wake sources. Respectively, establish dependency between turning rail off and LP2 wake timers configuration options. 3. Finally, no IPIs is sent by CPU0 entering LP2. There are no special changes in wake up procedures - whenever CPU0 is awaken by external interrupt or wake timer, cpu complex is powered on by h/w, and secondary CPUs that were in LP2 state are ungated by the same interrupt (off-line CPUs are kept power gated). Hence, there is no need for CPU1-3 external wake timers to run while the rail is off, and these timers are stopped. To make sure that none of secondary CPUs over-sleeps its LP2 time, CPU0 wake timer is set to minimum sleep interval of all CPUs. By default configuration option for powering off multiple on-line CPUs is disabled on Tegra3. Change-Id: I4920d0df375536b2b8ebd9e6738c5fe4f92b92a0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/83547 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-02-17ARM: tegra: power: Add external LP2 wake timers on secondary CPUsAlex Frid
Add an option to use external timer as Tegra3 secondary CPU wake source from lp2 (power gated) state. This is a follow up to commit 51e6be9ce103fbeb2b73fa2a9d2b6528a6941e81 that disabled wake from external timer, since its interrupt is registered too late - after secondary CPU is brought on-line, and already had a chance to enter lp2. With this commit, secondary CPU is not allowed to enter lp2 in idle until wake timer is registered (clock-gated lp3 state is entered instead). External timer wake up mechanism is enabled on Tegra3 only if option HAVE_ARM_TWD is not selected. Otherwise, continue to use local CPU timers as lp2 wake sources. Change-Id: Ic8c33f55e77174717bfa6525041e1263d3232dd5 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/83546 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-14arm: tegra: kai: Add ALC5639 audio codecRakesh Iyer
Changes made to add support of ALC5639 codec for kai. Bug 931371 Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Reviewed-on: http://git-master/r/77954 (cherry picked from commit 8e3e4e00a97759983a0a2e3a2c4d9d4d367ed950) Change-Id: I899b31fc416d75875456fe7809e0dce6f2e78ffa Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/82736 Reviewed-by: Chandler Zhang <chazhang@nvidia.com> Tested-by: Chandler Zhang <chazhang@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-02-09arm: tegra: Reduce coresite clock frequencyScottPeterson
Source coresite clock from clk_m and reduce its frequency to 1Mhz to reduce the power consumption on csite module. BUG 922351 Signed-off-by: ScottPeterson <speterson@nvidia.com> Reviewed-on: http://git-master/r/76287 (cherry picked from commit 80c11f4c789efea49b30b8731711aa4c20d7630c) Change-Id: If8a75924229c8d6aae4fd449eff6ae2e194a6e45 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/79995 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-02-09ARM: tegra: p1852: Add board support files for p1852Amlan Kundu
bug 871603 P1852 is a T30 based Automotive platform. Signed-off-by: Amlan Kundu <akundu@nvidia.com> Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/72253 (cherry picked from commit 98d50016e70a22ae7e8e109cfb6633a8fe75f905) Change-Id: Iede9881fc1168bb6802694e233554d84adfb8f44 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/79981 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-02-03ARM: tegra3: Enable workaround for ARM_ERRATA_754322Scott Williams
Reviewed-on: http://git-master/r/77830 Change-Id: If1fbb73eff40dafdb7bcbe8da451115ef2105b0b Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78441 Reviewed-by: Automatic_Commit_Validation_User
2012-01-30arm: tegra: kai: create board filesJohnny Qiu
Create initial board files and config files for Kai. Reviewed-on: http://git-master/r/74441 Change-Id: I4b07607da85fe4bcb00e5fce2ddbc2a83471b1de Signed-off-by: Johnny Qiu <joqiu@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77296 Reviewed-by: Automatic_Commit_Validation_User
2012-01-16arm: tegra: Fix Kconfig dependency error if SMP is deselectedScott Williams
Change-Id: I080b7f29bccc9fada4a204dafed483bfcf7650ed Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/74612 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Reviewed-on: http://git-master/r/75145 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2011-12-27ARM: config: enable profiling memory controller by defaultLiang Cheng
bug 918997 Change-Id: I134ac6b40a9af40edca6dc902af604da32cfdc2b Reviewed-on: http://git-master/r/71698 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2011-12-22arm: tegra: power: add watchdog recovery functionKamal Kannan Balagopalan
Add watchdog recovery mechanism to protect against hangs during driver suspend/resume sequence Bug 857748 Change-Id: I03d540b38318a5a953b1a697af123291b48991e9 Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com> Reviewed-on: http://git-master/r/65986 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-31 14:53:27 +0000