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path: root/arch/arm/mach-tegra/Makefile
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2010-11-15[arm/tegra] cache kfuses on boottegra-10.9.5Jon Mayo
Cache the fuse contents early in boot before DMA is active to ensure exclusive access on that bus. This cache is exposed at /sys/firmware/fuse/kfuse_raw and it can be read() or mmap()'d. Bug 741232 Change-Id: I83bc991c89beb837ec22b2e03ceac11ab696cb6f Reviewed-on: http://git-master/r/10482 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2010-10-05[arm/tegra] provide wifi power/carddetect abstractionRakesh Kumar
When user switches on wifi, wifi driver need to poweron wifi card and ask sdhci stack to enumerate the card. Sdhci stack does not provide any interface to achieve this. Major wifi vendors depend on platform to provide wifi poweron/reset/carddetect abstraction function. Bug ID 739374 Change-Id: I988393352ff6cb54be3d70a59c94f67eedff06fb Reviewed-on: http://git-master/r/7097 Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> Tested-by: Rakesh Kumar <krakesh@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-07-13tegra: Re-partition CPU hotplug and LP2 codeScott Williams
Repartitioning so that core-specific, SOC-independent code is located in cortex-a9.S, SOC-specific code is located in headsmp-t2.S, and SOC-independent code is located in headsmp.S. Change-Id: I445df2ef4296e9486ad0f86450f8e2dac06cae12 Reviewed-on: http://git-master/r/3840 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-21tegra: Separate CPU-specific and SOC-specific suspend codeScott Williams
Change-Id: I9e4cd3da4a4b2f124241fd5cc7d713f117d8ec7c Reviewed-on: http://git-master/r/2831 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-11tegra: Move SOC-specific pinmux data to SOC-specific filesScott Williams
Change-Id: I9bb3607e9605eefd5c0eec07a8be3fafce9bae64 Reviewed-on: http://git-master/r/2528 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11[ARM/tegra] rename cortex_a9_save to tegra2_saveGary King
more of the code in this file is tegra power-state specific than common CPU save and restore routines, so rename it to reflect that it won't run on non-Tegra SoCs Change-Id: I22643da41309b48a7f85e62407ec8b7d9f75baff Reviewed-on: http://git-master/r/2244 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11[ARM/tegra] suspend: add scratch register mapping for tegra 2 LP0Gary King
to restore from LP0, a large number of memory, arbitration and PLL settings need to be preserved in scratch registers in the AO domain for the boot ROM to reload them after exiting LP0. Change-Id: Ic446ef47c3cba9b792dd7b86b176157757504bde Reviewed-on: http://git-master/r/2154 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-09[ARM/tegra] move MC error interrupt out of NvRmGary King
MC error interrupts are useful debug features, so implement them separately from the RM; also, enhance the printouts to include the client name, so that cross-checking the status value against a separate list isn't necessary Change-Id: I9aa2857388bf252bbcd2f3048eae0fb63d90a011 Reviewed-on: http://git-master/r/2280 Tested-by: Gary King <gking@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-07[ARM/tegra] add cryptographic engine (AES) driverGary King
Supports CBC & ECB encryption/decryption, AnsiX9.31 RNG, SSK/SBK/User Key, fine-grain uid/gid access control and ability for privileged user to reset the engine. A device node (/dev/nvaes) is provided to enable access from user-land. based on work done by David Le Tacon (dletacon@nvidia.com) Change-Id: I1a9c29b964ca15e6fec70389c2000306ef604086 Reviewed-on: http://git-master/r/2216 Reviewed-by: David Le Tacon <dletacon@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-05-28[ARM/tegra] add a vibrator timed_output driver for tegra ODM kitGary King
Change-Id: I82b4c5b61f6a52ae3ebc93a28219c15da446b040 Reviewed-on: http://git-master/r/1831 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-05-27tegra-kernel-fuse: Add fuse burning support from Linux via sysfsVenu Byravarasu
A fuse module is added to support programming and reading back fuse values. This module is built as part of kernel. Bug 657504 Tested on: Whistler Change-Id: I5663679c8d41834aa4077e9940a0595f6575af64 Reviewed-on: http://git-master/r/1259 Reviewed-by: Andy Carman <acarman@nvidia.com> Tested-by: Andy Carman <acarman@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-05-26[ARM/tegra] add cpufreq driverGary King
tegra cpufreq uses the dynamic voltage and frequency scaling code in the tegra RM to update the CPU and bus clocks on-the-fly, and to dynamically add and remove CPUs from the SMP cluster. this code runs in a background kernel task named cpufreq-dvfsd. all of the resources needed for cpufreq are allocated during kernel initialization; however, starting the DVFS thread is deferred until tegra_start_dvfsd is called (triggered by a user-space action, such as opening the RM device node, an ioctl on the RM device node, or writing to a sysfs node), because running the DVFS daemon during kernel init causes numerous problems Change-Id: I113e6a71b2405e9f33b9ec4912ff40d229d96a02
2010-05-23[ARM/tegra] add PCI driverGary King
Change-Id: I89e73a9247d48ddb808065f0f697b9fabcfc2901
2010-05-19[ARM/tegra] add nvec embedded-controller transportGary King
Change-Id: I8471465a765f07b76cfb41e79a746d86145095c3
2010-05-18[ARM/tegra] initialize debug console based on ODM query valuesGary King
add a new board file for initialization of platform data and registration of platform devices based on ODM-queried values, rather than compile- time constants. add debug console (UART) initialization to it. Change-Id: I592cea3b714b03d3e122ad46d12305c43c9e382f
2010-05-17[ARM/tegra] export most NvRm functions to kernel modulesGary King
Change-Id: Ifa3a208a1c091b4d20a4895edd8b9e0e69340f5b
2010-05-17[ARM/tegra] add nvrpc interface to NvRmTransport APIsGary King
Change-Id: I5ba8e15ff8b4ad49909d61222be6df8eb66d8867
2010-05-16[ARM/tegra] refactor platform_device registrationGary King
separate SoC from platform-specific initialization, so that common code (MMIO resources, interrupts, etc.) can be shared across platforms Change-Id: Ia29fb04d868d834e168c6739d996b9fc6cf4d11c
2010-05-16[mtd] add NAND device MTD block driver for Tegra SoCsGary King
Change-Id: Id38598e0a63b3f723cc07933c54bf5a99781ad0a
2010-05-16[ARM/tegra] nvrm: add NvRm-based clock supportGary King
when CONFIG_TEGRA_NVRM is selected, implement the clk_* functions using the RM's clock control APIs clock support currently limited to RTC, KBC and UART devices, and to querying the pclk, hclk, sys, cpu and pll_p clocks. Change-Id: Ibd0d7e67ac344594451db3964ec0dfba75c78779
2010-05-14[ARM/tegra] add nvreftrackGary King
add nvreftrack framework Change-Id: Ie4e0e1605d30dce07cbef24585af4b0376c49ee8
2010-05-14[ARM/tegra] add NvRm, ODM services, ODM kit for harmony & whistlerGary King
add power rail support to GPIO driver Change-Id: I45d4c1110a635047d68fb14f3e72a28f99acbe1b
2010-05-12[ARM/tegra] add NvOsGary King
integrate files from android-tegra-2.6.29 branch to build NvOs changes from previous branch: * nvos_ioctl.h moved to top-level include/ directory * tegra ATAG value and structure declaration moved to nvos.c * cache and memory fence calls updated to match new kernel APIs * PhysicalMemMap and PhysicalMemUnmap just call ioremap, which handles static vs dynamic remapping internally. Change-Id: I13d7b7068c12d73a4cf3d810a0e3ea6b21e3805c
2010-05-05[ARM] tegra: Add arch-specific udelay using TMRUSColin Cross
Change-Id: Ie59462e60b2f4c2f652a79d86fc106e915609600 Signed-off-by: Colin Cross <ccross@android.com>
2010-05-05[ARM] tegra: implement gpio_request and gpio_freeGary King
ensure that the pad group containing a requested GPIO is not in tristate before clients use it. add a tegra 2-specific table to map from the GPIO number to the pad group which contains it Change-Id: Iab930ac0df27735190d5b1eca5becb5e584d99d6
2010-05-05[ARM] tegra: add voltage rails and safe resets to the pin group tableGary King
the reset values for some pin groups in the tegra pin mux can result in functional errors due to conflicting with actively-configured pin groups muxing from the same controller. this change adds a known safe, non- conflicting mux for every pin group, which can be used on platforms where the pin group is not routed to any peripheral also add each pin group's I/O voltage rail, to enable platform code to map from the pin groups used by each interface to the regulators used for dynamic voltage control Change-Id: I66f061ab81d470f23ca71150397b4c5bbdbf8a21
2010-04-21[ARM] tegra: add I/O virtual memory manager interface (iovmm)Gary King
Change-Id: Ib0350fdc71ceac5bc9a12acae3d7a89b896c4133
2010-04-20[ARM] tegra: add APB DMA supportGary King
Change-Id: Ie7bfae5cc8a0d01f46556f1beebe3d00e4465dc5
2010-04-15[ARM] tegra: add CPU_IDLE driverGary King
supports clock-gated (LP3) SMP idle mode, and power-gated (LP2) idle mode when all slave processors are off-line latency for LP2 idle state is calculated as a 2-sample weighted moving average, to allow for future variations due to (e.g.) CPU frequency scaling. when LP2 is an allowed state (i.e., slave CPUs have been taken off-line), LP3 will perform an hrtimer peek-ahead; this avoids waiting for the first processor tick following an LP2 in order to run expired hrtimers (which was causing a 1 tick delay for most user-space sleeps) LP2 wakeup time and latency uses a 2ms hard-coded offset to account for the CPU powergood timeout; this is reasonable for Harmony but should be un-hardcoded for other platforms. Change-Id: Id0c8846d81b113086790961dd06c8dd182a8fc44
2010-04-15[ARM] tegra: add LP2 idle-mode supportGary King
LP2 idle mode power-gates the main CPU complex, requiring a full processor state save and restore from a reset vector processor context area is allocated during platform initialization from the kernel, and mapped into the hotplug page tables (which also serve as the initial page tables for the LP2 main processor reset) restoring the processor from LP2 requires calculation of a system- and APB-clock-dependent CPU power good timer value. on Harmony, 2ms is a good baseline value for this, and the APB clock is running at 13.5MHz. these values need to be un-hardcoded for other platforms. Change-Id: I70a18a1d995e1d34da64d60fbdcd4568ef442f0c
2010-04-08[ARM] tegra: CPU hotplug supportGary King
to save power, SMP tegra SoCs place non-boot CPUs in reset when they are removed from the scheduling cluster using CPU hotplug. slave CPUs save their contexts (incl. CP15 and VFP state) out to a reserved memory region, cancel SMP operation, and write to the SoC reset controller to disable themselves. this is done with caches and MMU enabled, so care is taken to ensure that all the dirty context cache lines are cleaned out to the PoC before shutting down. when re-enabled, slave CPUs execute a hotplug boot routine which mirrors the initial configuration performed by secondary_startup, but after enabling the MMU "return" to __cortex_a9_restore which restores the saved state from the context area, and returns to platform_cpu_die. in pseudo-code, the hotplug startup routine is basically: * invalidate i-cache, BTAC, TLB, exclusive monitor * enable i-cache, branch prediction * invalidate d-cache * invalidate SCU tags * enable SMP * setup page tables to secondary_data.pgdir * enable MMU & d-cache * restore CP15 from context area * change page table pointer to context from shutdown * restore stack registers * return to platform_cpu_die Change-Id: Ic098d82772af9ab2c97f9030d7a993c6a876785d
2010-04-08[ARM] tegra: add generic (will be ODM kit) board fileGary King
Change-Id: I7550f2b937fbc5a0caab200cae585f193e7c175a
2010-04-08[ARM] tegra: add GPIO supportErik Gilling
v2: Fixes from Mike Rapoport: - move gpio-names.h to arch/arm/mach-tegra v2: fixes from Russell King - include linux/io.h and linux/gpio.h instead of asm/io.h and asm/gpio.h Signed-off-by: Erik Gilling <konkers@android.com> Signed-off-by: Colin Cross <ccross@android.com> Cc: Gary King <gking@nvidia.com>
2010-04-08[ARM] tegra: Add timer supportColin Cross
v2: fixes from Russell King - include linux/io.h instead of asm/io.h Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
2010-04-08[ARM] tegra: SMP supportGary King
Change-Id: I630e65a8779c428a26b5575bf9cb9eb0d81aa588 Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com> Conflicts: arch/arm/Kconfig
2010-04-08[ARM] tegra: Add clock supportColin Cross
v2: fixes from Russell King - include linux/io.h instead of asm/io.h - fix whitespace in Kconfig - Use spin_lock_init to initialize lock - Return -ENOSYS instead of BUG for unimplemented clock ops - Use proper return values in tegra2 clock ops Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
2010-04-08[ARM] tegra: Add IRQ supportErik Gilling
v2: fixes from Russell King - include linux/io.h instead of asm/io.h and mach/io.h Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
2010-04-08[ARM] tegra: initial tegra supportGary King
Change-Id: I70a48fdf4b3a9dead90cbb7fb914e4b52f0cdd40 v2: Fixes from Mike Rapoport - remove unused header files (mach/dma.h and mach/nand.h) - remove tegra 1 references from Makefile.boot v2: fixes from Russell King - remove mach/io.h include from mach/iomap.h - fix whitespace in Kconfig v2: from Colin Cross - fix invalid immediate in debug-macro.S Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com> Conflicts: arch/arm/Kconfig arch/arm/mm/Kconfig
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-17 14:35:20 +0000