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disable the usb1 vbus gpio in kernel and not depend on bootloader
to disable the vbus initially.
Currently, the kernel enables and disables the vbus when
the otg is configured to host mode, but when the system boots
with no cable connected the kernel relies on the bootloader
to turn the vbus off.
This CL removes that dependency.
Bug 1047048
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/#change,141970
(cherry picked from commit c3461995dd156968d766ec05879fd1097221ceb8)
Change-Id: I96c1f4b97a2cafdfd498b591647200d26298a43b
Reviewed-on: http://git-master/r/142839
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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Corrected Mux option for LPW2
Bug 920686
Change-Id: I1e93a28c070ca7689c305d84ed8664c3f170bfcb
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/101959
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Setting drive strength to maiximum for all i2c pins.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/91952
Change-Id: I8882dd238af34e06c924f2e160d0897111e8103d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/100260
Reviewed-by: Automatic_Commit_Validation_User
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1) configuring wf_wakeup gpio
2) create resource wifi_resource and provide it to wifi driver
bug 902633
Change-Id: Ie35a492b89abd64073f3d4ec7eb366c02cd47b31
Reviewed-on: http://git-master/r/64487
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R3c9362bccd0ac9aea3e788af3b5266e386f33e60
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Change-Id: I156af0bdd8b37cb23aec214c3e158027252e27e1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/51157
Rebase-Id: R795bf03590a76b6c494afd37603ed951dc2cd082
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Bug 868608
Bug 862023
Change-Id: I0f902098fc9cabd9d8c4962cf73c758df99a3199
Reviewed-on: http://git-master/r/49459
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rea8335719e3f20cdb645d22c19da3d61d52d4eaf
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Fix ventana_pinmux_init() prototype.
Change-Id: Iaa42bcc80dea5b6ac4cb7a1a7680366eb13daf55
Reviewed-on: http://git-master/r/49682
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Rebase-Id: R8659b257c3436601078a3336d718af09c1aebe83
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The pin-func set by board-xxx-pinmux.c should be one of the 4 possible
values of the pin-func in master pinmux table. Also the safe pin-func
setting should follow the same rule.
If this is not followed then, warnings will be seen whenever a driver
tries to set a pin-func that is not in the master pinmux table. This is
specically seen for the mux values RSVD_X.
The hardware is always programmed with the bit value of setting
(00, 01, 10, 11) which is the position (0, 1, 2, 3) in master pin-mux table.
For bug 865503
Change-Id: I3933ca0002e099376798cc131690922fefa16868
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/48197
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R9177fb046ede6bd39b98904d25a18622b72d4ce6
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Current Ventana flash designed is connected to VI GPIO pin.
GPIO can't control as expected if we didn't set it to correct
Pinmux group.
Original-Change-Id: I77277f268c4086e135c2852bcb5a430bd3a3d2ca
Reviewed-on: http://git-master/r/24094
Reviewed-by: Shan Neng Chen (Engrg-HW-Media & Commns Prcsng) <snchen@nvidia.com>
Tested-by: Shan Neng Chen (Engrg-HW-Media & Commns Prcsng) <snchen@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rc97d8229cb97972f1d430146501cebe6fd540783
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Change the i2c pins pupd to normal because internal pull up
are present. gen1_i2c(rm), cam_i2c(dtf), gen2_i2c(pta),
pwr_i2c(i2cp) and ddc_i2c(ddc) are respectively pulled up to
vddio_uart, vddio_vi, vddio_nand, vdd_1v8 and vddio_hdmi
bug 788286
Reviewed-on: http://git-master/r/26695
(cherry picked from commit 617e288c1f7adca21b33e56ff124fde317eaaecd)
Original-Change-Id: I4ca5b76616b7664c2b9bd49c9bfc7988d8de0a0f
Reviewed-on: http://git-master/r/26831
Reviewed-by: Alok Chauhan <alokc@nvidia.com>
Tested-by: Alok Chauhan <alokc@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rff8c97abb43b92356f50fd3cae9eb5ca19aedd75
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The drive pin groups for i2c are DBG(GEN1_I2C), VI2(CAM_I2C),
AT1(GEN2_I2C) and AO1(PWR_I2C). As there are no entries in
tegra_soc_drive_pingroups table for DTF, I2CP and RM, pg_readl()
and pg_writel() use '0' as reg offset while configuring i2c drive
pin groups.
Original-Change-Id: Ide6aa68ad0d7247791169f1b3e6c84b324c1dfcf
Reviewed-on: http://git-master/r/23831
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Rebase-Id: R48299d59c3865ff80431d04a51df89f03669ff93
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Current MCLK is output with 12Mhz rather than 11.2896Mhz. Fix it by
pinmux modification.
Bug 796690
Original-Change-Id: I20399ad14c4a8a5e14ac82f31325523a0bac9727
Reviewed-on: http://git-master/r/22044
Reviewed-by: Ching Kuang (Roger) Hsieh <rhsieh@nvidia.com>
Tested-by: Ching Kuang (Roger) Hsieh <rhsieh@nvidia.com>
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Rebase-Id: Refcd65902c3dad9b0672625807d61f7718ed5655
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Add the code to change drive strength of individual pin group and
increase the drive strength to max for i2c pin group. Change the
i2c pin to pull up.
Original-Change-Id: I9ab84717a9ff6df78fa6c242420744d05ce09723
Reviewed-on: http://git-master/r/20745
Tested-by: Alok Chauhan <alokc@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rd0892cc386f844617d5bfc8d23a1e1d51dad7e8c
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for bug 789783
Original-Change-Id: I3b1b950afad6ed0f4af823fdf889859182a8b1f7
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/20562
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Ra611608b5961cfd4989ad032acee68613047ef0b
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Correcting the pinmux table for USB1 and USB3 vbus lines
on ventana.
Bug 770041
Original-Change-Id: I12266cafd4720959302ccb0fb29e29115e0de114
Reviewed-on: http://git-master/r/20022
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R8fde662dee16f4e1059218280691b21870d561e1
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This code is off by default.
By default Ventana's buttons are GPIO pins.
But it is possible to connect it to kbc controller
(simple hardware rework needed).
This code might be used as a reference code for using kbc driver.
Original-Change-Id: Iaad4b8ca4b1bf6da1674e282f3bfb86349927fbd
Reviewed-on: http://git-master/r/9801
Tested-by: Victor Ryabukhin <vryabukhin@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rec5eaab861c97d7b363b796db96b8eb181d38782
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Bug 696035
Original-Change-Id: Iafb02b1d4e6a8784e85cf7a48b1c674b71b4eb15
Reviewed-on: http://git-master/r/12640
Tested-by: Rajkumar Jayaraman <rjayaraman@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Refb27a8e730c8bb8837dde8233a798d36cd494cd
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-board-ventana-pinmux.c: change following pin groups
to TEGRA_PUPD_NORMAL and TEGRA_TRI_NORMAL
TEGRA_PINGROUP_CSUS,
TEGRA_PINGROUP_DTE and
TEGRA_PINGROUP_GPV
-board-ventana-power.c: tegra_camera is connected to
regulator LDO6 (vcsi) and it should be max 1800mv
-board-ventana.c: add platform device tegra_camera
Original-Change-Id: Ie83a9a34d72ba584673634dccf72c6cc0f25c74c
Reviewed-on: http://git-master/r/11336
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R92b15f626cb274d3a7b0d5bf8a49afbfc85f8a7e
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Note: The current mirroring mode seems to require both the
internal and external panel to be set at 1280X720. Since
ventana uses 1366X768, the HDMI monitor shows corruption.
Original-Change-Id: Iec0ce9fd92d6cd7050e881a1af6fa7e1ace92280
Reviewed-on: http://git-master/r/11655
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R46aa4ae04a2380bded8643c955551b4925fef0ca
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register the tegradc0, tegradc1, grhost, pwm-backlight and carveout
devices
Change-Id: Ia61c0632470e571cc57279dc3b197ccd1fca80f0
Signed-off-by: Gary King <gking@nvidia.com>
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Fixes by Anantha Idapalapati <aidapalapati@nvidia.com> and
Mayuresh Kulkarni <mkulkarni@nvidia.com>
Change-Id: Ib7599d3593a8cc19b5b6dce451f3b203d4c5b70f
Signed-off-by: Gary King <gking@nvidia.com>
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configure the drive pinmux for wifi and i2c, and configure
the tristate and pullups for the wifi pins correctly
Change-Id: I40cddea16aa66e3a286c7ccc93677d5459ae3717
Signed-off-by: Gary King <gking@nvidia.com>
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Change-Id: I5f844fd58a379cb7191f03bb23599cd4061caf5c
Signed-off-by: Gary King <gking@nvidia.com>
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Change-Id: I1993fda7628c623d53fd2c97649ec3533ad790e2
Signed-off-by: Gary King <gking@nvidia.com>
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