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path: root/arch/arm/mach-tegra/clock.c
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2012-05-14ARM: tegra: clock: Export clock minimumAntti P Miettinen
Add clock minimum to debugfs. Bug 917644 Change-Id: Ie088809829af2bdc81a969a034bf00847459f0ce Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/101555 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-09Revert "ARM: tegra: clock: Don't fail clk_enable when max_rate has been lowered"Alex Frid
This reverts commit 8d351aa5478de533114e614f2607bc85ed23df91. The above commit introduced recursive call of clk enable/set rate APIs that may hang the system. Change-Id: I04eff9e1c3ddee82f6d2e17690122cc41fad203f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/100710 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-07ARM: tegra: clock: Add locked version of round rateAlex Frid
Add locked version of round rate API to be used by tegra arch specific layer. Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 457627966b91f2141439812869adc4acf9242471) Change-Id: Id68d0bb952d1e7d9e650341872d1b06b0b2d3cea Reviewed-on: http://git-master/r/100474 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-02-03ARM: tegra: clock: Expand PLL usage restriction mechanismVarun Wadekar
Expand PLL usage restriction mechanism from Tegra3 only to common tegra clock framework implementation: fail set parent API if new parent is not allowed per usage policy. Actual usage policy is architecture dependent and exists now only on Tegra3. Reviewed-on: http://git-master/r/77251 Change-Id: I2a8d60cc0ddfd2179961ef50418b193f2e1829c8 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78029 Reviewed-by: Automatic_Commit_Validation_User
2012-02-03ARM: tegra: clock: Check usage policy when set cansleepAlex Frid
Check PLL usage policy when traversing clock tree for descendants of sleeping clock. Don't propagate cansleep attribute if parent is not allowed. Reviewed-on: http://git-master/r/77252 Change-Id: Ibe79888d378924f416f8458146b21d1bc3671f16 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78028 Reviewed-by: Automatic_Commit_Validation_User
2012-01-16ARM: tegra: clock: Expand shared bus debugfs entriesAlex Frid
Added possible rates debugfs entries for shared buses. Change-Id: Ibe2ae38b1667599988397633d03ece534f840a31 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/73895 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/75148 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2011-11-30ARM: tegra: clock: Enable EMC scaling for AP25Prashant Gaikwad
Workaround added to enable EMC scaling for AP25. PLL switching support added for 300MHz EMC scaling step. Bug 892505 Reviewed-on: http://git-master/r/#change,41718 Reviewed-on: http://git-master/r/#change,41720 Reviewed-on: http://git-master/r/#change,60861 Change-Id: I885b8dc4e3b6124ebed572c06cea773de6c83471 Reviewed-on: http://git-master/r/64465 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: Rb8e58cfa7fe1106978030c8aea292e95a7a5da2b
2011-11-30ARM: tegra: clock: Re-factor shared bus lockingAlex Frid
Current code: - on tegra2 unnecessary covers with bus lock shared user state update - on tegra3 does not cover shared bus rate update at all Modified to cover with bus lock shared bus rate update only on both tegra2 and tegra3. Change-Id: Iaa2597136a521adf4285c61eb579c917c2c7965c Reviewed-on: http://git-master/r/55640 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R1b28f32ae37d47c56855023b18c943bf8fd93c74
2011-11-30arm:tegra: Add EXPORT_SYMBOL and ioctls for test frameworkRahul Mittal
Added EXPORT_SYMBOL to functions to be used by loadable kernel module for audio test framework. Also added ioctl declarations for the same. Change-Id: Id8a023c1d76fd031c042c7c663bb0e1df2d33b5c Reviewed-on: http://git-master/r/52333 Tested-by: Rahul Mittal <rmittal@nvidia.com> Reviewed-by: Vijay Mali <vmali@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> Rebase-Id: Rfdc9fd3b9a42b2ee601c273480f9986ab897f046
2011-11-30ARM: tegra: clock: Use bus lock to protect shared bus updateAlex Frid
Protected shared bus update with bus lock - common for all shared bus users (update procedure was already covered by individual shared users locks, but it did not prevent concurrent access to shared rates list). Original-Change-Id: Ia0e6886265aff1f624802e0415fe8cecb887b507 Reviewed-on: http://git-master/r/39918 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R0e0ee997ce9347470e207910f7b4f6c42143717f
2011-11-30tegra: clocks: Fix in clock settingsmchourasia
clk_disable_locked should not be called when clk_enable_locked is failed. Original-Change-Id: I2524ec0198f62de2487723676ca7657d15757eda Reviewed-on: http://git-master/r/38273 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R1598bf84619449922c599d611a84dec791047837
2011-11-30ARM: tegra: sysfs write permission for user onlyManoj Gangwal
Giving read-write permission for user only for sysfs attributes. Group and other will have only read permission. -clock: syncevents Bug 828100 Original-Change-Id: I14affc209e954a58de055e291093e31dc1dbfe16 Reviewed-on: http://git-master/r/39364 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R97f4eadb711717e788be7c4e4e8993d048cf1428
2011-11-30ARM: tegra: power: Refactored kernel powergate codeKaran Jhavar
This change provides a centralized location for powergating modules. It would take care of switching on/off clocks while un-powergating/ powergating modules respectively. Bug: 814267 Original-Change-Id: Ic80dc517f634c29085c8e089bdaa32c6fd742710 Reviewed-on: http://git-master/r/31776 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Rc0aac0edd4e693c15d22d998c882fceeeb85765d
2011-11-30ARM: tegra: clock: Add shared bus users rate printoutAlex Frid
Original-Change-Id: Icb1a5028d575155427f1fd7fa5b3ee2a145934f4 Reviewed-on: http://git-master/r/38421 Tested-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Gerrit_Virtual_Submit Reviewed-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Rebase-Id: Rf473061330e8b6d63948c9a0ed247e37e3534a52
2011-11-30ARM: tegra: generate status events for all clocksPeter De Schrijver
Original-Change-Id: I55f52ab038764079811c68b3bb3738a9de17d7bf Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-on: http://git-master/r/31530 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R25afcccf5ff8d7a88b705ce7f68ab83e818ae1e4
2011-11-30ARM: tegra: sysfs write permission for user onlySachin Nikam
Giving read-write permission for user only for sysfs attributes. Group and other will have only read permission. - tegra_mc_stats: enable and quantum - susend: mode - clock: rate, parent, state File System Permission CTS expects this to pass. Bug 840409 Original-Change-Id: I3335b27124be38f0f5ea4cc415fef6532e574680 Signed-off-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/36867 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R3360698aa910479a0eccb460656d104912af99bb
2011-11-30ARM: tegra: clock: Add clock rate change notificationAlex Frid
Original-Change-Id: I97434334a4214180a365d9709a331405da135669 Reviewed-on: http://git-master/r/36202 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R7bfea35bf7b2e083e594538e245e3b74e25d090a
2011-11-30ARM: tegra: clock: Synchronize Tegra3 clocks scalingAlex Frid
On Tegra3 clocks of major h/w engines - 2D/EPP/3D/MPE/VDE/SE - are sourced from PLLC through integer dividers. Low resolution of these dividers does not allow to set scaling frequency levels matching intermediate voltage steps within core voltage range. Only changing the source frequency can achieve it. However, re-locking common PLL while engines are running requires synchronization of engines clock control, and complex operations including switching to backup sources during PLL stabilization time. This commit introduces a new virtual clock "cbus" to support clocks synchronization and PLLC re-locking procedures. The dvfs table for cbus clock is constructed from frequency steps close to maximum rates for each characterized core voltage level. Engine clocks exposed to the drivers are no longer physical module clocks, but shared cbus users. Setting the rate for such clock specifies the clock floor. The final cbus rate is determined as maximum floor setting for all enabled engines, and rounded up along the cbus dvfs ladder. Actual engine clock rate is set equal to the cbus clock rate. Hence, engines will be running close to maximum frequency for minimum voltage that satisfies all floor requests. Special case: Host1x. This clock will be always configured at 1/2 of cbus clock rate, and its shared user floor request is ignored by cbus target frequency calculations. Added cbus dvfs tables and updated VDE engine dvfs data. Original-Change-Id: Ic02ea08227f920dc4f47b2389c311a23cea472f6 Reviewed-on: http://git-master/r/36199 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R1b7556f1cca12987e4f7c8c6342778da1cec1915
2011-11-30ARM: tegra: Fix mutex in atomic context when updating TWD freqScott Williams
The CPU frequency change notifer runs in an atomic context but obtaining the current CPU frequency requires taking a mutex because updating the CPU frequency involves the regulator. Instead of directly parenting the TWD clock on the CPU clock, make the TWD a "detached child" of the CPU clock whose rate is updated whenever the CPU frequency changes. Change-Id: I49e15f85f269fb3ed0bcaee36ff739b4f064d6b8 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R7aa10f2576752390464586bc629c972802beb989
2011-11-30ARM: tegra: clock: Don't fail clk_enable when max_rate has been loweredDan Willemsen
Rebase-Id: Rea679b3ebef177d19f96bfc298d1f5da8588d6ad
2011-11-30ARM: tegra: remove calls to smp_processor_id()Peter De Schrijver
smp_processor_id() only makes sense if the code can not move to a different CPU. The tegra clock code runs with IRQs enabled and preemption on, so it can move to a different CPU. Bug 827687 Change-Id: I8b3077c71966e535cc6ca2a2ec63eca0d7119777 Reviewed-on: http://git-master/r/35239 Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Peter De Schrijver <pdeschrijver@nvidia.com> Rebase-Id: R9fe292bc81ca5f456f1f54155febfa1e6e4d544e
2011-11-30FIXUP: clock lock/unlock flagsDan Willemsen
Rebase-Id: R5cefc3b6d35fad4b52e50bd96e2ffae1212e31b8
2011-11-30ARM: tegra: clock: Enable clock while setting rate/parentAlex Frid
When clock configuration (source mux, divider value) changes, the new control register setting does not take effect if clock is disabled. Later, when the clock is enabled it would run for several cycles on the old configuration before switching to the new one. This h/w behavior creates two problems: - since dvfs takes into account only new (enabled) rate, the module can be over-clocked during initial phase of the clock switch - since parent clock refcount is updated when the mux register was written, the parent clock maybe disabled by the time of actual switch and h/w would not be able to complete switch at all To avoid described problems clock is now always enabled while setting the new rate/parent (and disabled afterwards to keep refcount intact). Original-Change-Id: I9bda56a2a98c9f3678715da1e1b8fe78874fb71e Reviewed-on: http://git-master/r/31640 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R9964ee8633a54e55e5b26d578487a6d0e02c4fe4
2011-11-30ARM: tegra: power: Set Tegra3 CPU/core rail nominal voltageAlex Frid
For different Tegra3 process corners/skus/revisions/boards set nominal voltages for CPU and core rails as well as adjust maximum clock rates as follows. - VDD_CORE rail nominal voltage: default value is indexed by speedo_id of the chip (speedo_id is determined by chip sku and revision). Minimum of the default and board specific electrical design voltage is rounded down against core dvfs voltage ladder. The result is set as nominal core voltage (edp voltage API is not implemented, yet). - VDD_CPU rail nominal voltage: default value is indexed by speedo_id of the chip. If too high, it is lowered to core nominal voltage so that core_on_cpu dependency is resolved at nominal core level. The result is compared with voltage required to reach CPU maximum rate as specified in the dvfs table for the particular process corner. Again, the minimal level is selected, and finally set as CPU nominal voltage. After nominal voltages are determined, maximum rate for each dvfs clock is adjusted accordingly, so that it does not exceed the rate specified in the respective DVFS table at nominal level. Original-Change-Id: Ia6c1c5c853f98ab185f42bf1cfd7a1d7d54d10c3 Reviewed-on: http://git-master/r/30928 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Rebase-Id: R30393515042d199154ba708afaefb134402f551a
2011-11-30ARM: tegra: implement events for clock tracingPeter De Schrijver
Original-Change-Id: If6ae23251aa615a678c8edb76d3c1e6463d86f2e Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Original-Change-Id: I50ffa54eacaf5b3973fcd6cb94eee56e46ec81bf Reviewed-on: http://git-master/r/30384 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rc05e6b5e44c3d337d718d2e62c91a06d4558d044
2011-11-30ARM: tegra: clock: Remove "sole parent" requirementAlex Frid
During dvfs initialization, change propagation of sleeping attribute from "current_parent-to-child" to "possible_parent-to-child". This would guarantee that any non-sleeping clock has only non-sleeping parents, and it is no longer required for sleeping clock to be a sole parent of all its children. Original-Change-Id: I11110f6cb9c538c1e71bf00195c3f49dd09ea1f7 Reviewed-on: http://git-master/r/29706 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R3916f7d951cc3ea8b80d9e22a8200f45ec54fa3d
2011-11-30ARM: tegra: clock: Show cansleep attribute in clock treeAlex Frid
Original-Change-Id: Iff900aa5b69329696bcd250c824e0a191f6f6299 Reviewed-on: http://git-master/r/29705 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc93662daa81d9cf5ba656b81958f95241c259b47
2011-11-30ARM: tegra: clock: Clip Tegra3 CPU mode rate limitsAlex Frid
Made sure Tegra3 LP CPU mode maximum rate, and G CPU mode minimum rate are clipped to the entries in cpufreq scaling table. Original-Change-Id: I4c82b65be3a8680edbb501041a7158d1a7fbbd07 Reviewed-on: http://git-master/r/29703 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R99b548e992c80e4850e6d7f9443db8f7d7134956
2011-11-30ARM: tegra: power: Split Tegra3 CPU-G and CPU-LP dvfsAlex Frid
On Tegra3 CPU power is supplied by different rails in G-mode (VDD_CPU) and LP mode (VDD_CORE) - updated dvfs dependencies respectively. Original-Change-Id: Ifae8ae501b227a44e46ce1577bcd532e2e778322 Reviewed-on: http://git-master/r/25200 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I96e6cb7e3dcdf8514714d2900d8f947b6438c95f Rebase-Id: R4d16a0002c701f6ee2f0f8c0f66c5313e4546d53
2011-11-30ARM: tegra: clock: Add clock time on statisticAlex Frid
Original-Change-Id: I361e00ef84ce4ca9a9c6d7340de2d095fc67a208 Reviewed-on: http://git-master/r/25180 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: If382fc3b5d2ca678df8a9319a06bae967fc3c658 Rebase-Id: Ref4182db3e144202dd2df2047a3683e478e070fc
2011-11-30ARM: tegra: clock: Re-factor Tegra3 cpu clocksAlex Frid
Added second level virtualization (on top of virtual cpu rate control) to support different Tegra3 CPU power modes: low power (LP) mode and geared performance (G) mode. Virtual cpu complex (cpu_cmplx) clock is defined as a child with two parents: virtual cpu_lp and virtual cpu_g clocks for the respective modes. Mode switch sequence was integrated into cpu_cmplx set parent implementation. (Before this commit mode switch was triggered outside the clock framework, which created cpu clock/mode synchronization problems). Each mode clock is derived from its own super clock mux (cclk_lp and cclk_g) to statically match Tegra3 h/w layout. (Before this commit the code had to dynamically synchronize CPU mode and active mux selection). This change also allowed to support PLLX output divider for low power mode as fixed 1:2 divider with bypass control embedded into cclk_lp parent section. Updated auto and sysfs CPU mode switch calls to use new clock framework, and removed clock manipulation from the low level mode switch implementation. Original-Change-Id: Ibc3cc495b2ff29e2d3417eff2bfd45535cbd015b Reviewed-on: http://git-master/r/24734 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I23ae80edbf14fb22727a6fc317cd9e5baf8bd6be Rebase-Id: Rdcd4a2165ebd92bf4caa35d68ca81d19a3789351
2011-11-30Update copyrightsScott Williams
Original-Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a Rebase-Id: Rd8ebde470ad475b826857413018a2da8e1fdea25
2011-11-30arm tegra:Using pll_p clk source for sdmmc instances.Pavan Kunapuli
Using pll_p clk source for all sdmmc instances. Disabling clocks left over by the bootloader. Original-Change-Id: I245347b016618c39a4ceb2323f659b09261eaf7d Reviewed-on: http://git-master/r/17847 Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Original-Change-Id: I0790f6f67c944a9ca42be9d6b9398d8093b4beef Rebase-Id: Reb04f18203438d4d42e6f066d4c5216b692aabc2
2011-11-30arm: tegra: sdhci: Do not disable sdmmc4 clockPavan Kunapuli
Do not switch off sdmmc4 clock. Also, removed ddr mode temporarily from linux mmc driver. Programming tap_delays and internal clock. Original-Change-Id: I830bf5e94ccd47e154c5ef9909e8bff1ff7754c0 Reviewed-on: http://git-master/r/17070 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Ic1cff8dd85229fe903206f1dc9a967d600ba88c1 Rebase-Id: R9c15db46ec7f4073c03301dbc77ee5cb2f7800bd
2011-11-30ARM: tegra: clock: Prevent parent over-clockingAlex Frid
Pre-set clock rate when changing parent to avoid parent over-clocking during clock initialization from common/board specific tables. Drivers however, may still hit over-clocking error. Original-Change-Id: Ib101d85e90ab4c1194ac98680c930eebd8c56b76 Reviewed-on: http://git-master/r/16877 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I307e7eb507d885c381087812d262d56338aab861 Rebase-Id: R1c5fae8b3b048b31b2ed775a602ea33afb5c732e
2011-11-30ARM: tegra: clock: Add check for parent over-clockingAlex Frid
Fail clk_set_parent() interface if switching the clock parent will set the rate above maximum limit. Original-Change-Id: I47c0798dafe5f8f497dcacfcd23f6957244cdb0a Reviewed-on: http://git-master/r/16876 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Ie5fef027411096a465ae5aa84fe84a08a769a613 Rebase-Id: Rce314c75bbd31c8fc579e7bd22a00777dc6e94dc
2011-11-30ARM: tegra: clock: Propagate errors in debugfsAlex Frid
Original-Change-Id: I7d7f4f49cc1e41707032467197d53967d3ecaf06 Reviewed-on: http://git-master/r/16659 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I9e04b2833ef12466664cf6f6c2666d440600db08 Rebase-Id: Rd3ba800e548a5ccf6a756d5523a0fc240819dc64
2011-11-30ARM: tegra: clock: Add clock state debugfs controlAlex Frid
Original-Change-Id: I2a16c36c8ee414a1f046eda2f3bdb9c1d71caf8b Reviewed-on: http://git-master/r/16657 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Icc4b526f44697bd788d83434f6e9a62de005b09c Rebase-Id: R34e12f5fbafa93a8f01cd00d83a33b356d0782ec
2011-11-30ARM: tegra: clock: Re-factor extended clock operationsAlex Frid
Re-factored extended clock operations to enumerate configuration parameters. Original-Change-Id: I6c1e5f07803a8e6da0ebd6690892f50bb59efcd5 Reviewed-on: http://git-master/r/15144 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I25147998969b385905bad5eb3ceb2dbb89c0d93a Rebase-Id: R815ccca27fac9a0af334c188ce77e0ec4fdad9b2
2011-11-30ARM: tegra: clock: Add extended clock configurationAlex Frid
Some peripheral clock source registers have extra bits with setting specific for the respective controller. Added mechanism to manipulate these bits from the clock code with proper locking. Implemented NAND, VI and DTV extended configurations. Original-Change-Id: Ic8a1887923f0b98f9b1fac06dcf4f90084b017c0 Reviewed-on: http://git-master/r/15059 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Original-Change-Id: Ic3416be8683c90043376d6675269fc23e440f61d Rebase-Id: Rd3e7af5a00bf9580816853456ddb6f19b9bc5b2b
2011-11-30Merge remote branch 'remotes/git-master/android-tegra-2.6.36' into 0104-mergeJin Qian
Conflicts: arch/arm/configs/tegra_defconfig arch/arm/configs/tegra_whistler_android_defconfig arch/arm/mach-tegra/Kconfig arch/arm/mach-tegra/Makefile arch/arm/mach-tegra/board-ventana.c arch/arm/mach-tegra/board-ventana.h arch/arm/mach-tegra/board-whistler-power.c arch/arm/mach-tegra/board-whistler.c arch/arm/mach-tegra/clock.c arch/arm/mach-tegra/clock.h arch/arm/mach-tegra/common.c arch/arm/mach-tegra/cpu-tegra.c arch/arm/mach-tegra/dma.c arch/arm/mach-tegra/fuse.c arch/arm/mach-tegra/headsmp.S arch/arm/mach-tegra/include/mach/iomap.h arch/arm/mach-tegra/irq.c arch/arm/mach-tegra/spi_tegra_slave.c arch/arm/mach-tegra/tegra2_clocks.c arch/arm/mach-tegra/tegra2_dvfs.c arch/arm/tools/mach-types drivers/crypto/tegra-aes.c drivers/rtc/rtc-tegra.c drivers/video/tegra/host/dev.c drivers/video/tegra/host/nvhost_acm.c drivers/video/tegra/host/nvhost_channel.c drivers/video/tegra/host/nvhost_intr.c sound/soc/tegra/tegra_i2s.c sound/soc/tegra/tegra_pcm.c Original-Change-Id: If13d61cce097ee90892132e775c5ac805a1f91e0 Reviewed-on: http://git-master/r/14922 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Id331a2ef77522766e5b7f86131c6c981b37ba4c8 Rebase-Id: R0a3bf55c838f202bc5469df6b497748670e7ff09
2011-11-30ARM: tegra: clock: Update LP-cluster related interfacesAlex Frid
Original-Change-Id: Ifde476a05bd01cdce8c3f4802b268a193a832a1b Reviewed-on: http://git-master/r/14584 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I41204d17c5d8092b1a24b3138efe12cfbd16d7e7 Rebase-Id: R9754ff5e07ecabd945edfccdbc0f9d9586be6e23
2011-11-30[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081 Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
2011-11-30ARM: tegra: clock: Adjust max rates to match SKU IDAlex Frid
Adjust max rates for CPU and several SKU-dependent core clocks (system bus, AVP, VDE, 3D) to match chip SKU ID. Added max_rate node to debugfs. Original-Change-Id: Ifd72d45a303b3d8b5ae5f327693bb97c8510031d Reviewed-on: http://git-master/r/16077 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R7aa44477fd12c9d046baf7ecb8e5e2fcb71818d7
2011-11-30ARM: tegra: clock: Add debugfs clock set methodsAlex Frid
Implemented debugfs clock write mechanism (disabled by default). Expanded and fixed debugfs clock nodes to properly read clock parent and rate. Original-Change-Id: I9f20994d0829634e09f4bccd6fce6c7c8b5bf844 Reviewed-on: http://git-master/r/15315 Tested-by: Amit Kamath <akamath@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Ra802d13d77e74c6e8def92a93c08157f8eb888fe
2011-11-30ARM: tegra: Add dvfsColin Cross
Change-Id: I865e52cae592507c642b92dde3a8293db2d0228f Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30ARM: tegra: clock: Disable clocks left on by bootloaderColin Cross
Iterates through all clocks, disabling any for which the refcount is 0 but the clock init detected the bootloader left the clock on. Can be disabled with command line tegra_keep_boot_clocks Signed-off-by: Colin Cross <ccross@android.com>
2011-07-20switch assorted clock drivers to debugfs_remove_recursive()Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2011-02-22ARM: tegra: clock: Round rate before setting rateColin Cross
Call the clock's round_rate op, if it exists, before calling the set_rate op. This will help later when dvfs is added, dvfs needs to know what the final rate will be before the frequency changes. Also requires fixes to the round rate functions to ensure calling round rate and then set rate will not cause the frequency to be rounded down twice. When picking clock divider values, the clock framework picks the closest frequency that is lower than the requested frequency. If the new frequency calculated from the divider value is rounded down, and then passed to set_rate, it will get rounded down again, possibly resulting in a frequency two steps lower than the original requested frequency. Fix the problem by rounding up when calculating the frequency coming out of a clock divider, so if that frequency is requested again, the same divider value will be picked. Signed-off-by: Colin Cross <ccross@android.com> Acked-by: Olof Johansson <olof@lixom.net>
2011-02-21ARM: tegra: clock: Add function to set SDMMC tap delayColin Cross
The SDMMC controllers have extra bits in the clock source register that adjust the delay between the clock and data to compenstate for delays on the PCB. The values need to be set from the clock code so the clock can be locked during the read-modify-write on the clock source register. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-20 11:47:51 +0000