Age | Commit message (Collapse) | Author |
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Propagate error to the caller when switching between alternative
cpu dvfs tables. Change dvfs table during cpu hotplug operation
only after the new edp limit is set, and abort bringing cpu core
on-line in case of failure in applying new (less conservative)
table. When cpu core is removed change dvfs table before setting
new edp limit, and ignore error (it is safe to continue with more
conservative table).
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 951710ec179fd620a2251d0815ca7bff15da014b)
Change-Id: Ib1ad8e41093fb9bee75d3d6bd18d0ac406da8271
Reviewed-on: http://git-master/r/114779
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Implemented an object based balanced throttling in preparation
for multiple balanced throttling objects.
bug 1007726
Change-Id: Ib58fafaf696af0ae58e78bd9fd417d3a822d0571
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/105238
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Extended EDP processing of cpu up/down events with calls to alter CPU
dvfs table. This is in addition to already supported changing of CPU
dvfs on EDP thermal event. For now, added calls do not actually alter
the table.
Change-Id: I1cbf2c54eeca8dea1e7b6f4c65d8dbaf563a980e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/104883
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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On Tegra3 make sure cpu rate is within G-mode range before LP to G
mode switch triggered by minimum CPUs notifier.
Bug 964208
Change-Id: Ic4ee6bc7eca5ad0902da4907e4702f296a155280
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/99834
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Check returned value from BPC set limit api, and re-try again
on error. Keep CPU throttled while re-trying.
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 8d5e5a36a03587e3e9374ad8cec6958bd3617f0c)
Change-Id: I29b24a92b87cbd41d68473d0c9ef4c8d6add992f
Reviewed-on: http://git-master/r/93732
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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To set cpu_user_cap in tegra drivers, added tegra_cpu_user_cap_set
function.
Bug 945552
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/87109
(cherry picked from commit db954aafdfdbe1fa122466b8e8ec4ea4273efb90)
Change-Id: I765c44de4ed4ae908ef56914db53533605bd6d88
Reviewed-on: http://git-master/r/89740
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Boost CPU frequency in tegra platform resume finish phase, just
before driver resume. Boost level is specified by platform suspend
data (ignored if 0).
Bug 946301
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit eaedf228861e4456454ca13f0958ed97e799fc59)
Change-Id: Ica0cff28f9651e38787ec98f54563d95d876d79e
Reviewed-on: http://git-master/r/89353
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Check error returned by cpufreq table helper API to avoid using
uninitialized table index in failed case.
Reviewed-on: http://git-master/r/77523
Change-Id: Ie47481a27397c6cafe73bfbddab0a392837ad019
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78439
Reviewed-by: Automatic_Commit_Validation_User
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Added Tegra3 MSelect clock to memory on CPU clock dependencies:
MSelect rate is scaled as half of CPU rate, up to 102MHz. Prevented
CPU clock increase if updates of dependent clocks (EMC and MSelect)
have failed.
Reviewed-on: http://git-master/r/76485
Change-Id: I679b60eb5aa13d5cca2b9751ff2c8c2fb866a076
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77767
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Added alternative frequency limits for Tegra3 CPU. These limits are
applied only in the lowest CPU EDP temperature zone, and the offset
from regular Tegra3 dvfs frequencies is set at -50MHz at all scaling
voltage steps. Offset values as well as temperature threshold are to
be updated per characterization.
Bug 913884
Change-Id: Ia420f54b4c9fdc966e44d0269d45d9164d751b5f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/70189
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/75615
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
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System electrical design point (EDP) alarm is generated when system
power source (battery) over-current is detected.
Part of the system EDP management is CPU frequency capping added by
this commit. Maximum CPU clock frequency is pre-determined depending
on number of CPU cores on-line. It is combined with CPU regulator EDP
limit and applied to final CPU rate; CPU voltage is scaled down by
DVFS, respectively. The system EDP limit of CPU rate is removed after
alarm is canceled.
EDP event can be emulated via debugfs entry /d/cpu-tegra/edp_alarm.
(cherry picked from commit fa673d27766ff9513139e94a498e4c24827d7c57)
arm: tegra: power: Removed erroneous ';'
(cherry picked from commit b4b404381b2d1823b7c127858950f853428fe3b5)
Change-Id: I60ec0e87f9442b698a8824895aac0a1f955565b4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/67823
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Refactored Thermal module so that thermal device
drivers themselves are agnostic of the thermal
framework. Also separated throttle limit constraints
from EDP table.
Reviewed-on: http://git-master/r/57990
Reviewed-on: http://git-master/r/63338
Cherry-picked from 8d0610bdd03c3490b718f11bc2108f45cd868533.
Change-Id: I4f87889c9cdc88daac1e6173043bab1f2e7cebfd
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/66551
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
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Added a thermal driver which is agonistic to the device driver
which will make it easier to port thermal devices to android
tegra.
Reviewed-on: http://git-master/r/55883
Reviewed-on: http://git-master/r/59471
(cherry picked from commit b89dbb5a64bcb3124794f644e71658de83a4ab71)
Change-Id: Ib3c7100144ea0a98ac7c15e404d4d9e7737018e5
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/66548
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
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Added sysfs node /sys/module/cpu_tegra/parameters/cpu_user_cap to set
maximum CPU rate from user space. Unlike per-cpu frequency governor
limit (scaling_max_freq), this cap is applied directly to common CPU
complex frequency underneath per-cpu governors.
(cherry picked from commit 5fbd5b19ddb43a03391957000f23b729f394b05b)
(cherry picked from commit bf81c8efc2c98e5008527ce019669dc57718f44b)
Change-Id: Ic2f152e1fd58f2f0062489309c0cffd32a2462ae
Reviewed-on: http://git-master/r/61711
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R800c2a4d5e097bdd29fa1b0b901264a2723abff0
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When voting on memory frequency based on cpu frequency, update memory
frequency before cpu frequency if cpu rate is increasing, and after cpu
frequency if cpu rate is decreasing (current code updates memory first
always).
(cherry picked from commit 9284039a4d86c22ee72e11d6c173b24a5b4f720e)
(cherry picked from commit 3cd676121913b1cd9eddff06d6966817dcd9de94)
Change-Id: I91b81f1eab91d575959a2fd9af3a8798f7ca6cf6
Reviewed-on: http://git-master/r/61707
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R64d5597f8360ca151ba5e017cb94915c63699aca
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(cherry picked from commit dc2f416df4664f5ddeba6f14f41cd6bcd717abab)
(cherry picked from commit caa79c7d6219231d02260ae91876eff4f411dee8)
Change-Id: I29eb42c73a7e3cd3f401e8b5d44bcf3f06478c2c
Reviewed-on: http://git-master/r/61021
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: Ref5015bb8336d8106c80fa390911ff0371b3ec57
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Tegra cpu complex frequency is set by cpufreq driver to the maximum
of per-cpu target frequencies specified by the respective governors
running on each cpu core. It guarantees that final frequency is above
all per-cpu policy low limits, but policy high limit set on one core,
may be exceeded if the other core has higher target.
This commit implements complementary mode in cpufreq driver that set
final cpu frequency below all per-cpu maximum policy limits. The new
mode is disabled by default, and can be activated via
/sys/module/cpu_tegra/parameters/force_policy_max
(cherry picked from commit d52a93527778b13efd2e4b783ce0707513f53f26)
(cherry picked from commit bc1450eedb97fd2f37544e07dae15946d209866c)
Change-Id: I2b51738a50312e0b3ba747747e6fa68efddc6038
Reviewed-on: http://git-master/r/61020
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R2fa76e42f800220db708c8720a3fe6b1792e5c59
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- Account for EDP affect on total available MIPS when bringing on-line
(removing off-line) new cpu core. Add multi-core overhead (in percent)
as a parameter - set by default to 10%.
- Add balance level parameter: level value (in percent) defines minimum
speed ratio used by hotplug algorithm to determine if current CPU cores
are balanced, so that another core may be brought on-line. By default
set to 75%
Added tunables:
/sys/module/cpu_tegra3/parameters/mp_overhead
/sys/module/cpu_tegra3/parameters/balance_level
Bug 865176
Bug 867186
Original-Change-Id: I6f2e175e0b5ed14c4b85794949c1e65d0e7f4a36
Reviewed-on: http://git-master/r/49772
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Rebase-Id: Rcfefb570c30bf78f6eae155c3f3f7547ac64f128
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bug 865842
Original-Change-Id: I54dcf3e2e968692746f1d8b17bdf912305f547a2
(cherry picked from commit 5b9dce25485824036f86db093b28a45a3cd86c76)
Reviewed-on: http://git-master/r/48257
Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R1adb1ca832e0f63f1e5b7e405f4c87c4a8a7aabe
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Original-Change-Id: Ic4a9571799da93749f571f5fb81a2391c6da50eb
Reviewed-on: http://git-master/r/48225
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R09222a436b9de16ca31d6824354bcd1ae702386f
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Always use maximum possible frequency when applying EDP
capping. Toggled through CONFIG_TEGRA_EDP_EXACT_FREQ.
Bug 863761
Original-Change-Id: I327440546991ad4f3abc78100a3a18017f3464b6
Reviewed-on: http://git-master/r/47169
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rdafcd7202975dd85631b4d281012343c5cda08be
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Moved tegra CPU throttling algorithm implementation into a separate
file. For now, the same algorithm is used for both Tegra2 and Tegra3
architecture.
Original-Change-Id: I478c32b5adee4c946472129b89615580c10b41e1
Reviewed-on: http://git-master/r/46748
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Anshul Jain (SW) <anshulj@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R2340f78e1d22942022e171044d6b20f260e2d312
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Added throttling enable reference counting, so that it can be
controlled by drivers for different thermal sensors (e.g, on
chip and device skin sensors).
Fixed possible dead-lock when cancel delayed work synchronous is
called while locked with the very same mutex that protects work
function.
Bug 837005
Original-Change-Id: If2aa8aa16f4a3b3497def592503213522fd38e54
Reviewed-on: http://git-master/r/40534
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R893b5a7b402d327b40acb7adbadb53f930804c0d
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Made sure that CPU thermal and edp limits are applied on all CPU set
rate paths: cpufreq governor, thermal throttling, edp notification,
power management notification. Also included auto-hotplug governor
state update in all these paths (current code does not apply the
limits, or does not include auto-hotplug on some rate change paths).
One exception - keep current functionality for suspend notification:
set pre-defined CPU rate, and force auto-hotplug idle state.
Original-Change-Id: I54531f8f919ce248b2b56f5aa56f39e2efcb568a
Reviewed-on: http://git-master/r/40533
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R1471a5f318644fa5a7f436d8ed73c12de8b76245
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Renamed and moved tegra cpu related function prototypes from power.h
to tegra-cpu.h. No functional changes.
Original-Change-Id: I24c25c9434bf7008e0875d1f74be502cd902c4ba
Reviewed-on: http://git-master/r/40532
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R3d90799453a86a5a9ed012d2bfe373715de6d5c3
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- Added table with EDP Capping values for different SKUs/regulator
currents in new file edp.c
- New entry point tegra_init_cpu_edp_limits()
- Added DebugFS entry under debug/edp to list the currently
selected EDP table
- Populated EDP table in edp.c with data from Bug 844268
- edp.c keeps main EDP table; cpu-tegra.c and board-cardhu-power.c
both read from there
Bug 840255
Original-Change-Id: I55c2ee16278be8cd3005218bedebe76846d137d8
Reviewed-on: http://git-master/r/40938
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R9a5f2bcfc1e6e0b5aee37cd700d75f9ef5cea30b
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Restored cpufreq governor target frequency on exit from suspend.
Otherwise, CPU would stay at frequency set underneath the governor
by tegra driver on suspend entry.
Original-Change-Id: Iad96c7771bf89b78cdeb3e8f4e2c40b36e845b57
Reviewed-on: http://git-master/r/38390
Reviewed-by: Alex Courbot <acourbot@nvidia.com>
Tested-by: Alex Courbot <acourbot@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R12135cc7f8f940eac1653432786826bf2affec16
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- For selection of cpufreq scaling table used top-most rate in G CPU
dvfs table, instead of G CPU max rate. Commonly the above rates are
the same, however, in case when PMU limitations on core voltage
indirectly (VDD_CPU on VDD_CORE dependency) lower cpu max rate, the
top-most dvfs rate should be used for table selection, and the max
rate clipped to table entry.
- Replaced BUGs in table selection implementation with errors. Thus,
when no table is found cpufreq is not installed, but the system boots
with respective error messages.
- Step up suspend frequency index in cpufreq tables to reduce suspend
entry latency (the selected rate is still low enough to work under
Vmin voltage setting).
Original-Change-Id: I45db19dbf5b48cef80db35663db2df3b68473993
Reviewed-on: http://git-master/r/37415
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R59fb213db14d868bec0ca701e1c73dd9d1918e82
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Original-Change-Id: I7f4fb6447c882a54d95ee3fb4c6149f4e0357d69
Reviewed-on: http://git-master/r/31457
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Rebase-Id: Rbe2ac5f11065109d34a04793f93c873441e261be
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Do not overwrite thermal zone and preserve boot CPU rate settings if
thermal sensor is initialized before edp governor.
Original-Change-Id: Ia705d5f453003c204459f594ffb95152ff74145f
Reviewed-on: http://git-master/r/32861
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rfae7a16b2a93b9b294d8b70191c57a9a2e7374fc
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The build currently fails for some boards when CONFIG_CPU_FREQ=n, since
we don't build cpu-tegra.c but tegra_throttling_enable is still
referenced. To fix this:
- Add cpu-tegra.h
- Define tegra_throttling_enable to NULL in the header if either
CONFIG_CPU_FREQ or CONFIG_TEGRA_THERMAL_THROTTLE are not set
- Use the header file instead of declaring the function extern
everywhere it's used
Bug 829501
Original-Change-Id: Ice84309546dee201f991a1194fefd80583afc455
Signed-off-by: Robert Morell <rmorell@nvidia.com>
Reviewed-on: http://git-master/r/32208
Reviewed-by: Allen R Martin <amartin@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Rebase-Id: Reda9651e2395231d5b1ec7150885d3d9f66ca16b
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Tegra cpu-freq driver will now recognize edp zones
and cap the max cpu freq for that zone. The temperature
monitoring driver will be giving inputs to cpu-freq
on the current temperature which would be interpreted
by the cpu-freq driver appropriately.
Original-Change-Id: I918eb31771aa7e1e1a5f25438edded727de6eb8c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/31339
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R6d93bf69d0731ce4ae84f80d1e9013378483331c
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Original-Change-Id: I7bbe018f3786b9683cc9d4189fdcaadb9098f3f1
Reviewed-on: http://git-master/r/31456
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R81da4e2834a9ae209aadba17337d484f26f67ada
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When current CPU complex frequency is above target range:
- bring new core on-line only if cpufreq governor requests for
all already on-lined CPUs are above 50% of current CPU frequency
- off-line one core (despite high pick request) if cpufreq
governor requests for at least 2 on-lined CPUs are below 25% of
current CPU frequency
- do nothing if neither of the above conditions is true
Original-Change-Id: I77e1bd543a8fadd51974f7d574f256a6e7e2979a
Reviewed-on: http://git-master/r/29702
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rc5c717454d1e09ca97ccc79fff60cb33fcf854e9
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- taking CPU core off-line: selected CPU with minimum load
- switching from ULP to G CPU mode: set CPU clock to cpufreq
target rate after the mode switch is completed
Original-Change-Id: I9bf4d0f4b48c262cf678c603aac02043dd602674
Reviewed-on: http://git-master/r/28420
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Original-Change-Id: I5a19be79dd8f8fe788637870a22cd34dcfea150e
Rebase-Id: Re264ec676c5c2103f7738c9eab5f4e11a4344975
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CPU electrical design point (EDP) limits specify maximum CPU frequency
depending on number of CPU cores on-line, and chip temperature. This
commit added initial edp governor to cpufreq driver. Governor is aware
of CPU departure/arrival, but temperature dependency is yet to be added.
Therefore CPU EDP support is left disabled for now.
Original-Change-Id: Ia875aa6904df7ec25ac98863d59a173703034241
Reviewed-on: http://git-master/r/26982
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Iae2e9d47c2d3fd4cb32104adbad4f4b26c46064c
Rebase-Id: Rde24788e86558e1c21b18a1857a8b52220ba8e2a
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Use cpufreq (cpu DFS) mutex for auto-hotplug (instead of a separate
one) to serialize cpu frequency scaling, hotplug, and CPU mode switch
operations.
Original-Change-Id: I7ea865894d1676c865294ab31a903248d9437534
Reviewed-on: http://git-master/r/24893
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I906a23561c1567079a41590a30b29b3d52fa5de8
Rebase-Id: R5d16154c91b41fd02f2a50af7ec6868a7958dc13
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Original-Change-Id: I9e10c8d4ed074f915769ae7c77d915d6b021e2c9
Reviewed-on: http://git-master/r/24892
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I23820e1557d304d7a99417b99afaeb4a36c9d18f
Rebase-Id: Re1b1e4f589376f52c1e9cf903ceaee7efe798ba1
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Original-Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a
Rebase-Id: Rd8ebde470ad475b826857413018a2da8e1fdea25
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Original-Change-Id: I28155e59fd6cb36ccd63d8d17ed01b70b9209f97
Original-Change-Id: Ic4ebe6007ab9ee308039ad86c0930f85d116fdd5
Reviewed-on: http://git-master/r/22531
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I4e5e939921d6d82aa8687545399a867901655069
Rebase-Id: R71c8b69183d12414112d88d60fe54a7b85a6d3de
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Initial implementation of Tegra3 quad core CPU management. Add closed
control loop on top of cpufreq DFS. Target frequency range is bounded
by Fmax(Vnominal) for low power cluster - currently set to 456MHz, and
Fmax(Vminimum) for high power cluster - currently set to 356MHz.
When CPU frequency is scaled below the target range, slave high power
CPUs are gradually brought down and eventually CPU is switched to the
low power cluster.
When CPU frequency is scaled above the target range, CPU is switched
to the high power cluster and slave high power CPUs are gradually
brought up.
The auto hotplug support is disabled on boot. It can be explicitly
enabled via sysfs interface.
Original-Change-Id: Ie0e5cf1f334d9c53932db05950cfcf5addd271d7
Reviewed-on: http://git-master/r/18500
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I86152069aa2bed73e0148a4bcab897811e1a5827
Rebase-Id: R9cf5f5f8868c659db526cb49ddf276a79d93ef1a
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Bug 764354
Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046
Reviewed-on: http://git-master/r/12228
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081
Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
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Added support for emc frequencies 75,100,25 Mhz scaling
Original-Change-Id: Id5f170a380c3acbc7a375ab5e5018628549b992f
Reviewed-on: http://git-master/r/18340
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Tested-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R95a7430358c3c527315b32b14609a18ce2e6324c
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Define cpu frequency tables for different tegra2 CPU clock ranges,
and add matching selection mechanism for scaling table as well as
throttling limits.
Original-Change-Id: I06b13f150d72f8a80f879ecf80ed44cc1f63bad4
Reviewed-on: http://git-master/r/16076
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rc69b8d00284b7bc164d47beb3615b712bfc2c25c
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Various review feedback, including:
Keep a global throttling index that specifies a ceiling CPU speed, lowered by one
at each delay interval (while the temperature alarm continues to be signalled).
Avoid lowering the throttle too far based on a transitory lowering of speed
requested by the governor.
Restore governor-requested speed when throttling turned off.
Add cpufreq sysfs attribute for checking throttling state.
Make throttling workqueue high-priority.
Cosmetic changes.
Change-Id: I068bf32115927fa61282f17f4a8798f2aee0b530
Signed-off-by: Todd Poynor <toddpoynor@google.com>
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The NCT1008 driver is now passed a function pointer from the board
file's platform data to be called when alarms are asserted or
deasserted. Switch to a single function for throttling
enable/disable suitable for calling via the temperature alarm
callback.
Change-Id: Ic0eb1566a68e151216e26dfb6ed6f4bc7a273ddb
Signed-off-by: Todd Poynor <toddpoynor@google.com>
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Based on work by Dmitriy Gruzman and Varun Wadekar.
Change-Id: I64d765628223b7ef1ec493b9e409ea11e9391b94
Signed-off-by: Todd Poynor <toddpoynor@google.com>
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Change-Id: I28d69d22437b6ba2d22e4ce12746630786006071
Signed-off-by: Dmitriy Gruzman <dmitriy.gruzman@motorola.com>
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This fixes a compilation error in cpu-tegra.c which was introduced in
dc8d966bccde ("ARM: convert PCI defines to variables") which removed the
now obsolete mach/hardware.h from the mach-tegra subtree.
Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Adjusts the minimum memory frequency when the cpu frequency
changes. The values are currently hardcoded to a reasonable
default. If memory frequency scaling is not enabled this
patch will have no effect.
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Colin Cross <ccross@android.com>
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