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path: root/arch/arm/mach-tegra/cpuidle.h
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2012-02-03ARM: tegra: power: Separate lp2 latency for G/LP CPU modesAlex Frid
Do not use common lp2 exit latency for Tegra3 CPU G and CPU LP modes. Separately measure and adjust latency in each mode; restart calculation after mode switch from the last measured latency in the target mode. Reviewed-on: http://git-master/r/78344 Change-Id: I54803c6abf4107a578aa1fed8feaa4a419a9c07f Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78902 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-01-10arm: tegra: REVERT "use unsigned cpuidle latency variables"Joseph Lehrer
Reverting until LP2 hang problem better understood. bug 896827 Reverts I8c8226433d26efbbc1579372c9a73cbc5897f26c Signed-off-by: Joseph Lehrer <jlehrer@nvidia.com> Change-Id: I9ae1f8e75b77049baf26480691b98e6f9cacca4e (cherry picked from commit c0b30ab66c5f1286a5c1f10777c436a80f8f2fa8) Reviewed-on: http://git-master/r/72905 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com> Tested-by: Joseph Lehrer <jlehrer@nvidia.com> (cherry picked from commit 3d7b52eaf614848e8417c84b819c76faed306503) Reviewed-on: http://git-master/r/73951 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2011-12-30arm: tegra: use unsigned cpuidle latency variablesJoseph Lehrer
Latency calculations were using mixed signed/unsigned variables and assignments resulting in very large values which interfered with entering LP2. bug 896827 Change-Id: I8c8226433d26efbbc1579372c9a73cbc5897f26c Signed-off-by: Joseph Lehrer <jlehrer@nvidia.com> Reviewed-on: http://git-master/r/72151 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2011-11-30ARM: tegra: power: Update Tegra3 LP2 time predictionAlex Frid
Use local timer count to predict time to be spent by secondary CPU in LP2 state instead of scheduler timing. This is more accurate, as local timer wakes CPU after counts down to zero. Change-Id: I28fe6c3153e1c527abf4cf66b556d64516582a35 Reviewed-on: http://git-master/r/55629 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Antti Miettinen <amiettinen@nvidia.com> Rebase-Id: R577246dfe6bce06bf7a1f87d0ab488322d98b631
2011-11-30ARM: tegra: Fix build error when CONFIG_PM_SLEEP is not selectedScott Williams
Change-Id: I65e18395eef3a36f6dd537d64d98ab970f166460 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/47590 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2643d7665780442e71444999f21d96a508c7a062
2011-11-30ARM: tegra3: power: Add LP2 power mode support for CPU 0Scott Williams
Add support for forced Tegra3 LP2 low power mode on the boot processor (CPU 0) via the cluster control interface when all others are offline. Switching to the LP CPU mode is also enabled with this change. LP2 in idle and LP2 mode on the secondary processors is not yet supported. Change-Id: Icb898729f093be5e006c413f701532dd45228687 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
2011-11-30ARM: tegra: Add Tegra GIC extensionsScott Williams
Implement extensions to the standard ARM GIC API for Tegra3 power management. Change-Id: If8b2ce2b366e48bb5ca82d3de2acab1fd0a81bb9 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd7527cd57edf054c871f5d04d7e9185643f79843
2011-11-30ARM: tegra: Add LP2 exit latency correctionScott Williams
Change-Id: I37cb57f8674d8ddea3861fdc59543c3dfa8498db Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R0a1d0c79e22f9191bde70b8b05541c5bfe26f4df
2011-11-30ARM: tegra: Catch early LP2 exitsScott Williams
Change-Id: I107d301ec8e8cd3b69ea293faab15b8d766e38f4 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R9f8f016c1850e2c65f30f2f67241a94acf8a7755
2011-11-30ARM: tegra: Prevent LP2 if request is less than target residencyScott Williams
Change-Id: Icc7409b611439ba94ec504579c00ab9227c9a857 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R4b56e98c821627de480a67c241363608ebfc2f07
2011-11-30ARM: tegra: Make LP2 require CONFIG_PM_SLEEPScott Williams
Change-Id: Iaaf96375eaf7408f5bedc4196d33a04fb94129ef Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R98567e0d894acbdac770b191f7e46f16592d5d0b
2011-11-30ARM: tegra2: Move LP2 into cpuidle-t2.cScott Williams
Move Tegra2 SOC-specific CPU idle functionality to cpuidle-t2.c Change-Id: I26c94ca74d7a78665c52e23571c5058e3da240a7 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1246e3942623458f5121ccdac3e6d4a1d40ad624
2011-11-30ARM: tegra: Move Tegra2 idlestats to cpuidle-t2.cScott Williams
Change-Id: I2c0814cfefd820626beeba468edd9c462c6be8bb Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbbb70f49af4e731c953315ae81a96480ac25ff4d
2011-11-30ARM: tegra: Add cpuidle.hScott Williams
Change-Id: I75ec091f9dcd0fa3fa56b1542f58a02006c1a314 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Ree5fce2632aff6dc59879817ad7ad3f2b1538244
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