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path: root/arch/arm/mach-tegra/dvfs.c
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2014-11-21arm: tegra12: add support for CD575M 24x7 ChipBibek Basu
Added DVFS support for CD575M Always on behaviour. With this personality configuration for the chip,the lifetime of the chip increases to 5 Yrs Operating Temp : -25 to 105 degC CPU DVFS: Max Freq 1938Mhz. Max Voltage 1.12V SOC DVFS: Max Voltage0 1.01V EMC dvfs max freq 792Mhz GPU DVFS: Max Freq 804Mhz and Ma Voltage 1.09V Bug 1563635 Change-Id: If7fec38b83ae4de8c5435006207fa3cf717384c0 Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/594855 GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2014-10-27arm: tegra: dvfs: Add cpu clock switch cdevsreenivasulu velpula
- Add cpu clock switch cooling device to switch between PLL and DFLL dynamically based on temperature. Bug 1563635 Change-Id: I098d41eb64ec53a284db310131c4f604c808645c Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com> Reviewed-on: http://git-master/r/439762 (cherry picked from commit 5cc4e0b770331dc2096d69b96ee8d27e585d8cde) Reviewed-on: http://git-master/r/559390 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2014-07-31ARM: tegra: dvfs: Don't protect dvfs data in early reasumeAlex Frid
Don't protect dvfs data with mutex in late suspend/early resume. DVFS operations are suspended at that time, but during syscore resume it may be necessary to update DVFS data to changes happened while the system was in suspend (in praticular memory configuration was changed by boot-rom on suspend wake). Change-Id: I8df278dc2e58e5ea1508d187afe0b8f4d8ccbe22 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/438903 (cherry picked from commit 9008a4ad3ee979445b42bc52b8d1619da82badbb) Reviewed-on: http://git-master/r/440505 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Tested-by: Gaurav Sarode <gsarode@nvidia.com>
2014-06-24ARM: tegra dvfs: Keep DVFS rate for disabled GPU clockAlex Frid
Preserved DVFS rate for single clock GPU rail when clock is disabled (instead of setting zero rate). In this case GPU rail is turned off explicitly, anyway. However with non-zero DVFS rate voltage level at regulator is appropriately updated when temperature is changes while rail is off. Bug 1526819 Change-Id: I022d908a47be81efbe37d8a777e93b1fec74e7e7 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/426917 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-04-03ARM: tegra: clock: Use DFLL Vmin comparison interfaceAlex Frid
Used DFLL Vmin comparison interface to determine if CPU rail voltage should be increased to account for temperature or SiMon grade change before switching CPU cluster from LP to G. Bug 1343366 Change-Id: I188cd8f7280a5b5361c59b244da6c8a4d729f05d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/391051 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-13ARM: tegra: dvfs: Add dvfs rail voltage to debugfsAlex Frid
Bug 1409319 Change-Id: Ic62cc8b843655041930d8f622120129dce420cbf Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/334843 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-13ARM: tegra: dvfs: Update debugfs DVFS treeAlex Frid
Added to debugfs DVFS tree resolution of rail dependencies when dependent rail (rail-to) voltage is zero. This is in addition to already printed resolution from current rail-to voltage. Bug 1461646 Change-Id: I0bf834c35441b80c974fa18bc4bd9b9ec8ad0c51 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/379283 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-19ARM: tegra: dvfs: Update rail relationships supportAlex Frid
- Since nominal and suspend voltage levels can be different, defined relationship solved_at_suspend flag (in addition to solved_at_nominal). - Since, overriding dependent rail below nominal voltage may not be safe set minimum override boundary to nominal level for any rail that depends on other rail. Bug 1461646 Change-Id: I1fee3380d16da3f0feeec26d91df0fb8723946b4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/369084 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-19ARM: tegra: dvfs: Resolve rail dependency in DFLL modeAlex Frid
So far, for the rail in DFLL mode - h/w controlled voltage - DVFS set voltage interface only recorded new requested level for statistical purposes. No regulator communication was sent by s/w in this case. It is possible, however, that the other - s/w controlled - rail may have dependency on DFLL rail voltage. Therefore this commit updated DVFS set voltage interface and DVFS suspend entry so that such dependency will be resolved via s/w control of the dependent rail. Bug 1461646 Change-Id: I1093ac048146d76b4c93a93f1023975424bfe5c3 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/369083 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-18ARM: tegra: dvfs: Add access to DFLL thermal floorsAlex Frid
Since SiMon grading offsets applied to CPU Vmin only if DFLL is used as a clock source, thermal floors in DFLL and PLL modes can now be different. Although CL-DVFS driver maintains its own copy of thermal floors properly updated with SiMon offsets, this updated floors are not accessible by legacy DVFS mechanisms that are still engaged in DFLL mode: rail stats gathering, DVFS debugfs tree, and safe voltage setting before cluster switch (using PLL mode floors is still safe in this case, but unnecessary push voltage higher). Hence, this commit exposed DFLL thermal floors to legacy DVFS. Bug 1343366 Change-Id: Ibd0bcd577f72f6022a4a83faf1894bec2361c151 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/368124 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-18ARM: tegra: dvfs: Change CPU VSEL access attributeAlex Frid
Changed CPU voltage selector register access to volatile/cached when switching rail to/from DFLL mode, respectively. Added debug prints to facilitate debugging. Bug 1454969 Change-Id: Ic5176d99f8a179bca9baef4296ef45df66db7f0e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/365780 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-02-06ARM: tegra: dvfs: Predict required voltage for a given freqNaveen Kumar Arepalli
Export the tegra_dvfs_predict_millivolts interface to drivers to be used during tuning and getting the minimum core voltage for a given frequency. Bug 1423429 Reviewed-on: http://git-master/r/359374 (cherry picked from commit 363ba00eab262307efc02880db06b1c5fb67fa92) Change-Id: I9dbadd831fa2f5b940ffb305a25ab56de63eec6e Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Signed-off-by: R Raj Kumar <rrajk@nvidia.com> Reviewed-on: http://git-master/r/363809 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2014-02-03ARM: DVFS: Add version number to dvfs tableKrishna Sitaraman
Add version number and print them as part of the dvfs table Change-Id: Ib60371aebd9f9ad1ad55b2e2a55cb03da2c61770 Reviewed-on: http://git-master/r/354699 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/361683 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Thomas Cherry <tcherry@nvidia.com>
2014-01-31ARM: tegra: dvfs: Update DVFS rail mode controlAlex Frid
When DVFS rail set mode interface is called on regulator that does not allow mode control at all, and requested mode does not match current mode, print warning only once to avoid cluttering console. If current mode cannot be retrieved as well, assume REGULATOR_MODE_NORMAL. Change-Id: I4725c885a43c8213c40d140dc4436599fd109162 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/362273 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-31ARM: tegra: dvfs: Add dvfs rail notificationAlex Frid
Added dvfs rail notification interface as a simple wrapper around the respective regulator notification. This is done in order to simplify registration for clients that are not (and must not be) consumers of the dvfs-managed regulators. Bug 1363113 Bug 1343366 Change-Id: I2e5a7aa5c1beb493c3a80fc36621582bd5089435 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/360764 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-01-30ARM: tegra: dvfs: Print rail connected infoAlex Frid
Change-Id: Ib6504fa6ff4fe018b0e0650c160d684fc3f401d3 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/361856 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-29ARM: tegra: dvfs: Enable connected dvfs railsAshwin Joshi
If CONFIG_TEGRA_DVFS_RAIL_CONNECT_ALL is set, enable rails and voltage scaling only if all required rails connect successfully. Otherwise, enable all those rails which connect successfully. Bug 1410210 Change-Id: I9ba692b4a3946dc31ce13dea863ffb493cf9e080 Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com> Reviewed-on: http://git-master/r/357668 Reviewed-by: Sandeep Trasi <strasi@nvidia.com> Tested-by: Sandeep Trasi <strasi@nvidia.com>
2014-01-27ARM: tegra: dvfs: Add interface to set fmax at vminAlex Frid
Added interface to specify clock fmax/vmin limits at run-time. Calling this interface updates frequencies in the respective DVFS table to be consistent with the new limits (voltage ladder is preserved): - for voltages below new vmin, the respective frequencies are shifted below new fmax to the levels already present in the table; if the 1st table entry has frequency above new fmax, all entries below vmin are filled in with 1kHz (min rate used in DVFS tables). - for voltages above new vmin, the respective frequencies are set at or above new fmax (not necessarily present in DVFS table before) - if new vmin is already in the table the respective frequency is set to new fmax (not necessarily present in DVFS table before) Since, such update may result in changing voltage requirement up at the same clock frequency, the interface can be called only for clocks that are allowed to override core voltage (SDMMC on tegra platforms), and only if core voltage is already overridden to the level higher than new vmin. Bug 1423423 Bug 1423429 Change-Id: I4f61ea6e3f8b6792ed058509339e16bff1947104 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/350016 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-17ARM: tegra: dvfs: Don't initialize SiMon offsetsAlex Frid
Removed SiMon offsets initialization when configuration option CONFIG_TEGRA_USE_SIMON is not set. This also prevented registration of SiMon notifiers (which would fail, anyway, generating unnecessary error logging). Bug 1343366 Change-Id: Ic54e6f113a172c2f6e7069c7a442e3e9cc0f8144 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/355377 (cherry picked from commit f04d13b84a8001c2018b3faab6d75b540e888fdb) Reviewed-on: http://git-master/r/356946 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-26ARM: tegra: dvfs: Dereference after null checkSumit Singh
Coverity id : 25069 Bug 1416640 Change-Id: I9fabafea8f6a00a9ec6f9f8d3e2ae2f6553d448d Signed-off-by: Sumit Singh <sumsingh@nvidia.com> Reviewed-on: http://git-master/r/343648 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com>
2013-12-18ARM: tegra: dvfs: Add nominal voltage to DVFS debugfs treeAlex Frid
Change-Id: I4e15f272018640b1c3054514e840d177b659b609 Signed-off-by: Alex Frid <afrid@nvidia.com>
2013-12-16ARM: tegra: clock: Re-factor DVFS initializationAlex Frid
Combined DVFS rail connection to regulators and DFLL initialization steps into one critical section protected by CPU clock mutex. Change-Id: Icb49b124b9f3f7d372324f5666e0d3f013182f66 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/345605 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-16ARM: tegra: dvfs: Force voltage scaling disable levelAlex Frid
Explicitly set disabled voltage level even when voltage scaling is disabled during kernel initialization (used to keep boot voltage as is in such case, that may result in unsafe frequency scaling after initialization). Change-Id: If8b4131cd2c7048a7cfc0c25ed5fca6be0e320f4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/345604 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-12ARM: tegra: dvfs: Update GPU DVFS debugfs nodeAlex Frid
Updated GPU DVFS table debugfs node to properly show maximum voltage across thermal ranges at current SiMon offset (instead of peak maximum voltage across all SiMon offsets). Bug 1343366 Change-Id: I3462cb888c944fc42620e7095cd864196124fc0a Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/339677 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-10ARM: tegra: dvfs: Allow voltage table replacementAlex Frid
Added interface to replace DVFS voltage table in flight. New table is installed provided peak voltages across possible tables are specified in advance, and new voltages do not exceed peaks. Bug 1343366 Change-Id: I2d8cf553cc8fb9d65d31afe11869104038b4bb4c Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/339674 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-10ARM: tegra: dvfs: Add SiMon offsets to DVFS railsAlex Frid
Added Silicon Monitor (SiMon) offsets to DVFS rail object. Offsets will be applied to minimum voltage requirements for the clocks in the respective rail domain. Implemented interface to verify expected offsets properties: all offsets should be equal/below zero, listed in descending order, starting from zero. Bug 1343366 Change-Id: Icb2afa77fcd60088284baf9b626e513034c0bb9e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/339673 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-09ARM: tegra: dvfs: Removed unused predict interfacesAlex Frid
Bug 1307919 Change-Id: I5a1db715be65b4ace106154ea6e7a30cefc46cfc Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/339371 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2013-12-09ARM: tegra: dvfs: Fix error handling in predict APIsAlex Frid
When clock rate passed to predict voltage interface exceeds maximum rate, return maximum voltage instead of error (to be consistent with clk_set_rate interface that just clips over clocking rate to maximum supported and don't return error). Added proper error check in predict peak voltage interface. Change-Id: I5d5bce7c63316e23a85329541967fd67dfa49124 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/339370 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-09ARM: tegra: dvfs: Refactor dvfs set rate functionAlex Frid
Re-arranged code to consolidate voltage array access in one place. Change-Id: I0c1136bc866b3741097bdbd390d8e281129e2ccb Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/339369 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-09ARM: tegra: dvfs: Fix GPU dvfs table debugfs unitsAlex Frid
Change-Id: I0f2e97083cc8a714e670d410a6c6b2ef04e83b0d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/339368 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Chris Dragan <kdragan@nvidia.com> Tested-by: Chris Dragan <kdragan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-05ARM: tegra: dvfs: Account for rail floorsAlex Frid
Updated predict peak voltage interface to account for rail floors: made sure peak voltage at any frequency is above maximum (cold) rail floor. Converted printout info about shared buses throttling limitation by maximum core rail floor into debug print, since this limitation is obvious. Change-Id: I2110f6a0721e5ed38fd9628df3087f9e3b98d42f Reviewed-on: http://git-master/r/338128 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2013-11-26ARM: tegra: dvfs: Add core rail Vmax cooling deviceAlex Frid
Added cooling device to cap frequencies of core shared buses based on core rail Vmax thermal profile. Thermal limits implementation is an extension of the existing core voltage capping mechanism, combined with core voltage override limits, and limits set from user space. Bug 1413311 Change-Id: I65e8b885f49318020e20d25425e257b7f0b0f66e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/335357 Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Prashant Malani <pmalani@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-11-19ARM: tegra: dvfs: Update voltage prediction interfacesAlex Frid
Allowed peak voltage prediction for clocks with alternative dvfs frequencies installed. The purpose of alternative frequencies is to provide lower voltage is some special modes. Hence, using primary dvfs frequency entries results in peak predicted voltage anyway. Still failed other predict voltage interface if alternative dvfs ladder is installed. Change-Id: Iebac2774c9d33cefddbd2756282f0494f65cca42 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/333091 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-11-19ARM: tegra: dvfs: Support persistent alt frequenciesAlex Frid
Existing interface to dvfs alternative frequencies combined enable control with alternative ladder installation. Hence, the only way to switch back to primary frequencies was to de-install alternative ones. This commit provided separate install and enable interfaces, so that alternative ladder can be installed once, and then enabled/disabled under client control. Also made sure alternative voltage-frequency mapping results in lower voltage at the same frequency (this was an implicit assumption of alternative frequencies support - now it is enforced explicitly). Bug 1397158 Change-Id: I4663602d1882f72156e02590f41ff04e7e69fbf8 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/333090 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-11-08ARM: tegra: dvfs: Re-name core cap interface/dataAlex Frid
Re-named interface and data object used to apply core rail override cap to include "override" feature designation in the name. Change-Id: Iedd5cd7ee28134db38c571feeb6b7703e75c8d28 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/328100 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-11-04ARM: tegra: dvfs: Add deferred override optionAlex Frid
Added an option to defer aggregation of module peak voltage into core override floor after DVFS initialization. This way the peak voltage can be determined based on board specific maximum rate rather than using maximum chip capability. Provided interface to specify deferred maximum rates, and platform specific call-back to adjust DVFS tables (when necessary) after final override floor is resolved. Override floor is reported equal to nominal voltage (i.e., zero override range) until all deferred limits are known. Bug 1372817 Change-Id: Iaee091a3dd95f1cbdb93efae71cbe6fa1048a895 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/323712 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-29ARM: tegra: dvfs: Don't apply upper bound to Vmax profileAlex Frid
Removed warning when Vmax thermal profile entries exceed rail nominal voltage - the profile limitations are satisfied in this case, anyway. Still fail profile initialization, and generate warning if Vmin profile entries are too high. Change-Id: I107ddd7843c1440d644b089477ae33e5a9fa493b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/304562 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-28ARM: tegra: power: Add dynamic CPU regulator mode controlAlex Frid
Operational mode of CPU voltage regulator depends on load current. Commonly on Tegra platforms this dependency was handled by regulator h/w itself. There are exceptions, however, introduced on some Tegra12 designs that requires s/w control of the mode. In order to dynamically control regulator mode based on load, s/w has to (a) estimate load based on CPU frequency, number of on-line CPU cores, and temperature (b) compare load estimation with regulator specific threshold whenever any of the above factors changes (c) change regulator mode when the respective threshold is crossed This commit adds layer (b) in cpu-tegra driver. It expects existing Tegra CPU load calculator in EDP driver to implement (a), and provide look-up table of frequency thresholds for each combination of on-line CPU cores and temperature ranges. When the respective threshold is crossed standard regulator mode change interface is called to carry on (c). Only switching between IDLE and NORMAL regulator modes is supported. The respective EDP calculator functions are just stubbed, for now. Bug 1302884 Change-Id: Iaea42a101aaea239643c0c80a7ad165ece3b1e36 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/301520 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-22ARM: tegra: dvfs: Install thermal DVFS peak voltagesAlex Frid
Initialized peak voltages array in DVFS structure for clocks that have thermal DVFS. Updated Tegra12 GPU DVFS initialization respectively. As a result peak voltage prediction interface now actually returns maximum voltage across thermal DVFS ranges at requested frequency. Re-used peak voltage array as safe DVFS table if registration of the scaling cooling device failed. Added peak voltages to debugfs. Bug 1307919 Change-Id: I7f004bc2cc4707cc4b50afacbca4e085e4c28c77 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/298528 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-22ARM: tegra: dvfs: Add predict peak voltage interfaceAlex Frid
With introduction of thermal dvfs, frequency-to-voltage mapping may be changed at run time with temperature. Therefore, s/w layers that rely on inverse voltage-to-frequency tables to determine frequency caps, should use peak voltages across all thermal dvfs ranges. Hence, this commit: - added the respective peak_millivolts entry in dvfs structure - added tetra_dvfs_predict_peak_millivolts() interface - modified EDP table calculation to use peak voltage prediction - modified core cap table construction to use peak voltage prediction, changed warning reported when voltage for minimum frequency is above core Vmin to info - this maybe true in some thermal dvfs range - modified override range calculation to use peak voltage prediction, added dvfs safe-guard in rail override mode to make sure that override limit is not violated in any thermal range For now, dvfs peak millivolts entries are not populated at all, and predicted peak voltage are based on dvfs table active at the moment in current thermal range (the same as standard predict voltage interface). Bug 1307919 Change-Id: Ia8d962c66efbcb98d227dab55b36bbba8d93ef5f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/289480 Reviewed-on: http://git-master/r/298527 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-16ARM: tegra: dvfs: Remove obsolete gpu_dvfs debugfs nodeAlex Frid
Change-Id: Idb9e5b225b2b94232200154e00f5843889516106 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/298529 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Chris Dragan <kdragan@nvidia.com>
2013-10-14ARM: tegra: dvfs: add missing arg to warnPhilip Rakity
/nvidia/DEV_KERNEL/kernel/arch/arm/mach-tegra/dvfs.c: In function 'dvfs_rail_update': /nvidia/DEV_KERNEL/kernel/arch/arm/mach-tegra/dvfs.c:417:3: warning: format '%s' expects a matching 'char *' argument [-Wformat] Change-Id: I3b012fdcc12ec364a8e82c3e9eea65be915bc5fc Signed-off-by: Philip Rakity <prakity@nvidia.com> Reviewed-on: http://git-master/r/298534 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-11ARM: tegra12: clock: Separate EMC DVFS voltage stepsAlex Frid
Separated EMC DVFS voltage steps from all other VDD_CORE clock domains, since EMC steps are, in fact, different, and can very for different board and DDR manufacturer combinations. Change-Id: I6f01e664ba70dbd105124e31dee8c805d3823217 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/289510 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Xue Dong <xdong@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-03ARM: tegra: dvfs: Add GPU scaling trip-points interfacesAlex Frid
Added common interfaces to set GPU scaling trip-points. Bug 1273253 Change-Id: I25f5870c00b1e3b8fb4fdcd685900512954a9125 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/280079 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> (cherry picked from commit 840ed28c2d5f35b3c6c8f8ce9c6a044a4bc57705) Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
2013-10-03ARM: tegra: dvfs: Construct safe thermal DVFS tableAlex Frid
Made sure maximum voltage across all temperature ranges is used for DVFS in case when scaling cooling device registration failed, or the device was not binded to thermal zone Bug 1273253 Change-Id: Iea2ba91db6174ee8e43dafb60f6bfee162ba65da Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/280078 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> (cherry picked from commit e58fbf1ba72f6dd8bdb7b67c2401ffb123562315) Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
2013-10-03ARM: tegra: dvfs: Fix predict millivolts interfaceAlex Frid
Predict millivolts interface selected pll or dfll mode tables based on target rate and dynamic dvfs state: rail mode, and current dvfs clock rate. Since interface clients may not be serialized with run time rate/voltage scaling (e.g., edp client) it opens possibility for races. On the other hand there is no need to use current dynamically changes state to select scaling table - comparing target rate, with initialized once dfll rate range is sufficient. This commit updated predict millivolts interface accordingly. Bug 1370030 Change-Id: I89167607d346ed5f2dfe1eedc27aabacd87e7303 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/276139 (cherry picked from commit 712e59d7f1f432719c5de51b03062954e63b6f1f) Reviewed-on: http://git-master/r/277521 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> (cherry picked from commit 4851b9e44d31e4703060f04b551f79655f50e788) Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
2013-10-03ARM: tegra: dvfs: Add GPU thermal dvfs table to debugfsAlex Frid
Bug 1273253 Change-Id: I4434f39434d505a1601b5f9275588b822302a937 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/279198 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> (cherry picked from commit 010f3fc5eb62ce35ad5d7c3ef191736d6d4afc55) Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
2013-10-03ARM: tegra: dvfs: Add dvfs thermal dependencyAlex Frid
Added temperature dependency to dynamic voltage scaling. When thermal dvfs table is installed for the particular clock, voltage required to run at any frequency is no longer assumed constant (i.e., worst case) across entire operational temperature range, but determined according to temperature index set by thermal dvfs cooling device. The following limitations are enforced by current implementation: - thermal dvfs is applied only when rail is in pll mode (in dfll mode voltage on temperature dependency is taken care of by dfll h/w). - tabulated voltages at any temperature must increase monotonically with frequency (monotonicity is not expected at iso frequency across temperature ranges). - voltage for any frequency/temperature combination must be within the respective rail minimum/maximum limits - thermal dvfs is supported, for now, only on GPU clocks Bug 1273253 Change-Id: I4cf2ff1ae862c32c2d2fc57b9b4c98e316539024 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/278103 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> (cherry picked from commit e0baf0bf9a692894e49c4d59c15a52f2fd405aa6) Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
2013-10-03ARM: tegra: dvfs: Add thermal dvfs cooling device opsAlex Frid
Added thermal dvfs cooling device operations to support voltage and frequency scaling with temperature. Renamed tegra_dvfs_rail_cooling_ops to tegra_dvfs_vmin_cooling_ops to differentiate with newly added tegra_dvfs_vts_cooling_ops. Bug 1273253 Change-Id: I7f8f9082d683883920e80d1e68331f4c0f1a53c6 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 13790063b65041f1cf171ad058b8f9b4df8ca1b6) Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
2013-10-03ARM: tegra: dvfs: Handle zero GPU rail voltageAlex Frid
Preserved voltage of the rail with in-band enable / disable control when all clocks associated with dvfs rail are disabled, and "0" voltage is requested. The rail will be turned off via explicit call to regulator interface - applicable to GPU rail. No changes if "0" voltage is requested for rail with side-band control, and jump-to-zero property - CPU rail: allow to pass "0" through, mainly for statistical purpose. Added warning and preserve voltage if "0" requested for core rail - must never happen (core system clocks are never disabled at run-time). Change-Id: I724ea9373d0731d6f115ecde1e3b8dd8e7ff2884 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/278180 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Prashant Malani <pmalani@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> (cherry picked from commit fab7582bcae0c63a645aa2cbb9e1e001b4b5603c) Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-12-28 13:43:11 +0000