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path: root/arch/arm/mach-tegra/edp.c
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2013-09-14arm: tegra: Move all tj dependent thermals from nct to soc_thermDiwakar Tundlam
Functions moved are vdd_cpu, core edp. Raised shutdown limit for nct. Added two higher temps for cpu_edp to support higher soc_therm temps. Doing this only for Dalmore, Pluto, Ceres, Pismo. No real changes to Roth. Bug 1200075 Change-Id: I2b4ac4ba7cd933bd47c30ab2ad9eabb3a3da5fbe Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/195331 (cherry picked from commit 2af79db3c5763d3a0b6e78663ccf1ad6c04be134) Reviewed-on: http://git-master/r/197096 GVS: Gerrit_Virtual_Submit
2013-09-14arm: tegra: edp changes due to thermal_trip_info use in driverDiwakar Tundlam
Bug 1200075 Change-Id: I96b01b1caa468c0d376e79b416aeb329e1cb0390 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/190820 (cherry picked from commit bedff5775d6dab5870a777a1b5a1abfc9e23b033) Reviewed-on: http://git-master/r/193896 Reviewed-by: Automatic_Commit_Validation_User
2013-09-14arm: tegra: move common edp cdev init to edp codeDiwakar Tundlam
Moved repetitive platform initalization of edp features to common areas in preparation for handling these cdevs from soc_therm. Bug 1200075 Change-Id: I8f7fe45d8f0797c72272e5ee1db3707493ec90a5 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/190765 (cherry picked from commit f36a20dd1bce7314a97f48213f2180b0a7440a97) Reviewed-on: http://git-master/r/192538 Reviewed-by: Automatic_Commit_Validation_User
2013-09-14ARM: tegra11: power: Add CPU EDP safety limitsAlex Frid
Added fixed absolute CPU EDP safety limits that are applied on top of calculated EDP limits across all temperatures and process corners. Bug 1161126 Change-Id: I9cb33a0a94115a83220d9b70950823fcbbf96427 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/187570 (cherry picked from commit 356cec5d26b07603e2014aedaf197354b52ee1d6) Reviewed-on: http://git-master/r/188919 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra11: dvfs: EDP freq granularity to follow CPU dvfs tablesDiwakar Tundlam
Bug 1170986 Bug 1161126 Change-Id: I8d83903a58d9099fec7b04fadc558244177ebbbb Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/173531 (cherry picked from commit f5e680768419f7e50f1ba9420e92d25ba0644327) Reviewed-on: http://git-master/r/174343 Reviewed-by: Automatic_Commit_Validation_User
2013-09-14ARM: tegra11: dvfs: Update CPU dvfs tables and binsAlex Frid
Based on characterization results: - Integrated new cvb dvfs coefficients - Expanded DFLL operating voltage range to 0.9V ... 1.35V with 1.0V as dynamic tuning threshold - Added speedo_id 2 to differentiate fast parts - Duplicated CPU EDP table for new speedo_id Bug 1170986 Bug 1178825 Bug 1161126 Change-Id: I49ccdb7c3d734dcdd3bb9f2542683d418d21ab5f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/170368 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: tegra11: power: Add A01P CPU EDP tableAlex Frid
Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: Iea6aff82147bfebf9f4d16d6f6de6c7dea3d9d11 Reviewed-on: http://git-master/r/168244 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2013-09-14ARM: tegra: restructuring battery EDP init codeSivaram Nair
The EDP manager init and registration code is slightly restructured in oder to decouple the config flags CONFIG_EDP_FRAMEWORK and CONFIG_TEGRA_EDP_LIMITS which are otherwise independent. Change-Id: I48f0fb198fbf2ac2118e95293a6ac7ecd1abdcab Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/166903 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14ARM: tegra11: power: Add core EDP basic implementationAlex Frid
Added mechanism to limit maximum GPU and memory frequency in order to keep core rail current within power supply capabilities. The actual limits yet to be characterized, and they will depend on (a) Chip SKU (b) Regulator current limit (c) Slow (LP) CPU state (On/Off) (d) Temperature range (trip-points TBD) (e) User profile (balanced, favor GPU, favor EMC) (f) Core module state (reserved) Dependencies (a) and (b) are resolved statically when core EDP is initialized for the particular chip. Core EDP limits will be changed dynamically when run-time conditions (c), (d), (e), and (f) are changed. This commit implements only initialization of the core EDP limits table and debugfs access to the table. Dynamic control is not implemented. EDP table data is just a template. Core EDP configuration option is unselected by default. Bug 1165638 Change-Id: Ia1187f4e5d59d2668a5058e47fea7ae668018413 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/164832 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2013-09-14ARM: tegra: dvfs: Recompute EDP tables after dfll mode changesDiwakar Tundlam
Also recompute on clock-late-init for EDP table with correct dfll mode Bug 1167145 Change-Id: Icff6c1c4b8fb7d861951abb0b4b6edbfeec32dba Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/161773 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14arm: tegra: power: update model parameters for VDD_CPU EDPDiwakar Tundlam
Bug 1167145 Change-Id: I485d86c42c90351b3207f5dbd1b7b5a8188b6e50 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/160721 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2013-09-14arm: tegra: power: cleanup dynamic VDD_CPU EDP capping codeDiwakar Tundlam
Refactor data structures and names in preparation for dynamic/leakage parameters update. Bug 1046108 Change-Id: Id7ed9b4a5aedbd8556fa1520eab93e91fd728556 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/159377 Reviewed-by: Automatic_Commit_Validation_User Rebase-Id: Rd16cf64ce8ba7c2c978e129675dd5d823fb46147
2013-09-14arm: tegra: power: ignore duplicate reg_override valuesDiwakar Tundlam
and some clean ups Change-Id: Ic5c239cea8921ae4b5639dd8439c569fa89cb1ec Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/159375 Reviewed-by: Automatic_Commit_Validation_User Rebase-Id: Ra59d8e3a57782ac1f830243b94827aa1ff34a238
2013-09-14arm: tegra: power: check chip-id and select table or calculated edpDiwakar Tundlam
Change-Id: Ib1b6641095d3568e339c1e56a199157d8f25ad84 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/142786 (cherry picked from commit 8de620ebdaf0426bf64db2a0d3feb04f003b11f8) Signed-off-by: Gaurav Batra <gbatra@nvidia.com> Reviewed-on: http://git-master/r/146699 Reviewed-by: Automatic_Commit_Validation_User Rebase-Id: Rc75b6c21137aa26c6bff2848d18b72c99f407b07
2013-09-14arm: tegra: power: fix dynamic VDD_CPU EDP capping granularityDiwakar Tundlam
Changed freq-step to ensure EDP freq caps line up with actual cpufreqs Also since min-cpufreq changes after bootup, don't use min, use 0. Change-Id: I57498b719b06f7dd3bade5b2038277c2564c69cc Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/141055 (cherry picked from commit 37d92240720f40c0528188ec4409ac5055397e4b) Signed-off-by: Gaurav Batra <gbatra@nvidia.com> Reviewed-on: http://git-master/r/146678 Reviewed-by: Automatic_Commit_Validation_User Rebase-Id: R0b740fe222bf61eb2aadb5356df878770414b3b2
2013-09-14arm: tegra: power: enable dynamic VDD_CPU EDP cappingDiwakar Tundlam
Using the model used to enforce max frequency for a given VDD_CPU EDP. Enabled for dalmore and pluto. Initialised edp_reg_override to 6A and increased default per-platform edp-limit higher by 6A to allow users to override the limit up by upto 6A when needed for specific use-cases. Change-Id: I2741ba7316cebe0ae2836b84c4b3bbbe0afefe5e Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/134306 (cherry picked from commit 9648d86f4a9a7b3b2557e98530e8265ea9f53467) Signed-off-by: Gaurav Batra <gbatra@nvidia.com> Reviewed-on: http://git-master/r/146677 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R41ff83ba9a5dd4c1799961cc00dc6e796a93c8ba
2013-09-14arm: tegra: power: Update dynamic CPU EDP modelDaniel Solomon
Update the model used to calculate max frequency for a given VDD_CPU EDP. Change-Id: Id220f25b58880c936f621f07faae414be42e8971 Signed-off-by: Daniel Solomon <daniels@nvidia.com> Reviewed-on: http://git-master/r/133051 (cherry picked from commit eca6edfc4220c5d0a004e9655926ea805c485152) Signed-off-by: Gaurav Batra <gbatra@nvidia.com> Reviewed-on: http://git-master/r/132941 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: Rc0a772f04ed867da313d2044f6bc6a26ae58cd57
2013-09-14arm: tegra: power: fix coverity issueSri Krishna chowdary
Fix Unsigned can't be less than zero issue. tegra_dvfs_predict_millivolts returns int, so voltage_mV can't be unsigned int. Bug 1046331 Change-Id: I7973c3a434beef1cc54c4d61024b0b381c4fc66f Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/142152 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com> Rebase-Id: R9cb9294b7d575aa5aa45207720d0fb42dd2fda68
2013-09-14pm: EDP: t114: adding battery EDP managerSivaram Nair
Battery EDP manager is added for Pluto and Dalmore boards. Change-Id: I7a3fd1e7621f6c0c0a873185b23a8b81947b16a9 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/132526 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R1f3821b5d08d378387da9728aec7696ae46a624a
2013-09-14edp: edp nodes moved to $DEBUGFS/edp/vdd_cpu/Mitch Luban
Moved edp nodes to $DEBUGFS/edp/vdd_cpu/ so that EDP manager and VDD_CPU_EDP capping have equal footing in debugfs namespace. Requires the following changes: http://git-master/r/131482 http://git-master/r/131272 http://git-master/r/131273 Bug 1046809 Change-Id: I61184bf8bd54a2a701fd4182b421b0da229883b7 Signed-off-by: Mitch Luban <mluban@nvidia.com> Reviewed-on: http://git-master/r/131271 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com> Rebase-Id: R53b209ad7c921751165797462049f5f8a5641094
2013-09-14arm: tegra: power: Add debugfs entry for CPU regulator limitDaniel Solomon
Add a debugfs node to override VDD_CPU regulator current limit at /d/edp_reg_override. Values written to this node will be subtracted from the regulator's current limit; EDP table will be recalculated accodingly. Change-Id: I523fa73bf5a8fa806477f4884e920b5866417cf3 Signed-off-by: Daniel Solomon <daniels@nvidia.com> Reviewed-on: http://git-master/r/118815 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R91e8e4722dfc06a003c3730e9a5a4a20d29a52e5
2013-09-14arm: tegra: power: Add dynamic CPU EDP mechanismDaniel Solomon
Add dynamic VDD_CPU EDP. This mechanism calculates EDP frequency caps based on dynamic power, leakage power, and CPU regulator current limit. The formula for this uses temperature, number of cores, and CPU IDDQ as input. It relies on sets of pre-calculated constants, which vary per SKU. This mechanism complements the existing EDP mechanism. At bootup, chip SKU is read: If a corresponding hardcoded EDP table is found, this table is used; otherwise, an EDP table is calculated. Note that the EDP formula used is subject to change, and final sets of pre-calculated constants still need to be added for each SKU. Change-Id: I5fb22c6a3da0f0adff21dcdf4950275002927e88 Signed-off-by: Daniel Solomon <daniels@nvidia.com> Reviewed-on: http://git-master/r/116120 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: Rcd73d8b4bd0e5ade35216b63af9da6a6e4ba2ab4
2013-09-14arm: tegra: power: Refactor VDD_CPU EDP initDaniel Solomon
Refactor VDD_CPU EDP initialization in preparation for addition of dynamic VDD_CPU EDP. Change-Id: Id79c6d6835fd0a940f0bc911023ed9d5d846848c Signed-off-by: Daniel Solomon <daniels@nvidia.com> Reviewed-on: http://git-master/r/118372 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R145f36dac3a36aa51a6892bb5e819ce11f1e2bf7
2013-09-14unknown changes from android-tegra-nv-3.4Dan Willemsen
Rebase-Id: R940fad74c7e91ef3d1d3d589a48064ccb7335541
2013-09-14arm: tegra: power: Add AP33 Battery EDP tablePeter Boonstoppel
Exact copy of AP30 table Bug 926056 Change-Id: I48730c41605b177d267a569804bbc75a6b94cfba Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/85233 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: Rf882b5566c8619ddbbe4c98ca6b7ef9717807639
2013-09-14arm: tegra: power: Updated EDP table to latest specDaniel Solomon
Added new tables for T37/T33A (same table as T33) and AP37 Bug 844268 Reviewed-on: http://git-master/r/77662 Change-Id: I51e0939eb2f1f5582215bc409cf2d8eaf9890fba Signed-off-by: Daniel Solomon <daniels@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78709 Reviewed-by: Automatic_Commit_Validation_User Rebase-Id: Re0aec18339a1f71bc8c6f31eed741357bbbb867e
2013-09-14arm: tegra: power: Updated EDP table to latest specDiwakar Tundlam
Changed 20C to 23C to account for hysteresis effect Bug 844268 Change-Id: I11fca162db737e8cf81c31bf38575ecc42a730df Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/75049 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Reviewed-on: http://git-master/r/75538 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: R670b117ccf30d439de4b3063d8b50e38b866fa37
2013-09-14arm: tegra: power: Enhance debug EDP tableDiwakar Tundlam
Bug 844268 Change-Id: I16327668c5df0ead318753f753be1680980ad9c1 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/75030 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/75537 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: Rcfbe1c77c11bee7d59c99398c0e2d2fd3583f4c1
2013-09-14arm: tegra: power: Updated EDP table to latest specDiwakar Tundlam
(see bug for Excel with the new spec) Bug 844268 Change-Id: I7a3bdd674b987c2edd540de7764e01338f66c0ac Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/74094 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/74893 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Ra86df1a80bf0b7e05efca69a736aba16ca55a3b4
2013-09-14ARM: tegra: power: Limit CPU rate on system EDP alarmAlex Frid
System electrical design point (EDP) alarm is generated when system power source (battery) over-current is detected. Part of the system EDP management is CPU frequency capping added by this commit. Maximum CPU clock frequency is pre-determined depending on number of CPU cores on-line. It is combined with CPU regulator EDP limit and applied to final CPU rate; CPU voltage is scaled down by DVFS, respectively. The system EDP limit of CPU rate is removed after alarm is canceled. EDP event can be emulated via debugfs entry /d/cpu-tegra/edp_alarm. (cherry picked from commit fa673d27766ff9513139e94a498e4c24827d7c57) arm: tegra: power: Removed erroneous ';' (cherry picked from commit b4b404381b2d1823b7c127858950f853428fe3b5) Change-Id: I60ec0e87f9442b698a8824895aac0a1f955565b4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/67823 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R6a004bea8dfc99cd965f94035481907007bd1e32
2013-09-14arm: tegra: power: Added EDP table for Tegra3 xLDiwakar Tundlam
Bug 844268 Change-Id: Iddffd445401318fb0e64d6739dbf833da7daede9 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/68313 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Rc62624a34cb15039023c46f53c1c07119dbed007
2013-09-14arm: tegra: power: Updated EDP table to 9/12/2011 specPeter Boonstoppel
(see bug for Excel with the new spec) Bug 844268 (cherry picked from commit 036969082d6571a26572cfe80f62144be87e732b) Change-Id: Iacc9081ace5629588b7634d2927d9ea5a7c8c91b Reviewed-on: http://git-master/r/57095 Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/68257 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R1d5a65cedf5c222b5368c9e883543210ae161406
2013-09-14ARM: Tegra: power: Tegra3 T33 set EDP limits correctlyDiwakar Tundlam
bugid 844268 Use correct regulator current value obtained from bootloader Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Change-Id: I9059a5e83c88c6fc0e933acd3c4ab6e6b9c35078 Reviewed-on: http://git-master/r/67025 Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Rebase-Id: Rce035e804a189df47a5b5c2a03f418d88cd9147a
2013-09-14ARM: Tegra: power: Tegra3 T33S updated EDP limitsDan Willemsen
bugid 844268 Reviewed-on: http://git-master/r/65547 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> (cherry picked from commit 72d41cc5200454175d8dc04c761c983405e4d901) Change-Id: Ica5aaf0bedb02bff3485cdcb76e81da80896a309 Reviewed-on: http://git-master/r/66520 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R7ed6a74e13a6900490c83a15f5adc00c5163d663
2013-09-14ARM: Tegra: power: Tegra3 AP33 SKU updated EDP tableDiwakar Tundlam
bugid 844268 Reviewed-on: http://git-master/r/64185 (cherry picked from commit a27e20a84ce1bab8a1d37f12f7f9260d9d32dbfe) Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Change-Id: I88b108fd44719828e11499606ab7ef754f76ebac Reviewed-on: http://git-master/r/65290 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R557e282e415fd4bed871ea1ed8c056ae79731311
2013-09-14ARM: Tegra: power: T33 SKU EDP table for 10A regulatorDiwakar Tundlam
bug 841336 Reviewed-on: http://git-master/r/62766 (cherry picked from commit c27e091be2ec3899fbb0bdbfe199784063f24be1) Change-Id: I40277cea7f48cc15e074123ee73287b25389c0e6 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/64211 Rebase-Id: Reef8906240656bfee07dbf9ba8f581677bad8e5f
2013-09-14ARM: Tegra: dvfs: T33 SKU EDP tableDiwakar Tundlam
Bug 841336 Reviewed-on: http://git-master/r/60779 (cherry picked from commit 4d3f017e2715f50aaca6c7e8dc61e880947f7550) Change-Id: Ib1eeb8729a91162d39fc952eeb7494d8863a03c7 Reviewed-on: http://git-master/r/64204 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: Rcfa5f6c11e831c4f08e956609ea8f9d98a6111f8
2013-09-14arm: tegra: power: set throttling temperature = 85CDiwakar Tundlam
Earlier value of 75 had unnecessary double guardbanding. Changed 90C row in EDP table down to 85C to get throttling alert. Bug 862301 Reviewed-on: http://git-master/r/50544 (cherry picked from commit 9f2693a80274bcd9eb8e7424bca87f34cc190741) Change-Id: If7204150013e7894fc310a2f7e8fd46baf11d869 Reviewed-on: http://git-master/r/62773 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6dacf9402de8edbb02bddb08b138808628b7eb15
2013-09-14arm: tegra: add edp limit to debugfsJoseph Lehrer
bug 865842 Original-Change-Id: I54dcf3e2e968692746f1d8b17bdf912305f547a2 (cherry picked from commit 5b9dce25485824036f86db093b28a45a3cd86c76) Reviewed-on: http://git-master/r/48257 Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R1adb1ca832e0f63f1e5b7e405f4c87c4a8a7aabe
2013-09-14ARM: tegra: power: Update to EDP tablePeter Boonstoppel
- updated EDP table for AP30 A02 2.5A to match data from Bug 844268 - updated EDP cap for single core on AP30 A02 to 1.3Ghz - changed EDP table for A01 to match AP30 A02 Original-Change-Id: I1722768f235d63a2f311d082d8126ba071226eb6 Reviewed-on: http://git-master/r/46482 Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rc98aaffd4568b9ad642696eef5f559d9c7fd7237
2013-09-14arm: tegra: enterprise: EDP supportDiwakar Tundlam
Added EDP support for Enterprise board via ext temp sensor nct1008 Bug 824621 Original-Change-Id: I476b9ad2cb46620d4775e6ee6e102b45f2b4dc27 Reviewed-on: http://git-master/r/43144 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R0a59e82334166da1abfbc5a748ff4285e66590a4
2013-09-14ARM: tegra: power: Added global EDP Capping tablePeter Boonstoppel
- Added table with EDP Capping values for different SKUs/regulator currents in new file edp.c - New entry point tegra_init_cpu_edp_limits() - Added DebugFS entry under debug/edp to list the currently selected EDP table - Populated EDP table in edp.c with data from Bug 844268 - edp.c keeps main EDP table; cpu-tegra.c and board-cardhu-power.c both read from there Bug 840255 Original-Change-Id: I55c2ee16278be8cd3005218bedebe76846d137d8 Reviewed-on: http://git-master/r/40938 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc598b39c3517e10c3c5052258e5a3e444f092b96
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-29 19:03:28 +0000