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Change-Id: If6cd2914551331bd49b128ad3143a0d7adf0f120
Reviewed-on: http://git-master/r/13396
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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spare fuse bits 18 and 19 are used to distinguish A03p Tegra 2
chips from A03 chips. this is needed on some platforms to
determine whether or not LP0 suspend should be enabled.
Change-Id: I03a964eac3783535357faecee8cd35e65350b356
Reviewed-on: http://git-master/r/12078
Tested-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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There is a dependency loop between fuses, clocks, and APBDMA.
If dma is enabled, fuse reads must go through APBDMA to avoid
corruption due to a hw bug. APBDMA requires a clock to be
enabled. Clocks must read a fuse to determine allowable cpu
frequencies.
Separate out the fuse DMA initialization, and allow the fuse
read and write functions to be called without using DMA before
the DMA initialization has been completed. Access to the fuses
before APBDMA is initialized won't hit the hardware bug because
nothing else can be using DMA.
Change-Id: Ib5cb0f346488f2869e8314c5f3b24fd86873f4c3
Signed-off-by: Colin Cross <ccross@android.com>
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expose fuse register read and write apis for fuse
burning
Change-Id: Id6785f5506fe9293ddb5072240f49470ca5fcd08
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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tegra2 hangs if fuse registers are accessed during an apb dma
operation. war is to use apb dma to read/write fuse registers
instead.
Change-Id: I4d99a1ad56115c0d73e9cd0679cf38f70f922f3d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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The Tegra SOC contains fuses to identify the CPU type and
bin, and a unique id. The CPU info is required to determine
the correct voltages for each cpu and core frequency.
Signed-off-by: Colin Cross <ccross@android.com>
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