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Re-arranged the order low corner limit is applied to voltage request
to guarantee that no actual PMU transaction is triggered (= no clock
control re-entry) if peripheral clock is disabled concurrently with
low corner increase.
Bug 717899
Change-Id: I854164998fa8e88651950fb5aeed3b8595c3c10b
Reviewed-on: http://git-master.nvidia.com/r/3757
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Iqbal Bhinderwala <iqbalb@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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If transfer started and driver waits for transfer completes with
given timeout, and if transfer have not completed in a given
timeout then driver handles the erro_timeout case. In this
error handling, it does not need to call the Interrupt done
as it has not been interupted yet.
Calling unnecessarily InterruptDone create warning for
unbalanced call.
Change-Id: Id7f924eefcd49131b9f752d530b108ab08874b57
(cherry picked from commit 31bc11d7583d089673cb0c474f210343a729e8da)
Reviewed-on: http://git-master/r/4377
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Used microsecond timer to track CPU1 On/Off delays, instead of DVFS
tick count (the latter can be stopped in LP2, resulting in CPU1 hotplug
request extension). Set On/Off delay to 1.5sec/1.0sec, respectively.
Change-Id: Idde0173f90041796ffcc0b26d865b46a48a27864
Reviewed-on: http://git-master.nvidia.com/r/4743
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Iqbal Bhinderwala <iqbalb@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Added sysfs node /sys/power/nvrm/core_lock to dynamically select lowest
tegra power state in conjunction with static ODM query:
- if ODM query specifies DeepSleep as lowest power state and core_lock is
cleared, tegra platform enters DeepSleep (LP0) when system is suspended
- if ODM query specifies DeepSleep as lowest power state and core_lock is
set, tegra platform enters Suspend (LP1) when system is suspended
- if ODM query specifies any state other than DeepSleep as lowest power
state, core_lock is ignored (tegra platform follows ODM specification
in suspend)
Addresses bug 697619, facilitates LP0/LP1 testing.
Change-Id: Id2d046ba202cf7630cff5e9b524995ec5e867eaa
Reviewed-on: http://git-master/r/4127
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Preserved EMC, AVP, and system bus clocks during RM resume instead of
setting them to maximum. This is necessary, since some PMUs set fixed
boot core voltage value after LP0, which may be below nominal. DVFS
will scale the above clocks after resume along with core voltage as
necessary.
Change-Id: I33ad90f39696eca569bd3bd76bb3cbf72ed18681
Reviewed-on: http://git-master/r/4569
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
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- Disabled support for main clock doubler as AVP clock source (h/w
recommendation). Adjusted PLLP policy entries to compensate.
- Extended PLLC use for AVP clock scaling into 108MHz-216MHz range to
provide better granularity than PLLP is able to.
- Moved VDE v-scale reference update from preview to configuration phase
(synchronized with actual clock change). Still kept voltage requirement
evaluation during preview, so that core voltage is increased before the
change.
Change-Id: Iefc1899bd57b7f0034e945239c09b5805ebebdbb
Reviewed-on: http://git-master/r/4508
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Sharad Ranjan <shranjan@nvidia.com>
Tested-by: Sharad Ranjan <shranjan@nvidia.com>
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Fix for bug 710667
Previous calculation gave x4 times longer time interval then necessary.
Also algorithm did not work correctly on odd time intervals.
Change-Id: I0f123b27e8102f3f1e49e0ebf507c6a75a3abec0
Reviewed-on: http://git-master/r/4576
Tested-by: Victor Ryabukhin <vryabukhin@nvidia.com>
Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
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It is recommended by ASIC to make sure that fifos are empty
before starting any new transfer specially dma based transfer.
Adding support code for this.
Change-Id: Ic6b5db650b50e664b5cdd601eed9e0c3286a764b
Reviewed-on: http://git-master/r/4211
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Tested-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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The rm spi driver is using the nvrm dma driver which is wrapper
over the native dma. Using directly the native dma driver to
get rid of one more level of wrapper call from spi driver.
Making sure that prev dma operation is completed before starting
new transfer.
Removed the code which was specific to OAL as this is not
required any more.
Calling the write buffer barriers after writing into the write
dma buffer and before starting the transmit dma to make sure
that all written data is available in physical memory before
dma start.
Change-Id: Iabcd86f0d63b2decffda0ad6da6f1b22161e9d3b
Reviewed-on: http://git-master/r/2670
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Tested-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Added configuration options to set default LP2 policy.
Change-Id: I81820f575858dda62d31b304b6adf09f7d0f3689
Reviewed-on: http://git-master/r/4164
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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The problem is that some drivers can keep GART memory pinned, fragmenting
it and making impossible to pin the memory allocated in other process.
24M limit on GART made situation less probable but didn't solve it
completely.
This fix disables GART allocation for ap20rm_i2c driver.
Change-Id: I22889a58ca9f6c0e38b00301abd36e272654e7d4
Reviewed-on: http://git-master/r/4150
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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When there is timrout happen in the requested slave transaction,
driver should rerurn the NvError_Timeout.
Currently the error status was overwritten by other api status and
so was not returning the correct error.
Fixing this issue.
Change-Id: Ie2d8600824ea837ec7fed94246a7a17e23d49d56
Reviewed-on: http://git-master/r/3921
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Tested-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Use a variable instead of scratch register for storing lp2 time.
Scratch register usage was overwriting the data required for
wakeup from deepsleep.
Change-Id: Ifcc660c35a31d776d085e6b0d54205e544affa2b
Reviewed-on: http://git-master/r/3887
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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It is require to change the peripheral bus width dynamically.
Provide option to select the peripheral bus width through the
structure NvRmDmaClientBuffer.
The bus width information is passed with upper 16 bit of the
wrapsize parameter which is member of struct NvRmDmaClientBuffer.
Change-Id: I3e1dc84c08b98d7337ca7e661715abb3dc54667a
Reviewed-on: http://git-master.nvidia.com/r/3243
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Set different LP2 policies based on SDRAM typed:
- "Ignore Low Corner" for DDR2 platforms (no changes, since DDR2
scaling is limited).
- "Mask in Low Corner" for LPDDR2 platforms - changed so that DVFS
continue to run until LPDDR2 frequency reaches low corner.
This change should compensate increase in core/SDRAM power observed
for low power use cases after switch to 2.6.32 kernel (bug 697013).
Change-Id: I5f6ed7196bb03bd3182d858760c50f2072afe494
Reviewed-on: http://git-master.nvidia.com/r/3654
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Sharad Ranjan <shranjan@nvidia.com>
Tested-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Modify gpio module to use regulator module for controlling GPIO power rail.
Since there are some issues related to init sequence after this change, using
"postcore_initcall_sync" to involve regulator module, as well as modifying
NvRmOpenNew routine are required.
Bug Id 697774
Change-Id: Ie8002f1190da83355c0554496f9fef24d18207f5
Reviewed-on: http://git-master/r/3103
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Moved PMU related suspend procedures from RM kernel suspend to the
PM_SUSPEND_PREPARE pm_notifier callback. This is necessary as RM kernel
suspend is invoked after interrupts are disabled, and no interrupt based
transactions can be used. Similarly, moved PMU resume configuration to
the PM_POST_SUSPEND pm_notifier callback.
Bug 701894
Change-Id: I1614a968cc1b039f809b165877fcf1595c7cc596
Reviewed-on: http://git-master/r/3221
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Added oscillator as HDMI clock source. This configuration is
possible in VGA mode, and must be supported to keep HDMI in
sync with Display.
Change-Id: I57aaa9126876ad9a35acad02bab3e4979d8e1f6a
Reviewed-on: http://git-master/r/3120
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Arthur Spence <aspence@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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- Updated cpuidle driver parameters:
Determined LP2 state target_residency as a break even time balancing the
power cost of LP2 entry/exit (estimated via LP2 latency), and LP2_vs_LP3
power saving - this approach is consistent with governor interpretation
of residency. As a result the latency_to_residency factor reduced from
2.0 to 0.3. Included exit latency into idle time returned to governor to
avoid double subtraction (by platform code and governor code) - otherwise
under-reporting of LP2 time would skew downward governor correction
algorithm. Replaced hard coded power good time with platform data.
- Updated DVFS parameters
Set CPU minimum frequency to 216MHz - additional dynamic power will be
compensated by savings due to increased LP2 residency (216MHz is provided
by low power PLL, and still allows CPU to run at lowest possible voltage).
Changed maximum CPU/EMC frequency ratio to match new low corner settings.
Change-Id: Ic58d0dd628f51bc3ede61a83c87792fca4f0845b
Reviewed-on: http://git-master/r/2916
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Make sure the I2C close() function pointer has been initialized
before trying to call through that pointer. This can happen
if I2C open fails because there is no ODM configuration for the
requested controller/instance combination.
Change-Id: I790272463dad0211a439cddac61f45f36325272b
Reviewed-on: http://git-master/r/3030
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Change-Id: I6855c9cfcfaf2646569fcad5ae0090eb47f11dff
Reviewed-on: http://git-master/r/2963
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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(A) Interval (... 90C) - no throttling, free running system
(B) Interval (90C, 115C) - active throttling of CPU frequency with
- gradient: -100 MHz/2 sec
- low limit: 50% of CPU frequency maximum
(C) Above 115C - h/w shutdown.
Bug 528708
Change-Id: Id4d57521f378eb72e740c9dc55a2814f8100384e
Reviewed-on: http://git-master/r/2851
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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McErrorIntHandler() is no longer used. Remove it.
Change-Id: Ie63c2227bd9090fa2873ac17fadf2ed2fc3f4395
Reviewed-on: http://git-master/r/2795
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Change-Id: I0841c494462e4c2b2fd9f58cc0a3ad0305e5914a
Reviewed-on: http://git-master/r/2735
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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SPI driver normally enables / disables CPU and bus frequency boost
at the start / end of each SPI transaction. Instead of turning off
frequency boost immediately at the end of each SPI transaction, use
a timeout period after which frequency boost hints will time out.
The timeout period is calculated based on the number of bytes in
the SPI transaction and the SPI clock rate. The timeout insures that
frequency boost is still active in between multiple SPI transactions.
This has the side effect of increasing SPI data transfer rate for
multiple SPI transactions.
This was a cherry-pick from android-tegra-2.6.29
id: I088127ebb5ea07810dac824bfafd3f99ae6c96f2 and
applied to the android-tegra-2.6.32.
Change-Id: I765e892cb34a4fff8d8607cdf52cec065979c6e7
Reviewed-on: http://git-master/r/2338
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Tested-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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It is require to use the hw based CS to meet the timing requirement as:
- Minimum CS setup time i.e. time from CS active to first clock.
- Maximum CS hold time i.e. CS should be active after last clock.
SW based CS can support the above 1 but not 2 because it dpeneds on os
load and system performance. To meet the above requirements, it is
require to enable the hw based CS.
As spi controller support for the hw based CS for the smaller number
of packet, enabling this feature.
Driver use the sw based CS by default. If client want to use the hw
based CS, then it need to enable this through nvodm query
NvOdmQuerySpiDeviceInfo table for different CS.
For this, client need to set device info as
CanUseHwBasedCs = TRUE,
CsSetupTimeInClock = xx
CsHoldTimeInClock = xx
Change-Id: I9e943e0b39f2d75272826cc2ec7687b3434b1c2a
Reviewed-on: http://git-master/r/2536
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Change-Id: I9bb3607e9605eefd5c0eec07a8be3fafce9bae64
Reviewed-on: http://git-master/r/2528
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Skipped spare clock h/w access when DVFS is running - it was not used,
anyway, since all rates in this case are available in DVFS variables.
Change-Id: Id324c7904e30ea8fe50b319cfd06c75a721b6b3f
Reviewed-on: http://git-master/r/2458
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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This is a port of change 1465 from android-tegra-2.6.29.
Change-Id: Ibca32ecc0424fae28e4db04977722f7d7a6c6938
Reviewed-on: http://git-master/r/2502
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Added support for wake event delay, and CPU power off time controls.
Exposed the respective settings as ODM PMU properties.
Bug 690326.
Change-Id: I2c30365de3fce4e2d45b1e66c7af9087f10d8451
Reviewed-on: http://git-master/r/2377
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Expanded CPU power off (LP2 state) policies as follows:
(a) "Enter in Low Corner" - LP2 is entered and DVFS tick interrupt is
masked only when DVFS is in low corner.
(b) "Mask in Low Corner" - LP2 is entered independently of DVFS, but DVFS
tick interrupt is masked only when low corner is hit
(c) "Ignore Low Corner" - LP2 is entered and DVFS tick interrupt is masked
independently of DVFS low corner.
Ported from android-tegra-2.6.29, but set default policy to (c), which is
the same as current android-tegra-2.6.32 kernel behavior (on 2.6.29 kernel
(a) was default).
Added sysfs node to change and evaluate policies.
Change-Id: I22e89f4d58dfa2e2fb668154c1ae2cd301fbe1ca
Reviewed-on: http://git-master/r/2359
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Bug 663469
nvrm is split into two nodes, /dev/knvrm and /dev/nvrm.
/dev/nvrm has access to limited set of API's.
Added validation of params in the API's that can be
accessed from /dev/nvrm.
Change-Id: I57c2aae000bf873fe85db00df66ec004c2882b5c
Reviewed-on: http://git-master/r/2300
Reviewed-by: Gary King <gking@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
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DSI one shot support requires register access in the tegra framebuffer to
poke the frame trigger bit (with both the trigger bit and the tearing effect
signal are high, a frame of pixels will be sent to the panel). The boot args
must also be expanded to have a "use tearing effect" flag.
tegra RM: Expanded Display clock configuration options.
Added an option for restricted Display clock synchronization with MIPI
PLL - select MIPI PLL as a pixel clock source, but preserve PLL settings.
To specify this option flag NvRmClockConfig_InternalClockForPads should
be set by RM client along with NvRmClockConfig_MipiSync flag (in the
absence of the former flag, MIPI PLL can be re-configured at RM discretion
- current behavior).
Change-Id: I495c2d76656efe8653aa5731c07180c2bfcd2fc0
Reviewed-on: http://git-master/r/2342
Tested-by: Arthur Spence <aspence@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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MC error interrupts are useful debug features, so implement them
separately from the RM; also, enhance the printouts to include the
client name, so that cross-checking the status value against a separate
list isn't necessary
Change-Id: I9aa2857388bf252bbcd2f3048eae0fb63d90a011
Reviewed-on: http://git-master/r/2280
Tested-by: Gary King <gking@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Change-Id: I6ee6d3a6ce9defa25a30343932db309d05feb557
Reviewed-on: http://git-master/r/2289
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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In the multplexed pinmux option, it is require to unconfigure the
current configured pinmux and need to move the pingroup to safe option.
The function NvRmPinMuxConfigSelect() was not handling properly the
request for selecting the multiplexed pinmux option.
Change-Id: I2869fedfaa9c47cd9af18581dc1555966138f145
Reviewed-on: http://git-master/r/2242
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Added explicit RM state update in RM kernel resume path (no need to
rely on "the 1st resumed driver must report its state to RM")
ported from android-tegra-2.6.29
Change-Id: Idb86728fcb5c73e2874f3077a9d665f0b241c8e6
Reviewed-on: http://git-master/r/2232
Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Replaced dynamic busy hints allocation with busy hints pool.
bug 686569
ported from android-tegra-2.6.29
Change-Id: Ie64dfc1a060e2d574b5970018c95f61acb735e07
Reviewed-on: http://git-master/r/2225
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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the allocated RM DMA handle was not being returned to the caller,
causing a segfault in a number of circumstances, and incorrect
behavior in others; fix this and enhance the error detection in
NvRmStartDmaTransfer to catch this in the future
additionally, it appears that no-timeout and no-signal was a valid
mode of operation in the previous code, so add support for this to
the new code
Change-Id: I954fdbf7307fbae8946292215ebec79750ffbda7
Reviewed-on: http://git-master/r/2018
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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the DMA API expects that the peripheral address supplied by the client
is a valid APB address in the system memory map (0x7000:xxxx); however,
the I2C code was only providing the offset of the register relative
to the start of the controller's aperture.
it's not clear how this ever worked, but the additional error checking
in the new RM DMA-on-native DMA implementation choked on this, highlighting
the problem
Change-Id: I4e10be05e03a6feeff4b0a26b5f870caf9ee5e1c
Reviewed-on: http://git-master/r/2017
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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the gpiolib function gpio_direction_output expects to have the value
asserted on the pins provided as a parameter, but the RM GPIO code
was always providing 0; this was causing numerous bootup problems for
user-space GPIO access
on AP20, VI GPIOs can be accessed through the standard GPIO controllers,
so this cleaned-up implementation just reassigns legacy VI GPIOs to the
correct port/pin on the proper GPIO controllers, to eliminate the need
for two codepaths.
additionally, since no one is using the ODM External GPIOs, this change
removes support for them.
and, since the only chip-specific codepath in this tree is just the VI-to-
GPIO mapping, move it into the common directory.
Change-Id: I182d161a05548d299a4a48714b37c2cd57a1e77c
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Change-Id: I8bb150efaac60cae7ff1a879a9cd7e2051392e18
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Change-Id: I7aa12d51d526eff977c7569ee3059ee627b25824
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Change-Id: If71d82ad705beca7699a05ff4add5584d14abdbe
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Change-Id: I901f5a4af15ae8170d3592c42e710535b1cda915
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add power rail support to GPIO driver
Change-Id: I45d4c1110a635047d68fb14f3e72a28f99acbe1b
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