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path: root/arch/arm/mach-tegra/pm-t3.c
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2014-04-23platform: tegra: move LP0 entry function to driverPrashant Gaikwad
Change-Id: Ife6926d0c00d7e046b2579795f50ef96d633fc8f Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/395845 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2014-01-21ARM: tegra: fix pm-t3 for G-only systemPeng Du
Change-Id: I07434d42788aef4c4ae6a5702f0c19a1c02de95b Signed-off-by: Peng Du <pdu@nvidia.com>
2014-01-21ARM: tegra: port inline assemblies for ARM64Peng Du
Port the inline assemblies w.r.t ARMv8 ISA and #ifdef the code with CONFIG_ARM64. Change-Id: I430b441cc23c88ef947ddb7c5aa1836d06dbabf9 Signed-off-by: Peng Du <pdu@nvidia.com> Reviewed-on: http://git-master/r/196609 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2013-12-31arm: tegra: pm: switch print statementsPrashant Gaikwad
Move the print for suspend state after changing CPU mode so that it appears after cluster switch print in case of LP0. It was confusing for some users if CPU was switching cluster after entering LP0. Change-Id: I2b02fa8b70bd110b4386c235c5521730b6cc7536 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/350961 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-11-21ARM: tegra: add cluster to tracesAntti P Miettinen
Log start and target cluster in cluster switch event traces. Change-Id: I5b83139809cb8e4928033ade87c14321e7ce2aad Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/332498 Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2013-10-24ARM: tegra: increase DPD status read delayBibek Basu
Delay before read of a DPD_STATUS register after writing a DPD_REQ register should be pclk * (Max DPD_TIM + 5) Bug 1389663 Change-Id: I7e13f7587bb30005c5992b2a6ea6800a115b0840 Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/302756 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Kiran Adduri <kadduri@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-10-17ARM: tegra: Move mach-tegra/{cpuidle.h,timer.h}Ajay Nandakumar
Moving mach-tegra/clock.h and mach-tegra/timer.h to include/linux/tegra-cpuidle.h and include/linux/tegra-timer.h so that it helps faclitate the movement of drivers from mach-tegra/ to drivers/. Bug 1379817 Change-Id: Ia0a33c3f726d2f672409c270ac8ca1629f05eff8 Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/299019 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-26ARM: tegra: power: Don't allow CRAIL and CxNC togetherAlex Frid
Rail gating and non-cpu partition power gating must not be enabled together during cluster switch. This commit enforced this restriction: if both flags are set, WARN() is generated, and only CRAIL request is processed. Change-Id: I0755eece55ca6d3ad976fd21423e547baba519c7 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/274866 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com>
2013-09-26ARM: tegra: fix warning during LP0Deepak Nibade
- with CONFIG_DEBUG_ATOMIC_SLEEP enabled, below warning was seen BUG: sleeping function called from invalid context at /kernel/kernel/mutex.c:85 - function 'tegra_get_clock_by_name()' was being called from atomic context in 'tegra_lp0_cpu_mode()' - move function tegra_get_clock_by_name("cclk_lp") to separate init function and call it through subsys_initcall() to avoid this warning during LP0 Bug 1355279 Bug 1318641 Change-Id: I42df042051938d75366884946e7f660522f3c26c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/273034 (cherry picked from commit 9c126a72c41aa66fb9bf394426e331d379aa5c40) Reviewed-on: http://git-master/r/275055 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2013-09-16ARM: tegra: power: Disable CPU sensors for cluster switchAlex Frid
Disabled soctherm CPU sensors before switch to LP cluster, if CRAIL is controlled by s/w. Re-enabled sensors respectively after switch back to G cluster. This is done to avoid bogus temperature reading during cluster switch when s/w is turning CPU rail on/off. Bug 1351735 Change-Id: Ia4864cdbfa622ca42533fe717a358a89dd262bc0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/272916 Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-16ARM: PMC: tegra12: enable IO DPD function for T124Terry Wang
Enable PMC IO DPD function for T124. Bug 1352773 Change-Id: I18387f8054957745bf3f7de70e9e5fa4ce581cb7 Signed-off-by: Terry Wang <terwang@nvidia.com> Reviewed-on: http://git-master/r/267755 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Hunk Lin <hulin@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-09-14ARM: tegra: Move platform detect from <mach/hardware.h> to <linux/tegra-soc.h>Dan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I13f3ff891510d2c868f609d507149b32183d34c5
2013-09-14ARM: tegra: Move mach/powergate.h to linux/tegra-powergate.hDan Willemsen
This moved upstream, do the equivalent change here. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I2de76e5c6487ed4513b6d070e0c515a27a881fff
2013-09-14ARM: Tegra: Move cluster switch tracepointsAntti P Miettinen
Move tracepoints for measuring cluster switch latency to account for the whole interrupts-disabled time. Change-Id: Ib49cc54078d2e284c34b55dd6e2dc57431706b78 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/264800 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2013-09-14ARM: tegra: power: Support CPU rail early startupAlex Frid
Added an option for cluster switch procedure to turn CPU rail ON via direct access to PMC registers before disabling interrupts, and then continue scheduler execution while the rail is ramping up. RAM repair is executed in s/w as well after rail ramp is done. Only non-CPU partition is power-gated/un-gated by flow controller in the atomic section. However, rail ramp in this case is serialized with CPU save context. Hence the trade-off: early startup option reduces interrupt disabled time during cluster switch, but increases overall cluster switch time. Bug 1351735 Change-Id: I5ff9afb2aa6b27b9aa4b2318ee2740dee4908e2f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/262864 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra: power: Add cluster switch time statsAlex Frid
Expanded cluster switch instrumentation with simple timing statistic: running window average, exponential average, maximum switch time - aggregated separately for LP/G and G/LP cluster switch. Added the respective debugfs node. Moved cluster switch start/end timing samples to exactly match interrupt-disabled section of the switch. Replaced cluster instrumentation error message with debug print. The INSTRUMENT_CLUSTER_SWITCH compile option is still disabled, so by default all changes in this commit are not compiled in. Change-Id: If7b9c7b1469f6839e20b7c8db3aa9cf2c0592f2d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/262859 Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra: power: Keep interrupts ON for LP CPU delayAlex Frid
- Moved LP CPU minimum residency delay out of the interrupt-disabled section of the cluster switch to reduce interrupt disabled time. - Time stamped start of LP CPU residency, and rail statistic after the cluster switch is completed, still within interrupt disabled section to make sure LP residency restriction is applied on top of cluster transition latency. Change-Id: I55f769af197bbd757966bafe37a10a6e43b7bf2e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/261328 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra: Move clock/power to pre-siJeff Smith
This change is a part of the effort to enable runtime platform detection and reduce compile-time conditionals. Bug 1333554 Change-Id: I93c215fff80e35767593918ffe88e7bb3e6e9f9a Signed-off-by: Jeff Smith <jsmith@nvidia.com> Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com> Reviewed-on: http://git-master/r/252553 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2013-09-14ARM: tegra: bonaire_sim: dpd initJin Qian
disable tegra io dpd on t12x Change-Id: I2e61d24ce94b3bb2a4380e4b3d0741514913096b Signed-off-by: Jin Qian <jqian@nvidia.com> Reviewed-on: http://git-master/r/129808 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Robert Bond <rbond@nvidia.com> Reviewed-by: Mark Stadler <mastadler@nvidia.com>
2013-09-14ARM: tegra: cluster: Remove obsolete tracingDan Willemsen
The old cpu power tracing API was removed by this commit: 43720bd6014327ac454434496cb953edcdb9f8d6 Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: Move ARM gic.h to include/linux/irqchip/arm-gic.hDan Willemsen
See upstream commit 520f7bd73354f003a9a59937b28e4903d985c420 Change-Id: I50337275d7336e05a2ec0b4978bcd3abd778813c Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra: power: remove all sd dpd entriesrrajk
Bug 1191332 Change-Id: I270e808b8d561afee304550c9cd3564af924085b Signed-off-by: rrajk <rrajk@nvidia.com> Reviewed-on: http://git-master/r/227046 Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2013-09-14fixup pm-t3.c gpio.h removalDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra14: Changes for SMP and cluster switchSeshendra Gadagottu
1. Enabled following kernel configuration for SMP on fast cluster and cluster switching functionality: TEGRA_LP2_ARM_TWD if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP GIC_SET_MULTIPLE_CPUS if SMP ARCH_TEGRA_HAS_ARM_SCU ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE ARM_CPU_SUSPEND if PM 2. For T14x, disable RAM repair bypass and power-up CPU rail during Cluster 1(LP) to Cluster0( fast cluster) switch. 2. For T14x, for IMMEDIATE_WAKE use WAITEVENT as wakeup condition. Change-Id: I8f3e067207eac3b3776dfbd265527fc7a0fae266 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/118464 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra11x: Enable RAM repair per fuse settingBo Yan
fuse bits spare_10 and spare_11 decide whether or not to do RAM repair bug 1027322 bug 1056548 Change-Id: Id12f5fde052332759b03d191fbea99dc01aab894 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/169134 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2013-09-14ARM: tegra11: power: Update core EDP on CPU cluster switchAlex Frid
Update core EDP limits when CPU cluster is switched between fast (G-mode) CPU, and slow (LP-mode) CPU. Bug 1165638 Change-Id: I956eb5ab2d8fbe873f998cca1e22984413cf5743 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/165617 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14arm: tegra: API for cluster switchingNitin Agrawal
API for doing cluster switching so that we can do cluster switching within the kernel from another process explictly. Bug 1058804 Reviewed-on: http://git-master/r/141961 (cherry picked from commit 96e05643a4b1ea2c566ab5cf07642645f4f935bb) Signed-off-by: Nitin Agrawal <nitina@nvidia.com> Change-Id: Ic4821fbd507327d7c951ab74ae7b1febc6f5bbe6 Reviewed-on: http://git-master/r/161869 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bob Johnston <bjohnston@nvidia.com> Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Nagaraj Kolur <nkolur@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra: pm: moving to clk prepapre APIsSivaram Nair
The clk_enable/clk_disable pair of APIs are replaced with tegra_clk_prepare_enable and tegra_clk_disable_unprepare. This is needed for the migration to common clk framework. Bug 920915 Change-Id: Ie5e86f391ef5157d35e02109770db38ad96950af Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/162321 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: tegra11x: cpuidle: Remove LP2 referencesBo Yan
This change completely removes references to lp2 in cpuidle-t11x.c, some related changes also affect cpuidle-t2.c, cpuidle-t3.c, and a few other files. bug 1034196 Change-Id: Ic2387bf614b39bd08ed4b2fc6e996f6fbf8306c0 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/160017 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2013-09-14ARM: tegra11x: CPUID virtualization supportBo Yan
This is the first patch to support CPUID virtualization. The goal is to treat all CPUs as equal in software. In current implementation, CPU0 is the anchor CPU, which must be the first one brought up, and the last one taken down. This patch removes that restriction. the cluster switch still has to start from CPU0 with this patch. This can not coexist with secure OS Reviewed-on: http://git-master/r/144610 (cherry picked from commit d32fba4be39e3f9a95ef5ab44d0c64dc6d2808a3) Change-Id: Ib7fcaae751d17fee839a4f228f5ef5c3ee2390c2 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/159486 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R09e29d45acf92b3ad2d909d5438c3375aa85e7dd
2013-09-14ARM: tegra: pm: Enable DPD for sdmmc3,4Pavan Kunapuli
Enabling DPD support for sdmmc3 and sdmmc4. Bug 1051532 Reviewed-on: http://git-master/r/144546 (cherry picked from commit 7c7f6bfd5bcf068b626557c50776f1cd2d47ac79) Change-Id: Id44bc1b009e5136ec15b91b30825500ed9ba90e6 Signed-off-by: rrajk <rrajk@nvidia.com> Reviewed-on: http://git-master/r/146410 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R750c6bfb1417737e96cc4bce291ac1686162204b
2013-09-14ARM: tegra: pm: Fix DPD code offset for T11xPavan Kunapuli
The DPD code offset for enabling/disabling DPD modes is different for T30 and T11x. Fixed the same. Bug 1051532 Reviewed-on: http://git-master/r/144536 (cherry picked from commit 83ca9c5ee3515f825150211b21411e9cd7eb38a9) Change-Id: Icdf2ba622a8baa2facb0ba91e0ce068c1104401d Signed-off-by: rrajk <rrajk@nvidia.com> Reviewed-on: http://git-master/r/146409 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R783d90e0f2a9dc0639ba0d473f27521bc9e8465e
2013-09-14ARM: tegra11x: CPU start up fixBo Yan
The first time when a CPU powers up in kernel, it has to be done by directly toggling PMC register. Subsequent CPU power up sequence is controlled by flow controller. This is done after LP0 exit as well. Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/143296 Change-Id: If32712706d827e4d0337d75163449cfa0a3a50f8 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/146484 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> GVS: Gerrit_Virtual_Submit Rebase-Id: R8909dae486432fd628e8d89735634eee26063f4e
2013-09-14ARM: tegra11: clock: Add DFLL resume operationAlex Frid
- Implemented DFLL resume including CL-DVFS state restoration. - Moved G-CPU clock resume after DFLL. - Made sure that LP-CPU clock is enabled before cluster switch on entry to LP0 (it can be disabled on tegra11 if G-CPU is on DFLL). Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/140004 (cherry picked from commit 09f59e09eab56e855ab36c43244f0e04a3246216) Change-Id: I90cf3f5c8c54bb99303851b30b42da49b47e208f Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/146265 Reviewed-by: Automatic_Commit_Validation_User Rebase-Id: R88edf44729cda253776deda3b965a89de038a55e
2013-09-14ARM: tegra: add config option for io_dpdVishal Singh
Adding a temporary config option for allowing devices listed in tegra_list_io_dpd[] to go into DPD state. Since the pins under sdhci DPD groups are used for different purposes on different platforms, this list should be either in platform files or should be guarded by a config option. This change does the latter for now, until a decision is made on this. Bug 1036567. Bug 1040511. Change-Id: Ic2de96d9e506463f140d7a4e998c7a657c9593bc Signed-off-by: Vishal Singh <vissingh@nvidia.com> Reviewed-on: http://git-master/r/141251 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com> Rebase-Id: R07835d6a216fba7c61b4431818ef72b913694889
2013-09-14ARM: tegra11x: Fix power gating modeBo Yan
When switching cluster from slow to fast, and if CRAIL is specified by user in sysfs, force NONCPU instead, since there is no CRAIL for slow cluster. Reviewed-on: http://git-master/r/134148 (cherry picked from commit dd4a35406f8f78a11f24b0a741de9a1d7f86fded) Change-Id: I27eb056a76e8ef5e2480ba4101252415e44eb6c3 Signed-off-by: Bo Yan <byan@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/143141 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: R32f361794ddc0d29a690c5085adc40f882c16448
2013-09-14ARM: tegra11x: disable RAM repairBo Yan
It's obvious that RAM repair is causing problems when switching cluster. Disable it for now. Reviewed-on: http://git-master/r/134214 (cherry picked from commit 4e72925ef08797e130618db7964e3f87346fa35c) Change-Id: I07bf0a744d1d9bfa6758f8f10f104d03a68314c6 Signed-off-by: Bo Yan <byan@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/143139 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: R5693e38b48fd07f24688423ea72b8ef0f5fae210
2013-09-14ARM: Tegra: Enable SDMMC DPD support only for T30Pavan Kunapuli
IO DPD mode is not working on T11x platforms and is resulting in a spew of error messages. Enable the DPD support only for T30 platforms. Reviewed-on: http://git-master/r/133269 (cherry picked from commit 46044a4ca51ae4a93cd24beec980db02b7a1e839) Change-Id: I274a04ed2cf2198dba8e788cf9a792110d3c774b Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/143078 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Rc14193ff5e212b9b724e20b8a94e4c9d3cf8b012
2013-09-14arm: tegra: fix coverity issueSri Krishna chowdary
Array compared to NULL has no effect. Fixed it. Bug 1046331 Change-Id: I2f89bc7851558795084ba03c84fbcdc4330f489d Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/134781 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R2e7cbe86b22a3a7659a886aebda9d1f02073feb4
2013-09-14HACK: Disable dpd spew messages on FPGAnaveenk
Bug 1031496 Bug 1013917 Change-Id: I489e88dd3c3a2ddffc398dbfbdd2b415ce96233a Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com> Reviewed-on: http://git-master/r/124291 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Rebase-Id: R8e148e1a28e49702516627480b533c049331d82f
2013-09-14ARM: tegra: reset io dpd modeBitan Biswas
Bootloader io dpd settings are cleared during kernel initialization bug 758856 Change-Id: Ic6d5250a5ae127bb45ab37b9200ca06c8d1f11a2 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/115395 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R2a63cb307f02dc2870e73c6a9fcc73e8c76dca32
2013-09-14arm: tegra: PLLX LP/G ports switching ON/OFFPrem Sasidharan
Enable target PLLX port(LP/G) before cluster switch and disable the previous PLLX port(LP/G) after cluster switch is finished. Seeing a power improvement of ~10mW when core operates at max. voltage and max. frequency. Bug 997358 Signed-off-by: Prem Sasidharan <psasidharan@nvidia.com> Change-Id: I9d05245977f9f63a8f4c53b1c6797118d2d8b903 Reviewed-on: http://git-master/r/113399 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R78b0623f2478f2b4844d5912d5dbf74b7ae7537e
2013-09-14arm: tegra: sd: enable sd dpdWen Yi
This is a WAR solution that allows for the turning on SD DPD feature. The original issue is that enabling SD DPD immediately after device comes out of LP0 causes ULPI disconnect. The root cause of that is not known. The WAR is to delay the enabling of SD DPD for 100ms after device comes out of LP0. Bug 929628 Change-Id: I3c5e35ace422e5441535c2c0fe18545b53bbddc4 Signed-off-by: Wen Yi <wyi@nvidia.com> (cherry picked from commit bffb7b917d52a3523af80db21322ec7ba5fd33f9) Reviewed-on: http://git-master/r/113392 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Rd4728fda7b23fa349f48b19c054ed412bf10e089
2013-09-14Revert "arm: tegra: power: disable all sd dpd"Bitan Biswas
This reverts commit 8924926cdb77c6ab270867d4caef7a8cdacd11f2. Bug 924452 Bug 929628 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> (cherry picked from commit 142b34993404c853579864f7b7b4f320fb92a715) Change-Id: I9d49703799e32d410beba18938e94e4b641eea6f (cherry picked from commit 8de60b7a832bfbbf09e75def756379dbb2d14c3e) Reviewed-on: http://git-master/r/113387 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Wen Yi <wyi@nvidia.com> Tested-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R5ad33e04ba72e5408bf553685b1a6efead1e2bf0
2013-09-14ARM: tegra: Fix compilation warningsBo Yan
Remove unused variables in timer.c and pm-t3.c Change-Id: I1116678431775f2d33d345e93de1c47c3ed67a16 Signed-off-by: Bo Yan <byan@nvidia.com> Rebase-Id: R69c3a3e3a3cafa9dc4c88f7219150c0cb33d23eb
2013-09-14ARM: tegra11: Do not restore FW bit in ACTLRBo Yan
For Cortex-A15, the bit 0 of ACTLR controls the behavior of "Invalidate Instruction Cache All" and "by MVA", not TLB maintenance broadcast. So we do not need to set it. We invalidate branch predictor in a separate step when invalidating CPU state. Change-Id: I9f71566f2e3aa5061b53a8d6d4ced281122534c8 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/111971 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Rebase-Id: R386b94063119cf1618c6e01f88e25aea1091360a
2013-09-14ARM: tegra: Clean up flow controller CSR macrosBo Yan
Group flow controller macros for CSR register in one place in sleep.h Also strip "CPU" out of macro names because the corresponding COP CSR register has only one field INTR_FLAG which is at bit 15, same as CPU CSR, so there is no confusion here. Change-Id: Ib3dea0bd3e9051d1e7b9048abc4afde5ddc8bab5 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/103478 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Rebase-Id: R63c198f17e573818b8d44482c46cb61516bf1267
2013-09-14ARM: tegra11: CPU rail power up sequenceBo Yan
It is necessary to disable RAM repair bypass when CPU rail is powered up. This needs to be done even in case of HW controlled CPU rail power-on. This change also enables cluster switch to use "power_gate" flag defined in sysfs to control the power gating mode. For LP0 entry case, rail-gating is set to default. Set default power gating mode for cluster switch to rail gating. For chips that doesn't support symmetric power gating, "0" is the default value which will trigger rail-gating. Change-Id: Ia7ccb023118bbfba4fa53dc263bdfda59e29f089 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/101045 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R50b64bfc236a664028edc822219af0d30d1af043
2013-09-14unknown changes from android-tegra-nv-3.4Dan Willemsen
Rebase-Id: R940fad74c7e91ef3d1d3d589a48064ccb7335541
2013-09-14ARM: tegra: power: Use CPU G mode in suspend prepareAlex Frid
Switch to CPU G mode in Tegra3 suspend prepare if CPU suspend rate is high enough. By symmetry, it guarantees that device resume will be happening in G mode as well. Bug 946301 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 082be3604056c39442e1b42f5cfceeb089ffdaae) Change-Id: I42e37ce8847e4916dd0fca9e4bd44096b65f7032 Reviewed-on: http://git-master/r/89352 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R927e8f6c3ea5394b94533dbafc6a4e4d63399671
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-27 06:22:32 +0000