summaryrefslogtreecommitdiff
path: root/arch/arm/mach-tegra/pm.h
AgeCommit message (Collapse)Author
2012-11-27tegra: fix file names and paths in commentsMarcel Ziswiler
Several file names and paths showed copy/paste or otherwise issues.
2012-09-17arm: tegra: raise cpu floor when display is onWen Yi
When device is idle and display is on, the minimal cpu frequency can drop to 51mhz. Since it takes several tens of millisecond to ramp up cpu freq, the delay impact negatively the performance of low latency CPU bound tasks. Given the power savings of several milliwatts running cpu at 51mhz comparing to 102mhz or 204 mhz at idle, the idle cpu freq is hence raised to 102mhz for smart panel device and 204mhz for dump panel devices. Bug 1036216 Change-Id: Ifb0ed88d4c5fcf5b637d09c587322cec72b8a08d Signed-off-by: Wen Yi <wyi@nvidia.com> (cherry picked from commit c8465feffcd0cf2401bbd6c6f535955dd68bda55) Reviewed-on: http://git-master/r/132479 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ujjaval Patel <upatel@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-08-29arm: tegra: Set Core to 0.95V in LP1Karthik Ramakrishnan
When the device prepares for LP1, the Core voltage is set to the highest value(1.2V for Enterprise and Kai, and 1.3V for AP37 and Cardhu). This is to set for some of the driver suspend along the sequence need a higher emc frequency and thus a higher Core voltage. Since the sequence of drivers suspend depends on the sequence of their registration in the table, which in turn is platform-dependent, there is no right place in the LP1 entry path where the Core voltage can be set to a lower voltage. Hence, the Core voltage remains high in LP1 resulting in higher power. Thus, the only safe location where the Core voltage can be lowered is once all the drivers are suspended and the DRAM is set in self-refresh, at the final point just before the system is suspended in the IRAM code. This location at the assembly code ensures that no other module will be running and thus that nothing will require a higher core voltage. The Core is set to the lowest possible value since nothing requires it. It is then restored to the highest voltage as soon as the LP1 resume code is started so that all drivers are resumed safely. At the execution point in IRAM during LP1 suspend path, even the I2C clocks are gated. They must be reset first and then the I2C transaction is performed. An I2C transaction involves 4 bytes of data, to send the slave address, the Core voltage register address and 2 bytes of data which has the value to set the voltage(the second byte is not required for this transaction). Once these registers are set, the I2C transaction is performed by setting the I2C transaction register to 0xA02. After sending the I2C transaction, we wait for about 250us to check the status of the transaction and if not updated, wait for more time to check again. If after 2ms and the transaction fails to register, the transaction is aborted and the device is allowed to enter at high voltage. Since the failure rate of I2C transaction is very low at this point in execution where there will be no conflicts in the bus, it is okay to have Core high for some of the LP1 cycles. However, it is unacceptable for the I2C transaction to fail on the way from LP1 resume since the device cannot come up with a lower Core voltage. In this case, the transaction is retried again and again till it is successful. There is no way but to keep trying as the device would fail to resume with Core at 0.95V. Each platform(or each PMU) has different values for the I2C transaction ie. slave address, Core voltage register and the value to set the voltage. For the device in IRAM, it cannot access anything in SDRAM memory, these values needs to be pushed to IRAM memory before the device starts execution in IRAM. This is done during initialization of suspend code when it picks values from the board files and copies it to IRAM part of code, before the whole memory is copied to IRAM. This new feature is controlled by a KConfig variable TEGRA_LP1_950 which should be enabled once the board file of the device is updated with the right values. The device hangs when it does not have the right values for the I2C transaction. With this change in Core, LP1 power is reduced by 12mW in Enterprise, 20mW in AP37 and about 24mW in Kai. Bug 1035684 Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> (cherry picked from commit ab476f287376fd0ae51a9f298659f5eba19f0296) Reviewed-on: http://git-master/r/124779 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-06arm: tegra: optimize L2 enable/disable paths for secureosHyung Taek Ryoo
For the CONFIG_TRUSTED_FOUNDATION code paths, differentiate L2 enable vs. reenable, which are different SMCs (won't trigger an invalidate in the case of a reenable). On an L2 disable SMC, optionally pass a 0 for the L2 ways arg, which skips the full clean/invalidate (and simply just disabled the L2). In order to safely skip flushing the L2 on the disable, we have to be careful what we dirty from the type we flush the L1 and disable the L2. Bug 939415 Signed-off-by: Chris Johnson<cwj@nvidia.com> Change-Id: I756d2ceda83d5d8d6bc5670218e9d874d5e5f62a Reviewed-on: http://git-master/r/119786 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-20ARM: tegra: reset io dpd modeBitan Biswas
Bootloader io dpd settings are cleared during kernel initialization bug 758856 Change-Id: Ic6d5250a5ae127bb45ab37b9200ca06c8d1f11a2 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/115395 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-16arm: tegra: sd: enable sd dpdWen Yi
This is a WAR solution that allows for the turning on SD DPD feature. The original issue is that enabling SD DPD immediately after device comes out of LP0 causes ULPI disconnect. The root cause of that is not known. The WAR is to delay the enabling of SD DPD for 100ms after device comes out of LP0. Bug 929628 Change-Id: I3c5e35ace422e5441535c2c0fe18545b53bbddc4 Signed-off-by: Wen Yi <wyi@nvidia.com> (cherry picked from commit bffb7b917d52a3523af80db21322ec7ba5fd33f9) Reviewed-on: http://git-master/r/113392 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-14ARM: tegra: power: Boost CPU rate before device resumeAlex Frid
Boost CPU frequency in tegra platform resume finish phase, just before driver resume. Boost level is specified by platform suspend data (ignored if 0). Bug 946301 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit eaedf228861e4456454ca13f0958ed97e799fc59) Change-Id: Ica0cff28f9651e38787ec98f54563d95d876d79e Reviewed-on: http://git-master/r/89353 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-03-01ARM: tegra: Add support for passing arguments to bootloader.Gaurav Sarode
PMC SCRATCH register 0 holds value across warmboot. Storing values in bit31:30 for recovery and fastboot. This requires change in bootloader as well to parse these arguments. Bug 863014 Change-Id: I1d4b752dbc6dd7b065e9d0cc87df189e7caeb201 Signed-off-by: Gaurav Sarode <gsarode@nvidia.com> Reviewed-on: http://git-master/r/86140 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-23ARM: tegra: power: Power off multiple CPUs on-lineAlex Frid
Currently on Tegra3 cpu complex is powered off in idle (enters CPU0 LP2 state) only if all secondary CPUs are off-line. This commit adds an option for CPU0 to enter LP2 while secondary CPUs are still on-line but have been power gated and entered LP2 state by themselves. The critical race: secondary CPU is waking up from LP2, while CPU0 is turning common CPU rail off, is addressed as follows. 1. When entering LP2 state on CPU0: a) disable GIC distributor b) check that CPU1-3 are all power-gated (i.e., either off-lined or have entered LP2) c) if (b) passes - set all interrupts affinity to CPU0, then re-enable distributor and continue with CPU complex powering off d) if (b) fails - re-enable distributor and enter clock-gated (LP3) state on CPU0 This procedure prevents waking secondary CPUs by GIC SPIs. 2. We still need to make sure that no CPU1-3 PPIs from legacy IRQ/FIQ or private timers would happen. This is achieved by disabling timers and legacy interrupts if CPU1-3 enters LP2 state with external timers selected as wake sources. Respectively, establish dependency between turning rail off and LP2 wake timers configuration options. 3. Finally, no IPIs is sent by CPU0 entering LP2. There are no special changes in wake up procedures - whenever CPU0 is awaken by external interrupt or wake timer, cpu complex is powered on by h/w, and secondary CPUs that were in LP2 state are ungated by the same interrupt (off-line CPUs are kept power gated). Hence, there is no need for CPU1-3 external wake timers to run while the rail is off, and these timers are stopped. To make sure that none of secondary CPUs over-sleeps its LP2 time, CPU0 wake timer is set to minimum sleep interval of all CPUs. By default configuration option for powering off multiple on-line CPUs is disabled on Tegra3. Change-Id: I4920d0df375536b2b8ebd9e6738c5fe4f92b92a0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/83547 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-02-17ARM: tegra: power: Add external LP2 wake timers on secondary CPUsAlex Frid
Add an option to use external timer as Tegra3 secondary CPU wake source from lp2 (power gated) state. This is a follow up to commit 51e6be9ce103fbeb2b73fa2a9d2b6528a6941e81 that disabled wake from external timer, since its interrupt is registered too late - after secondary CPU is brought on-line, and already had a chance to enter lp2. With this commit, secondary CPU is not allowed to enter lp2 in idle until wake timer is registered (clock-gated lp3 state is entered instead). External timer wake up mechanism is enabled on Tegra3 only if option HAVE_ARM_TWD is not selected. Otherwise, continue to use local CPU timers as lp2 wake sources. Change-Id: Ic8c33f55e77174717bfa6525041e1263d3232dd5 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/83546 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-01-04arm: tegra: power: io dpd APIs definedBitan Biswas
Defined IO deep power down(DPD) APIs for tegra drivers - tegra_io_dpd_get - returns dpd handle tegra_io_dpd_enable - enable driver dpd tegra_io_dpd_disable - disables driver dpd bug 919993 Change-Id: I45976b41dca0e3e9266ace86393ef4db8b20c97b Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/72737 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-12-23ARM: tegra: disable cluster switch messagesDiwakar Tundlam
Bug 915962 Change-Id: Icece8c31a7e31b3871dd836aa79b5f7cc28d0af1 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/70121 Reviewed-by: Automatic_Commit_Validation_User
2011-12-08arm: tegra: add Trusted Foundations hooks and driverChris Johnson
Add CONFIG_TRUSTED_FOUNDATIONS build option and calls to issue SMCs to the TL secure monitor (used when needing to update state not writable by non-secure code). Make security/tf_driver an optional part of the build, which is part of the TL framework to interact with secure services. Bug 883391 Change-Id: I9c6c14ff457fb3a0c612d558fe731a17c2480750 Signed-off-by: Chris Johnson <cwj@nvidia.com> Reviewed-on: http://git-master/r/65616 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-30ARM: tegra: power: add combined power req processingJoshua Cha
For platforms where the core & CPU power requests are combined as a single request to the PMU, we need separate processing to enable its suspend/resume operation. Bug 862504 Change-Id: If66282a7b069d35568147e2d64f14371e1692bfd Reviewed-on: http://git-master/r/64011 Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R21b966a438be03b11b80ce7deb70e3036b80dab2
2011-11-30ARM: tegra: power: implement LP1 suspend/resume for Tegra3Yudong Tan
Bug 862502 Change-Id: If70e54fb32ce14d5f13dde1d7fb4c1f1499a6722 Reviewed-on: http://git-master/r/47398 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Ra77a54e6930692bca628a97bf1de10a30408cdef
2011-11-30ARM: tegra: Use CONFIG_TERGA_CLUSTER_CONTROL for cluster controlScott Williams
Change-Id: I07c389092132e52e2bdd3deab22c10f8e1e6035c Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/48798 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1e0c9acc87c81f9d0dc394c09d6a7b8b94c48d3f
2011-11-30ARM: tegra: power: Re-factor power headers.Alex Frid
Renamed and moved tegra cpu related function prototypes from power.h to tegra-cpu.h. No functional changes. Original-Change-Id: I24c25c9434bf7008e0875d1f74be502cd902c4ba Reviewed-on: http://git-master/r/40532 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R3d90799453a86a5a9ed012d2bfe373715de6d5c3
2011-11-30arm: tegra: Console suspend for all boardsLaxman Dewangan
Added the board level suspend/resume and call the console suspend from board level suspend/resume. bug 820536 Original-Change-Id: I246265241246dc0682870571c927bd23023e5aca Reviewed-on: http://git-master/r/41448 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Rebase-Id: Re1f3dd4f75ee05456899d9a67f74ae84f9572654
2011-11-30arm: tegra: suspend: Add board specific suspend/resume callsLaxman Dewangan
Adding board specific suspend and resume call apis through platform data. Added call of these function at appropriate stage of suspend/resume. Added mechanism to select the uart debug channel base address through variable so that board file can directly change this. bug 820536 bug 832273 Original-Change-Id: Ia9ff3b8a8d2faa1071a8ff634960e6a6c8a43d40 Reviewed-on: http://git-master/r/34494 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6d7bfb3f8f9152779f5138cbcd1b7a9e9a9545df
2011-11-30ARM: tegra: power: Use CPU LP mode for Tegra3 deep sleepAlex Frid
Original-Change-Id: If23b48fb414332f5dd25307a098569a5474283c6 Reviewed-on: http://git-master/r/31471 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6ba9ce7c7b355da4148ce0ebc9bc357bf5fc0b13
2011-11-30ARM: tegra: power: Idle Tegra3 auto-hoplug on suspend entryAlex Frid
Original-Change-Id: I7f4fb6447c882a54d95ee3fb4c6149f4e0357d69 Reviewed-on: http://git-master/r/31457 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Gerrit_Virtual_Submit Rebase-Id: Rbe2ac5f11065109d34a04793f93c873441e261be
2011-11-30ARM: tegra: power: Fix build errors when DVFS is enabledScott Williams
Change-Id: Icc37a1ac4fe1af3d08e579faf35ccb4ab1db1b1c Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R786d091cccb765acb8d89acd59017ae993b78733
2011-11-30ARM: tegra: power: Clean up cluster control definitionsScott Williams
Reduce the complexity of the cluster control compile-time conditionals. Also disable DEBUG_CLUSTER_SWITCH because it invokes clock code that takes a mutex when taking of a mutex is disallowed. Change-Id: I9b614d4b0189fbb01d0b7f8af7053c7586d9515b Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R412820dc2fd9f0c9cc7b1e3ad7ead7e2e68a0ff3
2011-11-30ARM: tegra: power: Consolidate power management flagsScott Williams
Consolidate all of the power management control flags in one header and adjust the values of the software flags so that they do not conflict with the values of the hardware flags. Change-Id: I7971d274946d84dcc50bd9d9e0190091ebbefa2e Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R29d2420a74f977c16f73b1abd9ca7470695a53f4
2011-11-30ARM: tegra3: Add LP2 TimersScott Williams
Change-Id: I121c8aff9c4cb212ac625ef7751d8cf6b8093068 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes, move hotplug notifier to timer-t3.c Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbfbfdb1720960dd9ce2847fb16daa932bebb16d2
2011-11-30ARM: tegra: Add Tegra GIC extensionsScott Williams
Implement extensions to the standard ARM GIC API for Tegra3 power management. Change-Id: If8b2ce2b366e48bb5ca82d3de2acab1fd0a81bb9 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd7527cd57edf054c871f5d04d7e9185643f79843
2011-11-30ARM: tegra: Redesign Tegra CPU reset handlingScott Williams
- Add a single unified handler for all CPU resets that is copied to IRAM. - Add state information to direct the flow of execution through the reset handler based on the reason a CPU was reset. - Write the EVP CPU reset vector only once per cold/warm boot session. - Prevent modification of the EVP CPU reset vector in Tegra3. Bug 786290 Bug 790458 Change-Id: Ica6707f3514986ee914e73a2d9766a4e06ce2d29 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7b9859a83717e76c3c083bdde724bd5fef9ce089
2011-11-30ARM: tegra: Consolidate flow control registersScott Williams
Change-Id: I07ffcffafcf47fd7539b22d4829712e041293bf3 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R34a7800e24254d54b499411652d59421be703619
2011-11-30ARM: tegra3: Cluster Switch and LP0 require PM_SLEEPScott Williams
Change-Id: If3d4fa59cf6d7cd8692f6e5b59414a923abcfd0d Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rec3560499e4c64fd76a873689691cbae59f7602b
2011-11-30ARM: tegra: Catch early LP2 exitsScott Williams
Change-Id: I107d301ec8e8cd3b69ea293faab15b8d766e38f4 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R9f8f016c1850e2c65f30f2f67241a94acf8a7755
2011-11-30ARM: tegra: Idle event wakeup timerScott Williams
Change-Id: If072ef10f02d5be7560fdf42584ab11b2a863481 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf1ace67e281b1581501aaa936cd9137d326f2c4a
2011-11-30ARM: tegra: Update tegra_lp0_suspend_init stubbingScott Williams
Change-Id: I961125e938e72506dc304025b418e80387a5062e Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R393c5a77803f276467d2974041653eb92026601e
2011-11-30ARM: tegra2: Add LP2 TimersScott Williams
Restore the Tegra2 LP2 timers that were dropped in the port to Linux 2.6.39. Change-Id: Ie3958fa3c89886d5dc5a5858c694400bd1421741 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R63ede668965d11ac2b2114ffa817b690a616205a
2011-11-30ARM: tegra2: Move LP2 into cpuidle-t2.cScott Williams
Move Tegra2 SOC-specific CPU idle functionality to cpuidle-t2.c Change-Id: I26c94ca74d7a78665c52e23571c5058e3da240a7 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1246e3942623458f5121ccdac3e6d4a1d40ad624
2011-11-30ARM: tegra: Finish suspend.h -> pm.h renameScott Williams
Change-Id: Iad4b8a7c73ebe4b23a24b5986807358d481aac55 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rb796a9ffc20dd4fbf9c463bc9cf3c175f4b03f88
2011-11-30ARM: tegra: update copyrightsScott Williams
Change-Id: If50d29696867787b38febd909910dda75475cc30 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2275ad736d4dbee0a7b716ee6ea19b1863d8d4f8
2011-11-30get tegra3 compilingDan Willemsen
Rebase-Id: R03f1fc69f4859a0dc66fbd145eb0df31650de3ac
2011-11-30ARM: tegra: Fix flow control macrosDan Willemsen
HALT_CPU and CPU_CSR were backwards. Update with the formulas from android-tegra-2.6.36, making it hopefully a bit clearer too. With this fixed, Ventana LP2 works again. Change-Id: Iebde05904755041ce36d493f8d02507b03dd818a Reviewed-on: http://git-master/r/41257 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R4c6d9911e39bb9477ba43827ea73bdea729040d3
2011-11-30ARM: Tegra: Support to update edp zonesVarun Wadekar
Tegra cpu-freq driver will now recognize edp zones and cap the max cpu freq for that zone. The temperature monitoring driver will be giving inputs to cpu-freq on the current temperature which would be interpreted by the cpu-freq driver appropriately. Original-Change-Id: I918eb31771aa7e1e1a5f25438edded727de6eb8c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/31339 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R6d93bf69d0731ce4ae84f80d1e9013378483331c
2011-11-30ARM: tegra: power: Check Tegra3 auto-hotplug speed balanceAlex Frid
When current CPU complex frequency is above target range: - bring new core on-line only if cpufreq governor requests for all already on-lined CPUs are above 50% of current CPU frequency - off-line one core (despite high pick request) if cpufreq governor requests for at least 2 on-lined CPUs are below 25% of current CPU frequency - do nothing if neither of the above conditions is true Original-Change-Id: I77e1bd543a8fadd51974f7d574f256a6e7e2979a Reviewed-on: http://git-master/r/29702 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rc5c717454d1e09ca97ccc79fff60cb33fcf854e9
2011-11-30ARM: tegra: power: Update Tegra3 CPU auto-hotplugAlex Frid
- taking CPU core off-line: selected CPU with minimum load - switching from ULP to G CPU mode: set CPU clock to cpufreq target rate after the mode switch is completed Original-Change-Id: I9bf4d0f4b48c262cf678c603aac02043dd602674 Reviewed-on: http://git-master/r/28420 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Original-Change-Id: I5a19be79dd8f8fe788637870a22cd34dcfea150e Rebase-Id: Re264ec676c5c2103f7738c9eab5f4e11a4344975
2011-11-30ARM: tegra: power: Set minimum LP2 target residencyAlex Frid
Added board level tuning parameter to specify minimum LP2 residency time (previous policy allows down to zero residency targets limited only by LP2 exit latency). Original-Change-Id: I4ae7d458fba78f35a40f138cf9489bf938715b22 Reviewed-on: http://git-master/r/28162 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Original-Change-Id: I38e798ca6d242d136ea2353d90cc961de14f25b6 Rebase-Id: Rcf9efce3dd037b0a7ca13a9c342f884fac38d654
2011-11-30ARM: tegra: power: Add CPU EDP supportAlex Frid
CPU electrical design point (EDP) limits specify maximum CPU frequency depending on number of CPU cores on-line, and chip temperature. This commit added initial edp governor to cpufreq driver. Governor is aware of CPU departure/arrival, but temperature dependency is yet to be added. Therefore CPU EDP support is left disabled for now. Original-Change-Id: Ia875aa6904df7ec25ac98863d59a173703034241 Reviewed-on: http://git-master/r/26982 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Iae2e9d47c2d3fd4cb32104adbad4f4b26c46064c Rebase-Id: Rde24788e86558e1c21b18a1857a8b52220ba8e2a
2011-11-30ARM: tegra: power: Modify auto-hotplug lockingAlex Frid
Use cpufreq (cpu DFS) mutex for auto-hotplug (instead of a separate one) to serialize cpu frequency scaling, hotplug, and CPU mode switch operations. Original-Change-Id: I7ea865894d1676c865294ab31a903248d9437534 Reviewed-on: http://git-master/r/24893 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I906a23561c1567079a41590a30b29b3d52fa5de8 Rebase-Id: R5d16154c91b41fd02f2a50af7ec6868a7958dc13
2011-11-30ARM: tegra: clock: Re-factor Tegra3 cpu clocksAlex Frid
Added second level virtualization (on top of virtual cpu rate control) to support different Tegra3 CPU power modes: low power (LP) mode and geared performance (G) mode. Virtual cpu complex (cpu_cmplx) clock is defined as a child with two parents: virtual cpu_lp and virtual cpu_g clocks for the respective modes. Mode switch sequence was integrated into cpu_cmplx set parent implementation. (Before this commit mode switch was triggered outside the clock framework, which created cpu clock/mode synchronization problems). Each mode clock is derived from its own super clock mux (cclk_lp and cclk_g) to statically match Tegra3 h/w layout. (Before this commit the code had to dynamically synchronize CPU mode and active mux selection). This change also allowed to support PLLX output divider for low power mode as fixed 1:2 divider with bypass control embedded into cclk_lp parent section. Updated auto and sysfs CPU mode switch calls to use new clock framework, and removed clock manipulation from the low level mode switch implementation. Original-Change-Id: Ibc3cc495b2ff29e2d3417eff2bfd45535cbd015b Reviewed-on: http://git-master/r/24734 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I23ae80edbf14fb22727a6fc317cd9e5baf8bd6be Rebase-Id: Rdcd4a2165ebd92bf4caa35d68ca81d19a3789351
2011-11-30arm: tegra: Enable MC early ACK and scoreboardScott Williams
Bug 791803 Original-Change-Id: I25be461cccd6e14618d8b43fd0738e9abfbe4432 Reviewed-on: http://git-master/r/23584 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I6bb5dcfbf48323919529c6271ea7696ecc413bb2 Rebase-Id: R3308cf0a852ee2bf0e2adb3de17cebc81e48c71c
2011-11-30arm: tegra: Fix initial boot to LP clusterScott Williams
Forbid cluster switch to G cluster if the G cluster doesn't exist. Bug 791057 Original-Change-Id: I215de2581edf5fb3c1feaa00d1c6e0b52b15dc23 Reviewed-on: http://git-master/r/19302 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Id0a7e5ad62df4d1638518fe00715aac60e4efea9 Rebase-Id: Re39a0fedb7bb0e2518cfd56d46c6565d4a6c2ef4
2011-11-30ARM: tegra: Add auto-hotplug support for Tegra3Alex Frid
Initial implementation of Tegra3 quad core CPU management. Add closed control loop on top of cpufreq DFS. Target frequency range is bounded by Fmax(Vnominal) for low power cluster - currently set to 456MHz, and Fmax(Vminimum) for high power cluster - currently set to 356MHz. When CPU frequency is scaled below the target range, slave high power CPUs are gradually brought down and eventually CPU is switched to the low power cluster. When CPU frequency is scaled above the target range, CPU is switched to the high power cluster and slave high power CPUs are gradually brought up. The auto hotplug support is disabled on boot. It can be explicitly enabled via sysfs interface. Original-Change-Id: Ie0e5cf1f334d9c53932db05950cfcf5addd271d7 Reviewed-on: http://git-master/r/18500 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I86152069aa2bed73e0148a4bcab897811e1a5827 Rebase-Id: R9cf5f5f8868c659db526cb49ddf276a79d93ef1a
2011-11-30arm: tegra: Add run-time cluster switch debug controlScott Williams
Allow run-time control of cluster switch debug messages so they can be enabled for debuggability and disabled for performance measurement. Original-Change-Id: Id2bd85d6a9d3a57430a20d93b51ce5b59fe53c71 Reviewed-on: http://git-master/r/17927 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Ia57424eee01276d82af7aab37d2f3d0525acc379 Rebase-Id: Rb7054dcdd910d9f1b82edb485856e868a47c5034
2011-11-30arm: tegra: Instrument cluster switch transitionsScott Williams
Original-Change-Id: I1526de69a1224f42ce3ff11ba1b6fa949c2f13a5 Reviewed-on: http://git-master/r/17787 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I43caec7348d970dc076f27cc2bb4b6ded234a38c Rebase-Id: Ra122021184a1c12cc85e08cd3d7abe41345db058
generated by cgit v1.2.3 (git 2.0.4) at 2025-02-11 02:29:14 +0000