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Bug 1310370
Change-Id: I50b5a0c81500152e9bd0cc8e64f3d9ecbe0782ab
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/268872
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
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This state puts DRAM in self-refresh. It is attached to MC clock
domain, disabled initiallly and will get enabled automatically when
MC clock domain is turned off.
/sys/module/cpuidle_t11x/parameters/stop_mc_clk_in_idle can be used
to control this state.
Bug 1010971
Change-Id: Ia7d70ba1e5a4cdd8ac9cc722de20ed0cd4dabf1a
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/197386
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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As page tables can be outer cacheable we want to keep L2
available while MMU is on. Therefore, upon resuming from power
gating, enable L2 before MMU enable and upon power gating entry
disable L2 after MMU has been disabled. The optimization
is not stable with secure OS so leave the optimization out
for secure OS config. T148 has separate caches so there L2 flush
cannot be avoided. Also the caches are of different size so
the l2x0 module is initialized upon resume.
Bug 1046695
Change-Id: I520db89e880c08113e0b3e29a88efaad0c100045
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/204852
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Rebase-Id: R940fad74c7e91ef3d1d3d589a48064ccb7335541
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Bug 862502
Change-Id: If70e54fb32ce14d5f13dde1d7fb4c1f1499a6722
Reviewed-on: http://git-master/r/47398
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Ra77a54e6930692bca628a97bf1de10a30408cdef
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- Add a single unified handler for all CPU resets that is copied to
IRAM.
- Add state information to direct the flow of execution through the
reset handler based on the reason a CPU was reset.
- Write the EVP CPU reset vector only once per cold/warm boot session.
- Prevent modification of the EVP CPU reset vector in Tegra3.
Bug 786290
Bug 790458
Change-Id: Ica6707f3514986ee914e73a2d9766a4e06ce2d29
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R7b9859a83717e76c3c083bdde724bd5fef9ce089
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This reverts commit d457ef358f3c7179c428becda45b1dfd2b8cf98a.
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
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This supports power-gated idle on secondary CPUs for Tegra30. The
secondary CPUs can go into powered-down state independently. When
CPU goes into this state, it saves it's contexts and puts itself
to flow controlled WFI state. After that, it will been power gated.
Be aware of that, you may see the legacy power state "LP2" in the
code which is exactly the same meaning of "CPU power down".
Based on the work by:
Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prepare the Tegra secondary CPU core bringup code for other Tegra variants.
The reset handler is also generalized to allow for future introduction of
powersaving modes which turn off the CPU cores.
Based on work by:
Scott Williams <scwilliams@nvidia.com>
Chris Johnson <cwj@nvidia.com>
Colin Cross <ccross@android.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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