summaryrefslogtreecommitdiff
path: root/arch/arm/mach-tegra/tegra12_clocks.c
AgeCommit message (Collapse)Author
2014-01-30ARM: tegra12: clock: Notify fast G-CPU rate changesAlex Frid
Added fast G-CPU rate change notification chain. Exposed G-CPU clock for binding with SiMon grader. Bug 1343366 Change-Id: Ida5623884cd152cb388c34283fbe11d458ac818d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/355378 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-30ARM: Tegra: Ardbeg: E1761/TN8: add HDMI settingsAron Wong
Bug 1420213 PLLD2_KCP set to 0 for all HDMI pixel clocks Change-Id: I26b5acbac1dd2b89290857552fb86a4b073fa586 Signed-off-by: Aron Wong <awong@nvidia.com> Reviewed-on: http://git-master/r/356189 (cherry picked from commit 257a568c468b09ce75ae80077c2ced82d4fceacc) Reviewed-on: http://git-master/r/351969 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Jon Mayo <jmayo@nvidia.com>
2014-01-29Arm: tegra12: Add user interface for emc floorPuneet Saxena
Adds node to set min emc clock rate. sysfs(floor rate in Hz, and state for ref counting) /sys/kernel/tegra_emc/emc_floor_rate /sys/kernel/tegra_emc/emc_floor_state PM QoS (freq in kHz): /dev/emc_freq_min Usecase: echo "emc_floor_value" > /dev/emc_freq_min "emc_floor_value": required minimum emc value Bug 1432476 Change-Id: Ib971899f99726e22b9f38f94827b7c9b0ac9ce00 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/361479 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com>
2014-01-27ARM: tegra: Enable -WerrorSumit Singh
Fix warnings in multiple files under mach-tegra and enable -Werror flag to protect further warnings from creeping in. Bug 1438288 Change-Id: Ibdf27605b10f90f13a5dfa1abce16ec153d94114 Signed-off-by: Sumit Singh <sumsingh@nvidia.com> Reviewed-on: http://git-master/r/356554 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com>
2014-01-27ARM: tegra12: clock: Update SPI clock maximum rateAlex Frid
Lowered SPI (Tegra SBC modules) maximum clock rate to 33MHz. Since, this rate can be used at minimum core voltage, removed the respective clock entries from DVFS table. Bug 1342499 Change-Id: I59e3ebf34955f07a6ad15a770e3748f596859838 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/358007 (cherry picked from commit e3491fed48c578910a0356dd500d4faa48b36242) Reviewed-on: http://git-master/r/359530 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-23ARM: tegra12: dvfs: Synchronize soctherm with CL-DVFS rangeAlex Frid
Added callbacks to adjust soctherm cpu zone configuration when CL-DVFS is crossing boundary between high/low voltage ranges. Bug 1363113 Change-Id: Iaa991ffd11b0fe2f34111944252d7ff015481005 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/355875 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2014-01-22ARM: Tegra: T132: Remove LP cluster table access for cpufreqKrishna Sitaraman
Bug 1432739 Bug 1431952 Change-Id: Id55545b4e0001c87b831cf9303c28f7697a14a0f Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/351453 Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-01-21Tegra13: Clocks: Update backup pll for PLLX clock switchingKrishna Sitaraman
Change-Id: Id95afb292b900d039aab0880191288d173283cb1 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Peng Du <pdu@nvidia.com> Reviewed-on: http://git-master/r/345980 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-01-21Tegra13: Clocks: Changes needed for cldvfsKrishna Sitaraman
Change-Id: Ifd658003664c58608e1a8bf9b89c722d269000b7 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Peng Du <pdu@nvidia.com> Reviewed-on: http://git-master/r/345978 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-01-21Tegra13: Clocks: Update PLLX controls to use the CRAB spaceKrishna Sitaraman
PLLX control registers are in Core cluster register space instead of SOC space. Update all register accesses. Change-Id: I6f9a2e043edab996b4556c54290e4449d0dddb15 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Peng Du <pdu@nvidia.com> Reviewed-on: http://git-master/r/345977 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-01-21Tegra13: Clocks: Add cpu clock mux options for T132Krishna Sitaraman
Adding mux input options for the cpu clock and update the base address and ops function accordingly. Change-Id: Ie5c90f0dd71734b61afe29f6fb91520baf080231 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Peng Du <pdu@nvidia.com> Reviewed-on: http://git-master/r/345976 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-01-21Tegra13: Clocks: Remove cpu_lp clocksKrishna Sitaraman
Remove the cpu_lp clocks for T13x. Change-Id: Id1a8f259997689fd907c2201b32082d90f5c0e54 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Peng Du <pdu@nvidia.com> Reviewed-on: http://git-master/r/345975 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-01-21ARM: tegra: fix platform drivers for ARM64Peng Du
Change-Id: I03dae90251ce6c2cf0c0a237ebe0cf53bda9d57d Reviewed-on: http://git-master/r/200297 Reviewed-on: http://git-master/r/225393 Signed-off-by: Peng Du <pdu@nvidia.com>
2014-01-20ARM: tegra: clocks: Handle special clocks initAshwin Joshi
For some clocks, their reset bit is shared with other clocks or they share same register to set source/divider. Before setting such clock at safe rate during init, it is necessary to make sure that all concerned modules are held in reset. Bug 1410210 Change-Id: I47fd7641cbe6c8ba2d63a16ea22f6cb8d5304615 Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com> Reviewed-on: http://git-master/r/353773 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
2014-01-17ARM: tegra: dvfs: Set DFLL clock data in common codeAlex Frid
Set CL-DVFS data for DFLL target clock by CL-DVFS driver probe code (instead of per-chip DFLL clock initialization). Change-Id: I742093570245f6ef97dfdc908c538de6ff4c338e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/356964 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-15ARM: tegra12: clocks: Add new virutal clock.Ashwin Joshi
Add new virtual clock automotive.mselect for automotive board. Bug 1410210 Change-Id: I9b2fe65758b7afcc00424eccb2214ed8faeeba55 Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com> Reviewed-on: http://git-master/r/352596 GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
2014-01-09ARM: tegra12: clock: Allow cbus one-point DVFS tableAlex Frid
Accepted as valid shared cbus DVFS table with only one operational frequency (at least 2 were required before this commit). Change-Id: Iba196a7a3e4ad2b6ab14e6f06da69fc2f8b4622a Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/352540 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-07ARM: tegra12: clock: Add API to enable/disable gpu round pass-thru optionHoang Pham
Add an API to enable/disable gpu round pass-thru option when CONFIG_TEGRA_CLOCK_DEBUG_FUNC set Bug 1409249 Change-Id: Ie9ddd6ce27ab677c56ee378dd867913e05cc1ea1 Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: http://git-master/r/334840 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-07ARM: tegra12: clock: Add gbus round pass-thru optionAlex Frid
Added an option for gbus round operation to simply pass through the requested rate. This option will be enabled only in configuration with CONFIG_TEGRA_CLOCK_DEBUG_FUNC set. In addition reduced gbus rate granularity from 1 MHz to 100 kHz. Bug 1409249 Change-Id: I1e9905b3cf46aae00201995afcecb905d105fade Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/334128 Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-06ARM: tegra: clock: Raise pllx_out0 limit to 1.5GHzAshwin Joshi
Raise pll_x_out0 limit to 1.5 GHz. Bug 1410210 Change-Id: Ie6a106e36212d03b1c6f49dc94e3f56bb3718eb4 Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com> Reviewed-on: http://git-master/r/352194 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
2013-12-30ARM: clock: fix driver name for clk-duplicate of i2cLaxman Dewangan
Change teh driver name of i2c for clock duplicate from tegra14-i2c to tegra12-i2c as the driver name is tegar12-i2c.x. Change-Id: I14a687b5e8c7ffd441656b9031c5fbf95b458787 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/350549
2013-12-30ARM: tegra12: vcm30t124: Set clocks at PORAshwin Joshi
Set the clocks for vcm30t124 at POR value. Bug 1410210 Change-Id: I44fa2b7c1ea300b6f79356e624f49e34c5f2444e Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com> Reviewed-on: http://git-master/r/345716 Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
2013-12-30arm: tegra12: Enable MC holdoff state in resumeTerry Wang
Enable MC holdoff state when system resume from LP0 bug 1407116 Change-Id: Idf3853606fbfb248d0623fc14abeb7c72af72682 Signed-off-by: Terry Wang <terwang@nvidia.com> Reviewed-on: http://git-master/r/335069 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ryane Luo <ryanel@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-12-20ARM: tegra12: clock: Allow PLL_C_OUT1 fractional divisorsAlex Frid
Bug 1342499 Change-Id: Ia805aad58430346d99d82445e8350c5f8ca2c9db Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/346077 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Tested-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-18ARM: Tegra12: DVFS: Raise pll_m ceiling to 1200Sang-Hun Lee
Raise pll_m and emc ceiling to 1200 Mhz Bug 1393328 Change-Id: Ib31cf8fde622ae4949b848d1ef4d731a8d58ca99 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/334786 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-12-17ARM: tegra12: clock: Add memory controller clockAlex Frid
Memory controller clock is a child of EMC clock and it is running at either 1:1 or 1:2 ratio from EMC. MC rate is changing as part of EMC clock scaling only. No direct MC rate control is allowed. Added MC clock to the clock tree for information purpose. Ported from commit 9f8c1aa319ca19a39b56db901326997883fa6f2b Change-Id: Ie4217493355745ba8e0df7129dc08cc7192d3bd6 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/344657 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-11ARM: tegra: Add camera sclk supportSudhir Vyas
Bug 1362112 Change-Id: Ib5abfb92cbbe27430115a1501315e6a6e4f1e300 Signed-off-by: Sudhir Vyas <svyas@nvidia.com> Reviewed-on: http://git-master/r/336133 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2013-12-10ARM: tegr12: clocks: Remove sdmmc3/4 from sclk clientsNaveen Kumar Arepalli
Increasing sclk (ahb clk) won't improve sdmmc perf in T124. In T124, SDMMC became direct MC client. It is no longer on AHB bus. Bug 1416005 Change-Id: I768be41c866b31ceb7a98c2e07d456448c8ad7f2 Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Reviewed-on: http://git-master/r/339736 Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-12-02ARM: tegra12: clock: Convert mselect clock to shared busAlex Frid
Converted mselect clock to bus shared between CPU and PCIE users. Bug 1413311 Change-Id: Ibb34a474021e18cd842627bf66c5f466c5e355f5 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/336457 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-12-02arm: tegra: fix mismatched isp emc clockXue Dong
bug 1407159 Change-Id: I657dde0e7a3df01494adf07a5565fa61b543ec60 Signed-off-by: Xue Dong <xdong@nvidia.com> Reviewed-on: http://git-master/r/336075 Reviewed-by: Chao Xu <cxu@nvidia.com>
2013-11-26ARM: tegra12: clock: Update capping shared usersAlex Frid
- Added cap.vcore.<bus> (bus = emc, c2bus, c3bus, sbus, host1x) users; moved core voltage cap mechanism to these new cap.vcore.<bus> users. Kept for debugging purposes cap.<bus> users that were originally utilized for core voltage capping. - Removed edp capping users on core shared buses (no VDD_CORE EDP limits on Tegra12) Change-Id: Iff7d072beda0bcbb70c16517c470feb72b489b26 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/335332 GVS: Gerrit_Virtual_Submit Reviewed-by: Prashant Malani <pmalani@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-11-18ARM: tegra12: clock: Increase GPU bus max rate to 1.032 GHzAlex Frid
Bug 1342499 Change-Id: I82146d7d656c0b1983dd8a26fc2cb2e94a384290 Signed-off-by: Alex Frid <afrid@nvidia.com> tmp Change-Id: I1f9ec2d688a52307f850a17eda1c3e204f4ae90c Reviewed-on: http://git-master/r/327009 GVS: Gerrit_Virtual_Submit Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-11-13arm: tegra12: clocks: revise max rate of pll_d_out0Adam Jiang
To support panels with higher resolutions, much higher frequencies are required on pll_d_out0. This patch looses the max rate limitation of pll_d_out0. Bug 1387352 Change-Id: I1588c387cb93dfea388caf59899856f8f92fc5da Signed-off-by: Adam Jiang <chaoj@nvidia.com> Reviewed-on: http://git-master/r/328820 GVS: Gerrit_Virtual_Submit Reviewed-by: Chao Xu <cxu@nvidia.com>
2013-11-12ARM: Tegra12: DVFS: Add mselect entry in dvfs tableKrishna Sitaraman
Bug 1342499 Change-Id: I3017b7f23a5552085c39205becc411024f1942a9 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/329043 Reviewed-by: Chao Xu <cxu@nvidia.com> Tested-by: Chao Xu <cxu@nvidia.com>
2013-11-12ARM: tegra12: enable DT support for host1xDeepak Nibade
- make board file changes to enable DT support for host1x - rename clocks to isp.0/vi.0/vic03.0/gk20a.0 to match with device names bug 1366383 Change-Id: I97d8dcf1435c93be9cd81c40f101b645f8073019 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/304871 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2013-11-08arm: tegra12: clocks: fix pll_dp clockKerwin Wan
pll_dp is used for dp and the expected rate is only 270MHz. Change-Id: I99a98ac29a430f9820b4be9088b143e9ff693388 Signed-off-by: Kerwin Wan <kerwinw@nvidia.com> Reviewed-on: http://git-master/r/327995 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chao Xu <cxu@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-11-08ARM: Tegra12: Clocks: Update FCPU dvfs table with 204MhzKrishna Sitaraman
Bug 1342499 Change-Id: Ia1b4012e4b8ee9b511179ca71d4fba06ed13c586 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/326749 Reviewed-by: Chao Xu <cxu@nvidia.com> Tested-by: Chao Xu <cxu@nvidia.com>
2013-11-07ARM: tegra12: clock: add missing sbc clockShreshtha Sahu
This patch adds sbc4.sclk:sbc6.sclk clocks missing in tegra_list_clks[] list. Bug: 1353715 Change-Id: I25ae213d8b1cb7dba88296c9f6bd0e5f3a4c0894 Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com> Reviewed-on: http://git-master/r/326409 GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-11-04ARM: tegra12: clock: Add SDMMC clocks for DDR modeAlex Frid
Defined separate SDMMC clocks for DDR mode. They are associated with the same physical clock controls as HS200 and SDR104 mode clocks but have different max clock limits, and no voltage dependency. Updated SDMMC dvfs tables in HS200/SDR104 mode. Bug 1372817 Bug 1371250 Change-Id: I1ef2b7302003ebdf0bf8145eacf66ceb022eb520 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/298500 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-11-01ARM: Tegra12: Clocks: Update PROD values for PLLC2 and PLLC3Krishna Sitaraman
Update KB, FRM and HYST settings for PLLCX Bug 1339555 Change-Id: If1160b2ce550c8144515e735c50145eca4f0d95a Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/305111 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Chao Xu <cxu@nvidia.com>
2013-10-30ARM: tegra12: clock: Update PLLD 594MHz rate tableKaz Fukuoka
Bug 1339555 Change-Id: I23d804fe93f20df4ecd797f288768f2481b6d1e0 Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com> Reviewed-on: http://git-master/r/298511 Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Chao Xu <cxu@nvidia.com>
2013-10-30ARM: tegra12: clock: fix battery_edp clockTimo Alho
battery_edp clock is constraining the maximum frequency of GPU. On T114 this clock was constraining cbus frequency but on T124 gbus frequency needs to be constrained. This patch fixes the issue. Change-Id: I26b7f6e98a35ef15455773d4d77d41351c9edf0b Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/304864 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2013-10-29Revert "ARM: tegra12: enable DT support for host1x"Terje Bergstrom
This reverts commit 1a48e3a1826b6347b95aa3c1c96ab1c957a240ac. Change-Id: Ibd58be83afadda460b81def37665ab19e95b1693 Reviewed-on: http://git-master/r/304851 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2013-10-29ARM: tegra12: enable DT support for host1xDeepak Nibade
- make board file changes to enable DT support for host1x - rename duplicate ISP clock name to tegra_isp.0 since with DT, device name becomes isp.0 now bug 1366383 Change-Id: I3b8f08c8c52035dfcd019126774c9d1569499d8c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/299483 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2013-10-28ARM: tegra12: clock: Don't clip EMC max rate to boot rateAlex Frid
Don't set EMC maximum rate based on boot rate - let EMC DVFS to determine maximum limit when EMC scaling table is loaded. Change-Id: I0156ded9907fbda2fa6d42eb26d3b4026eeb5848 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/304122 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-28ARM: tegra12: clock: Set non-zero CPU minimum rateAlex Frid
Set minimum 3.1875 MHz rate for both LP and G CPUs on Tegra12. CPU frequency scaling table never go such low, anyway. However, debug interface allows to request any rate, and this request would fail for rates below minimum reachable from backup PLLP at max divider setting (408/128 = 3.1875MHz). Change-Id: Ib9541fb56e0a38e124e7d52c8440cf9867ce6baf Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/304121 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-28ARM: tegra: power: Add dynamic CPU regulator mode controlAlex Frid
Operational mode of CPU voltage regulator depends on load current. Commonly on Tegra platforms this dependency was handled by regulator h/w itself. There are exceptions, however, introduced on some Tegra12 designs that requires s/w control of the mode. In order to dynamically control regulator mode based on load, s/w has to (a) estimate load based on CPU frequency, number of on-line CPU cores, and temperature (b) compare load estimation with regulator specific threshold whenever any of the above factors changes (c) change regulator mode when the respective threshold is crossed This commit adds layer (b) in cpu-tegra driver. It expects existing Tegra CPU load calculator in EDP driver to implement (a), and provide look-up table of frequency thresholds for each combination of on-line CPU cores and temperature ranges. When the respective threshold is crossed standard regulator mode change interface is called to carry on (c). Only switching between IDLE and NORMAL regulator modes is supported. The respective EDP calculator functions are just stubbed, for now. Bug 1302884 Change-Id: Iaea42a101aaea239643c0c80a7ad165ece3b1e36 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/301520 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-24ARM: tegra12: clock: Increase PLLD feedback divider maskAlex Frid
Increased Tegra12 PLLD feedback divider mask to 11 bits (from 10). Bug 1392365 Change-Id: I1ba77801211460bc3f9c9266f46d935de2105e7b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/302121 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-24arm: tegra: tn8: support system edpSeema Khowala
Bug 1345931 Bug 1339832 Change-Id: Ia0a70e2f13c1ef24d9e89b8ec0604ef99c8cd3b4 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-on: http://git-master/r/289981 GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban <mluban@nvidia.com> Tested-by: Mitch Luban <mluban@nvidia.com>
2013-10-23ARM: tegra12: clock: Fix system bus clock roundingKaz Fukuoka
Made sure system bus clock (SCLK) round rate operation follows the same policy on fractional divisors as set rate operation - either both operations allow fractions, or both does not support them (otherwise, clock rate stats are confused). Ported from Tegra11 Change-Id: I3814d66905c01f2ff84b0402be9b9a3d0b113fd6 Change-Id: If4b0eed9be2ce8967c5597ac7471325d0043a38f Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com> Reviewed-on: http://git-master/r/298504 Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chao Xu <cxu@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-29 18:52:31 +0000