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2016-06-29tegra12_clocks.c: fix unusual comparisionMax Krummenacher
newer compilers throw the following error: arch/arm/mach-tegra/tegra12_clocks.c: In function 'tegra12_cpu_clk_init': arch/arm/mach-tegra/tegra12_clocks.c:1334:31: error: logical not is only applied to the left hand side of comparison [-Werror=logical-not-parentheses] c->state = (!is_lp_cluster() == (c->u.cpu.mode == MODE_G))? ON : OFF; Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2015-06-18Revert "mmc: sdhci: tegra: update T2T and Tap hole for VCM30T124"Jeetesh Burman
This reverts commit 28c9354b7cbade8813e0e5dbe9937300219fbeb9. Signed-off-by: Jeetesh Burman <jburman@nvidia.com> Change-Id: I4a809d75523513c939fa17a6dbeebee292aec77b Reviewed-on: http://git-master/r/759472 GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2015-05-04mmc: sdhci: tegra: update T2T and Tap hole for VCM30T124Seshagir.H
bug 200007291 Change-Id: Ia1d8d4c8ea67a30c61e4178863e2f6f1bcb13753 Signed-off-by: Seshagir.H <sholi@nvidia.com> Reviewed-on: http://git-master/r/413049 (cherry picked from commit 7564df85908c98b8fd6e5835cb02262091057d4e) Reviewed-on: http://git-master/r/725517 GVS: Gerrit_Virtual_Submit Reviewed-by: Jeetesh Burman <jburman@nvidia.com> Tested-by: Jeetesh Burman <jburman@nvidia.com> Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2015-01-07media: tegra_v4l2_camera: use port num to init clkBryan Wu
Change clks_init() internal API to use CSI port number to enable clks instead of using dev_id which is incorrect sometime, since vi.0 might also assigned to CSI_B/CSI_C port. Bug 1560636 Change-Id: I0e26308ec885e2e34fe8faa63fca404c911912c4 Signed-off-by: Bryan Wu <pengw@nvidia.com> Reviewed-on: http://git-master/r/539002 Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> (cherry picked from commit c66d8e5880589b0d95dba63d10daff53e47e8628) Reviewed-on: http://git-master/r/665995 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2014-12-17pcie: tegra: boost emc frequency for gen1 and gen2Jeetesh Burman
12MHz frequency for emc is not sufficient in case of high data transfer using PCIE, hence need to increase emc frequency for gen1 and gen2 pcie devices to 102MHz and 508MHz respectively. Bug 1566598 Change-Id: I82c5592dc232ba32eaf6ed959ff78a9966dc6ff1 Signed-off-by: Jeetesh Burman <jburman@nvidia.com> Reviewed-on: http://git-master/r/663267 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Vidya Sagar <vidyas@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2014-12-10arm: tegra12: add support for 0x80 embedded SKUBibek Basu
Added DVFS support for CD575MI SKU 0x80 always on personality CPU DVFS: Max Freq 1912Mhz. Switch to PLLX below 0 DegC and fixed voltage SOC DVFS: Vmax 1000mv constant. Lesser freq below 0 DegC EMC dvfs max freq 792Mhz GPU DVFS: Max Freq 756Mhz and thermal bump up of voltage by 50mv below 0 DegC Bug 1563635 Change-Id: Ifa66f4d9905be120a3534acd8f3ab9c2b58eea37 Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/557951 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2014-10-27arm: t12: clock: Change use_dfll behavioursreenivasulu velpula
- If CONFIG_TEGRA_USE_DFLL_RANGE is set to '3' then do not allow use_dfll sysfs to control dfll range. AND during kernel init also, by default dfll range becomes 0. Bug 1563635 Change-Id: I886a6ca365a1ee0fd7619312eca1ccd17d73222b Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com> Reviewed-on: http://git-master/r/439769 (cherry picked from commit ce3cd984f88d19f5d929c0acbe509486fddcb8bc) Reviewed-on: http://git-master/r/559391 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2014-09-24ARM: tegra12: add clock preinit code for U-BootBryan Wu
U-Boot doesn't setup clock as NVTBoot or fastboot, so clocks need to be preinit before our normal clock init. Bug 1482099 Change-Id: I5ad8dc7e61f1ad4864410a808c41298a91c7198f Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com> Reviewed-on: http://git-master/r/408427 (cherry picked from commit 6682ca58527e47fe6db40855d2deba48a6d321d3) Reviewed-on: http://git-master/r/500873 Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2014-07-31ARM: tegra: clock:Fix Sleeping while atomic in LP0Gaurav Sarode
After enabling CONFIG_DEBUG_ATOMIC_SLEEP,during LP0 we see warning regarding sleep in atomic region for clk_enable and clk_disable. To fix this, we need to use clk_enable_locked and clk_disable_locked instead.These functions do not acquire locks. Bug 1534913 Change-Id: I7ca661a8030308107c3467d9d524c79b6ec374e8 Signed-off-by: Gaurav Sarode <gsarode@nvidia.com> Reviewed-on: http://git-master/r/438904 (cherry picked from commit 908ff199970a093a022f4434afc1689ba979bfed) Reviewed-on: http://git-master/r/440467 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2014-07-16sound: tegra: ahub: add clock settings for T124Bryan Wu
Several additional audio clocks need to be initialized before accessing any audio register, otherwise system will just hard hang. Probably fastboot bootloader initialize these clocks, which actually should be handled in driver. We found this issue for U-Boot bringup. Bug 1482099 Change-Id: Ia7a7c0115bc92a4e98e6f337cf8efc7b2f7a72a0 Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com> Reviewed-on: http://git-master/r/408429 (cherry picked from commit 2929886db14e9d2ac0e75b282126397970fbf9c9) Reviewed-on: http://git-master/r/427929 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
2014-06-26arm: tegra: update vco_min value for pll_xIshwarya Balaji Gururajan
udpate vco_min value for pll_x from 700MHz to 1.2GHz bug 1526834 Change-Id: I5deb14b55e395a3ec964d59ce5dde4d8fabea79b Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com> Reviewed-on: http://git-master/r/427853 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2014-06-16ARM: T132: DVFS: Increase cpu frequency granularity below vminKrishna Sitaraman
Granularity set at 25.5mhz upto 1020Mhz. Bug 1509711 Change-Id: I80d4e78a2c8d1fe995a88ed220b7831b500e162f Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/417245 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2014-06-13arm: tegra: tweak cpu-emc ratioDonghan Ryu
the old cpu-emc ratio is probably not very optimal for newer CPUs with higher max CPU and EMC frequencies. It would be better if have a table of these per CPU architecture but tuning this hard-coded value for now won't make things any worse. Also, much lower CPU_AVG_ACT_THRESHOLD is used for tegra12x and tegra13x Bug 1455015 Bug 1473244 Bug 1497785 Bug 1500639 Bug 1504328 Bug 200004223 Change-Id: I96d4d4d36474c1d7f1d62762666e944fbd04b03e Signed-off-by: Donghan Ryu <dryu@nvidia.com> Reviewed-on: http://git-master/r/411700 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-06-05ARM: T132: DVFS: Cleanup cpufreq table generationKrishna Sitaraman
Also update table framework to easily change frequency granularity below a given frequency. Change-Id: I068f9e04b037e4b12bff422df5364560187ff777 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/414669 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Chao Xu <cxu@nvidia.com>
2014-05-27misc: Align spacing with dev-kernelDan Willemsen
When these changes were integrated, spacing was fixed. Propagate those fixes back to rel-21. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I49102bbf7571a6158fe7c0dd2c4d413ef5462334 Reviewed-on: http://git-master/r/409758 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-05-13arm: tegra: t124: add emc clock for disp laXia Yang
Add new EMC clock for display controller latency allowance Change-Id: Ia73de5b447b2344f9a9c475e9b89a2387cfcc0e0 Signed-off-by: Xia Yang <xiay@nvidia.com> Reviewed-on: http://git-master/r/407158 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2014-05-06ARM: T132: DVFS: Remove cpu/emc frequency dependency beyond A02Krishna Sitaraman
Keep the frequency dependency for A01 and A02 and remove for later revisions. Change-Id: I4220357de960f07aee4eee33f151da4a84ae1987 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Hridya <hvalsaraju@nvidia.com> Reviewed-on: http://git-master/r/401098 Reviewed-by: Chao Xu <cxu@nvidia.com> Reviewed-by: Mitch Luban <mluban@nvidia.com> Tested-by: Mitch Luban <mluban@nvidia.com>
2014-04-23ARM: tegra12: clock: PLLD2 KCP setting changeAron Wong
bug 1483704 Allow setting of SS PLL charge pump depending on clk.u.pll.cpcon_default field value, instead of a single #define shared by all SS PLLs. Affects pll_c4, pll_dp, and pll_d2. Change-Id: I4893c524c13ab321a3c592b9976c8653b2985173 Signed-off-by: Aron Wong <awong@nvidia.com> Reviewed-on: http://git-master/r/389878 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2014-04-23ARM: tegra12: clock: Fix debug print formatAlex Frid
Change-Id: I14fd3b560b9932f6a2b545d16c257993dd7d801b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/397506 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-04-23ARM: T132: Clocks: Increase max freq of sor0 clock to 540mhzKrishna Sitaraman
Bug 1497005 Bug 1442659 Change-Id: I1a70b3746120ec61e64d1ca4522faf4a1e0862fa Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/396660 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Chao Xu <cxu@nvidia.com>
2014-04-22ARM: tegra12: clock: Avoid locking clock list in DFLL late initAlex Frid
DFLL late init is invoked under CPU clock mutex taken, and in turn calls tegra_get_clock_by_name() interface that locks the global tegra clock list. On the other hand, there are several cases of clock list traversing that acquire list mutex, and then lock all individual clocks (including CPU). This created a possibility of AB-BA dead-lock. Fixed by re-arranging DFLL late init to avoid taking clock list mutex. Bug 1502699 Change-Id: I5b2848a616eb2a8a8024096c3537812a04cf43ab Reviewed-on: http://git-master/r/397473 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/398073 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2014-04-09ARM: tegra12: clock: Update PLLC2/3 settingsAlex Frid
- Set VCO range to PROD limits 650MHz/1.3GHz - Increased locking timeout to 360us (x2 of PROD) - Fixed initial post-divider setting - set it to 1 for intended ratio 1:2 (current setting 2 results in 1:3 ratio). - Since new VCOmin is not aligned at reference rate 12MHz boundary, configuration of some close/above VCOmin rates may fail crossing VCOmax limit. Clamp VCO output to maximum in such case instead of failing configuration. Bug 1494125 Change-Id: I23d960a65ee119c0a2dd4597340f700cd1fb897e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/392209 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-04-09ARM: tegra: clock: Don't set PLLE VREG controlsAlex Frid
Kept PLLE VREG controls default state (cleared) to match PROD settings. Bug 1490429 Change-Id: I3f253c968e096685196d24a04d6801eb1b1050ad Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/393597 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-04-08ARM: tegra12: Fix in PLLC2 and PLLC3 initAshwin Joshi
If platform is hypervisor, PLLC2/PLLC3 will have been already enabled. So, don't check the same from Linux in PLL init. Bug 1491546 Change-Id: I9d6a487e1bd6c7e8ff550832014287c42570fa34 Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com>
2014-04-03ARM: tegra: clock: Use DFLL Vmin comparison interfaceAlex Frid
Used DFLL Vmin comparison interface to determine if CPU rail voltage should be increased to account for temperature or SiMon grade change before switching CPU cluster from LP to G. Bug 1343366 Change-Id: I188cd8f7280a5b5361c59b244da6c8a4d729f05d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/391051 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-31ARM: tegra12: clock: Add propagation delay after resetAlex Frid
Added propagation delay after module reset is being asserted/deasserted. Bug 1484343 Change-Id: I34b02018e5e4de5f8d73322d477df6ac2de463d0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/390270 Reviewed-by: Hoang Pham <hopham@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2014-03-27ARM: tegra132: fix CPU clock suspend/resumePeng Du
A subset of the CPU clock registers are managed by Denver and mapped at a separate aperture (0x70040000). For such registers, we need to call clk_(readlx|writelx) which performs the access to the appropriate aperture based on the SOC, given the driver is shared by both T12x and T13x. Bug 1488366 Change-Id: I344179c2626c94d144235814b843a1cb21b502d9 Signed-off-by: Peng Du <pdu@nvidia.com> Reviewed-on: http://git-master/r/387363 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2014-03-25ARM: tegra12: clock: Re-factor posted clock writesAlex Frid
Posted clock writes macros include write to clock control register, read of the same register to flush write operation from CPU through Tegra interconnect buffers, and delay for clock tree propagation. In this commit: - macros are converted to in-line functions to avoid duplicated evaluation of macro arguments for write and read operations - DSB barrier added after read before delay, to avoid partial overlap of read operation and delay (possible, since architectural timer used as delay counter is not MMIO register). Bug 1484343 Bug 1479067 Change-Id: I14463e4907027c9c756d08717dab9b379684ab2c Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/385406 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-25ARM: tegra12: clock: Add read fences for USB clocksAlex Frid
To assure post of the previous writes through Tegra interconnect added read fences in the following USB clock control code paths: - UTMIPLL initialization - XUSB pads IDDQ control Changed the respective read macros to include DSB barrier after read. Bug 1484343 Change-Id: I6a6d1455cd7168a3146361c088f0e242a06654e1 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/385405 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-25ARM: tegra12: clock: Add read fences for external clocksAlex Frid
To assure post of the previous writes through Tegra interconnect added read fences in the following external clock control code paths: - blink clock enable/disable/set rate - clk_out enable/disable/set parent Changed the respective read macros to include DSB barrier after read. Bug 1484343 Change-Id: Ie386851642279859d8a25a4b767f54201ffe692f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/385404 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-17ARM: tegra13: clock: Remove redundant access macrosAlex Frid
Change-Id: I03a5c286a4dc9dec867007b980a1b045f4e14ce1 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/381855 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-17ARM: tegra12: clock: Print info about cXbus clientsAlex Frid
Printed info about cXbus clients left enabled by boot-loader. Change-Id: Ic8a49e74c5f153e846f1058424d9a32d7877a4e4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/345591 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-17ARM: tegra12: clock: Convert bring-up print to debugAlex Frid
Change-Id: I22ed58ebf2cec73ff222c2a9d9ed572252f1a089 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/381784 Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-13ARM: tegra12: clock: Remove PLLD2 duplicate restorationAlex Frid
Removed PLLD2 duplicate restoration. Added debug check for suspend array size. Change-Id: If3cbedc36df3b96e5348aae4c778c53fe32c4883 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/380586 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-13ARM: tegra12: clock: Restore PLLP_OUT5 dividerAlex Frid
Restored PLLP_OUT5 secondary divider after LP0. Bug 1463995 Change-Id: Ia44f048e3a98fc9b8312069917b8bd07e913eb47 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/380581 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-13ARM: tegra: clock: Use exact PLL rate in resumeAlex Frid
Removed 1Hz margin from target rate request during PLL resume. Although the PLL output rate is restored correctly in any case, PLL dividers settings may differ from tabulated targets (if any) when non exact rate is requested. Bug 1479262 Change-Id: I78a338145f8f552b71362fffb1bdb608f620e548 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/380498 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-13ARM: tegra13: clock: Update EMC/CPU clock relationsAlex Frid
Bug 1473244 Change-Id: Ifef039b7a20e99eb262bd6fc098bea6f40b378c8 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/380749 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-11ARM: tegra12: clock: Unify fixed source bus round opsAlex Frid
Unified round operations for shared buses with fixed rate sources: 1x_bus and sbus complex. Change-Id: I191814346e90f19cac3cf52bee3c5d831eed641d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/379748 Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-10ARM: tegra12: clock: Skip thermal voltage changeAlex Frid
Skip unnecessary voltage change during CPU LP=>G cluster switch when DFLL is used as G CPU clock source, and DFLL Vmin is at/above current CPU thermal floor. Change-Id: Icd20b96fe683efc35ec22d4aa0953185a1a17a52 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/364699 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-07ARM: tegra: power: Restore EMC clock client for CPUAlex Frid
This partially reverts commit bd65c015c97c87454e9dc0988485cd4191fe4d0c. It restores EMC clock client created for setting EMC frequency floor due to CPU-to-EMC direct coupling. The application of the restored client is limited to operational requirements - SoC may fail if they are not satisfied. EMC and CPU frequency scaling relations for power and performance optimization still handled via MCCPU actmon device. Tegra13 is the only tegra platform with restored direct CPU-to-EMC scaling dependency. Bug 1473244 Change-Id: Ie1771655cc6b8d304b7050dab141d356971525f8 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/377456 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-05arm: tegra: clocks: Keep pll_d refcnt when bootingJun Yan
pll_d needs to be available during booting to ensure that display doesn't have glitch. Bug 1357901 Bug 1439628 Change-Id: I3d9d375429924fd2e7dbb59f06e89bb18ce46f8c Signed-off-by: Jun Yan <juyan@nvidia.com> Reviewed-on: http://git-master/r/357413 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
2014-03-04ARM: T132: dvfs: Update cldvfs table v4Krishna Sitaraman
Add PLLX based table for A01 and CLDVFS based table for A02 Change-Id: Ibbec5b5d0dc9b43f6e4447791675a7226c732419 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/375803 Reviewed-by: Chao Xu <cxu@nvidia.com>
2014-03-04Revert "ARM: T132: dvfs: Update dfll request ratio for 1st post silicon table"Krishna Sitaraman
This reverts commit 3ed1b1fe808141a2ab08af77a2381d294ff53b1b. Bug 1440923 Change-Id: Ibd92221abdcc60bbacba9639e3f8e232d7dff49f Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/375802 Reviewed-by: Chao Xu <cxu@nvidia.com>
2014-03-03ARM tegra12 clock: Allow change of disabled dividerAlex Frid
Tegra12 supports changing dividers of disabled clocks. Change-Id: Ib5b8e3847368803a383f5516809a4cd37ec836bc Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/367526 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-25ARM: tegra13: clock: Rename CPU super clock opsAlex Frid
Renamed CPU super clock mux operations from tegra13_cpu_clk_* to tegra13_super_cclk_* (cpu_clk_* operations are separate, shared by tegra12 and tegra13 and existing naming was confusing). Updated several comments. Change-Id: I88049f3a4c8eb5ee465fc293f7d77d95a5e387a0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/373330 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-24ARM: tegra13: clock: Fix compiler warningsAlex Frid
Change-Id: I088cfea62afb3cf9329d892330bdf7fe4ce33ff6 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/373260 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-02-20ARM: tegra12: clocks: Add shared clock for host1xAshwin Joshi
Add a new shared clock for host1x. This will be used by automotive to keep host1x fixed at required target rate. Bug 1452008 Bug 1410210 Change-Id: Ie31d80f923acc9c0e1521564cc5fdfd43b6bf191 Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com> Reviewed-on: http://git-master/r/369174 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
2014-02-10ARM: T132: T12x: Clocks: Add SS setting for PLL_DPKrishna Sitaraman
Add spread spectrum settings for PLL_DP Bug 1406417 Bug 1382354 Change-Id: I3d9f4b264315e1f9e69c2733c3d01b2ea44c568f Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/362148 Reviewed-by: Chao Xu <cxu@nvidia.com> Tested-by: Chao Xu <cxu@nvidia.com>
2014-02-09ARM: T132: dvfs: Update dfll request ratio for 1st post silicon tableKrishna Sitaraman
DFLL VCO will run at twice the requested frequency and clk divider will be set to 2 to match the requested value. This change to be removed after proper DFLL settings are available for T132. Bug 1440923 Change-Id: I89c49d11677831677a385a0c4ef2d9bee4761693 Reviewed-on: http://git-master/r/354033 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/361711 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Tested-by: Seema Khowala <seemaj@nvidia.com>
2014-02-04ARM: T132: Clocks: Update PLLDP initialization routineKrishna Sitaraman
If BootLoader initialized PLLDP skip re-initilization. Bug 1439061 Change-Id: I0e188b20febf4e81f9442c60a3c304d5c13cf466 Reviewed-on: http://git-master/r/355589 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-on: http://git-master/r/361694 Reviewed-by: Seema Khowala <seemaj@nvidia.com> Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-27 02:52:37 +0000