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Add support for derating via keeping two separate sets of EMC tables.
One set is nominal, the other set is derated. Based on the temperature
reported by the DRAM the EMC thermal driver can specify which set of
tables the EMC driver should use when swapping frequencies.
This patch also adds support for a more graduated response to rising
temperature. The DRAM reports 3 levels of refresh and derating
requirements:
0x4: Refresh x2
0x5: Refresh x4
0x6: Refresh x4 + derating
The particular combination of refresh modification and derating is now
picked based on the particular level of throttling necessary.
Also, this adds the ability to control certain DRAM
timing parameters like refresh rate based on over
temp status and ddd ISO efficiency table for POP package
Bug 1436864
Reviewed-on: http://git-master/r/#/c/377913/
Change-Id: Ibfa5820436459029f6a0f8c0980b5ad3297d5ec7
Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
Reviewed-on: http://git-master/r/375058
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>
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Add function to query the DVFS clock change latency value. This value
is used in latency allowance calculations.
Bug 1327082
Change-Id: Idd4ab0eeb405828903b591aebcf17f7ad06d675a
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/379104
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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There are two tegra_emc.h files; this patch renames the platform
data header to "tegra_emc_pdata.h" to avoid confusion.
Change-Id: I8160682823ec4fcb7c9a883bfc10285d3cc91551
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/376788
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
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Move the core EMC header to a common location. This allows different
sources to include it without the annoying "../../" type stuff.
Change-Id: I57d2d35e1961eca23d7dd69c2634e8e9af52d4b1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/376787
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
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Disable MC Holdoff for HYST_VDETPER, HYST_VDEMCER, HYST_VDEMBER,
HYST_VDEBSEVR, HYST_MSENCSRD, HYST_ISPRAB, HYST_ISPRA, HYST_VICSRD
Correct some incorrect clients name definitions
Bug 1440582
Change-Id: I0b50668218051a060062b565f82e45abff82d875
Signed-off-by: Terry Wang <terwang@nvidia.com>
Reviewed-on: http://git-master/r/369254
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Add definitions of MC Holdoff state related registers/function
for T124
Bug 1407116
Change-Id: Ifad5a01e8d6f6433bc459e014304a9510c535d8c
Signed-off-by: Terry Wang <terwang@nvidia.com>
Reviewed-on: http://git-master/r/335065
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ryane Luo <ryanel@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Change-Id: I0739f559e805c0c65d54f6488e86b09c0e581052
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/337574
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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- Change 3906be deprecated 0x16 support
- Not all EMC tables are 0x18. Revert this change
until we have all tables in 0x18 version
This reverts commit 3906be6667d8f7770d344edca2b22de38d29677b.
Change-Id: I8229ce543c7795057055df032603bc1d44751041
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/336436
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
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Change-Id: I0f07977520f5ffa6b646e368f2844e6b56d878fc
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/305051
Tested-by: Mitch Luban <mluban@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>
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Adds functionality to load the EMC table from the NCT
partition. If no memory table is in NCT or the NCT
partition doesn't exist, fall back to the built-in table.
Bug 1300925
Change-Id: I09c13443600c987884f67520ca72a7702e052837
Signed-off-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com>
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/289290
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
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bug 1348140
Change-Id: I121d002b947f2ac2d7a15624b499173b17e9e893
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/299043
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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bug 1343186
Change-Id: Ia94f35d8a8f117862b8ea44c2e77d25940ece3ca
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/263585
Reviewed-by: Chao Xu <cxu@nvidia.com>
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Unlike T3 and T114, MC latency allowance registers on T124+ are
not in a contiguous MMIO range anymore, which is fixed by this
change. This change also updated the latency allowance register
definitions based on T124's HW spec.
Bug 1289211
Change-Id: I225d1956f669c1efcebce0442856a8d28a692bef
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/242508
Reviewed-by: Adeel Raza <araza@nvidia.com>
Tested-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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bug 1171013
Change-Id: Iaad24b9326e78fdd19c26f655c0412407d2368de
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/242139
Reviewed-by: Chao Xu <cxu@nvidia.com>
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Change-Id: Ie39ab61908c729e9c8ffd658f52ac6b5f7e7cb71
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/203999
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
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Change-Id: I42cdb350ba9c7380a1a3dbcce78951811cc6b9a2
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/203356
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
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Change-Id: Iee70053fff3a63fe56c76363289834c0e5d7165b
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Tested-by: Ken Adams <kadams@nvidia.com>
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/82934
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Mark Stadler <mastadler@nvidia.com>
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